1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26/// CCIfIsVarArgOnWin - Match if isVarArg on Windows 32bits. 27class CCIfIsVarArgOnWin<CCAction A> 28 : CCIf<"State.isVarArg() && " 29 "State.getMachineFunction().getSubtarget().getTargetTriple()." 30 "isWindowsMSVCEnvironment()", 31 A>; 32 33// Register classes for RegCall 34class RC_X86_RegCall { 35 list<Register> GPR_8 = []; 36 list<Register> GPR_16 = []; 37 list<Register> GPR_32 = []; 38 list<Register> GPR_64 = []; 39 list<Register> FP_CALL = [FP0]; 40 list<Register> FP_RET = [FP0, FP1]; 41 list<Register> XMM = []; 42 list<Register> YMM = []; 43 list<Register> ZMM = []; 44} 45 46// RegCall register classes for 32 bits 47def RC_X86_32_RegCall : RC_X86_RegCall { 48 let GPR_8 = [AL, CL, DL, DIL, SIL]; 49 let GPR_16 = [AX, CX, DX, DI, SI]; 50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 51 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 52 ///< \todo Fix AssignToReg to enable empty lists 53 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 55 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 56} 57 58class RC_X86_64_RegCall : RC_X86_RegCall { 59 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 60 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 61 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 62 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 63 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 64 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 65} 66 67def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 72} 73 74def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 75 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 76 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 77 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 78 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 79} 80 81// X86-64 Intel regcall calling convention. 82multiclass X86_RegCall_base<RC_X86_RegCall RC> { 83def CC_#NAME : CallingConv<[ 84 // Handles byval parameters. 85 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 86 CCIfByVal<CCPassByVal<4, 4>>, 87 88 // Promote i1/i8/i16/v1i1 arguments to i32. 89 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 90 91 // Promote v8i1/v16i1/v32i1 arguments to i32. 92 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 93 94 // bool, char, int, enum, long, pointer --> GPR 95 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 96 97 // long long, __int64 --> GPR 98 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 99 100 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 101 CCIfType<[v64i1], CCPromoteToType<i64>>, 102 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 103 CCAssignToReg<RC.GPR_64>>>, 104 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 105 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 106 107 // float, double, float128 --> XMM 108 // In the case of SSE disabled --> save to stack 109 CCIfType<[f32, f64, f128], 110 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 111 112 // long double --> FP 113 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 114 115 // __m128, __m128i, __m128d --> XMM 116 // In the case of SSE disabled --> save to stack 117 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 118 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 119 120 // __m256, __m256i, __m256d --> YMM 121 // In the case of SSE disabled --> save to stack 122 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 123 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 124 125 // __m512, __m512i, __m512d --> ZMM 126 // In the case of SSE disabled --> save to stack 127 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 128 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 129 130 // If no register was found -> assign to stack 131 132 // In 64 bit, assign 64/32 bit values to 8 byte stack 133 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 134 CCAssignToStack<8, 8>>>, 135 136 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 137 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 138 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 139 140 // MMX type gets 8 byte slot in stack , while alignment depends on target 141 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 142 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 143 144 // float 128 get stack slots whose size and alignment depends 145 // on the subtarget. 146 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 147 148 // Vectors get 16-byte stack slots that are 16-byte aligned. 149 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 150 CCAssignToStack<16, 16>>, 151 152 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 154 CCAssignToStack<32, 32>>, 155 156 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 157 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 158 CCAssignToStack<64, 64>> 159]>; 160 161def RetCC_#NAME : CallingConv<[ 162 // Promote i1, v1i1, v8i1 arguments to i8. 163 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 164 165 // Promote v16i1 arguments to i16. 166 CCIfType<[v16i1], CCPromoteToType<i16>>, 167 168 // Promote v32i1 arguments to i32. 169 CCIfType<[v32i1], CCPromoteToType<i32>>, 170 171 // bool, char, int, enum, long, pointer --> GPR 172 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 173 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 174 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 175 176 // long long, __int64 --> GPR 177 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 178 179 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 180 CCIfType<[v64i1], CCPromoteToType<i64>>, 181 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 182 CCAssignToReg<RC.GPR_64>>>, 183 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 184 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 185 186 // long double --> FP 187 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 188 189 // float, double, float128 --> XMM 190 CCIfType<[f32, f64, f128], 191 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 192 193 // __m128, __m128i, __m128d --> XMM 194 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 195 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 196 197 // __m256, __m256i, __m256d --> YMM 198 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 199 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 200 201 // __m512, __m512i, __m512d --> ZMM 202 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 203 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 204]>; 205} 206 207//===----------------------------------------------------------------------===// 208// Return Value Calling Conventions 209//===----------------------------------------------------------------------===// 210 211// Return-value conventions common to all X86 CC's. 212def RetCC_X86Common : CallingConv<[ 213 // Scalar values are returned in AX first, then DX. For i8, the ABI 214 // requires the values to be in AL and AH, however this code uses AL and DL 215 // instead. This is because using AH for the second register conflicts with 216 // the way LLVM does multiple return values -- a return of {i16,i8} would end 217 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 218 // for functions that return two i8 values are currently expected to pack the 219 // values into an i16 (which uses AX, and thus AL:AH). 220 // 221 // For code that doesn't care about the ABI, we allow returning more than two 222 // integer values in registers. 223 CCIfType<[v1i1], CCPromoteToType<i8>>, 224 CCIfType<[i1], CCPromoteToType<i8>>, 225 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 226 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 227 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 228 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 229 230 // Boolean vectors of AVX-512 are returned in SIMD registers. 231 // The call from AVX to AVX-512 function should work, 232 // since the boolean types in AVX/AVX2 are promoted by default. 233 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 234 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 235 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 236 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 237 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 238 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 239 240 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 241 // can only be used by ABI non-compliant code. If the target doesn't have XMM 242 // registers, it won't have vector types. 243 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 244 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 245 246 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 247 // can only be used by ABI non-compliant code. This vector type is only 248 // supported while using the AVX target feature. 249 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 250 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 251 252 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 253 // can only be used by ABI non-compliant code. This vector type is only 254 // supported while using the AVX-512 target feature. 255 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 256 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 257 258 // MMX vector types are always returned in MM0. If the target doesn't have 259 // MM0, it doesn't support these vector types. 260 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 261 262 // Long double types are always returned in FP0 (even with SSE), 263 // except on Win64. 264 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 265]>; 266 267// X86-32 C return-value convention. 268def RetCC_X86_32_C : CallingConv<[ 269 // The X86-32 calling convention returns FP values in FP0, unless marked 270 // with "inreg" (used here to distinguish one kind of reg from another, 271 // weirdly; this is really the sse-regparm calling convention) in which 272 // case they use XMM0, otherwise it is the same as the common X86 calling 273 // conv. 274 CCIfInReg<CCIfSubtarget<"hasSSE2()", 275 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 276 CCIfSubtarget<"hasX87()", 277 CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>, 278 CCIfNotSubtarget<"hasX87()", 279 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>, 280 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>, 281 CCDelegateTo<RetCC_X86Common> 282]>; 283 284// X86-32 FastCC return-value convention. 285def RetCC_X86_32_Fast : CallingConv<[ 286 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 287 // SSE2. 288 // This can happen when a float, 2 x float, or 3 x float vector is split by 289 // target lowering, and is returned in 1-3 sse regs. 290 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 291 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 292 293 // For integers, ECX can be used as an extra return register 294 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 295 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 296 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 297 298 // Otherwise, it is the same as the common X86 calling convention. 299 CCDelegateTo<RetCC_X86Common> 300]>; 301 302// Intel_OCL_BI return-value convention. 303def RetCC_Intel_OCL_BI : CallingConv<[ 304 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 305 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 306 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 307 308 // 256-bit FP vectors 309 // No more than 4 registers 310 CCIfType<[v8f32, v4f64, v8i32, v4i64], 311 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 312 313 // 512-bit FP vectors 314 CCIfType<[v16f32, v8f64, v16i32, v8i64], 315 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 316 317 // i32, i64 in the standard way 318 CCDelegateTo<RetCC_X86Common> 319]>; 320 321// X86-32 HiPE return-value convention. 322def RetCC_X86_32_HiPE : CallingConv<[ 323 // Promote all types to i32 324 CCIfType<[i8, i16], CCPromoteToType<i32>>, 325 326 // Return: HP, P, VAL1, VAL2 327 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 328]>; 329 330// X86-32 Vectorcall return-value convention. 331def RetCC_X86_32_VectorCall : CallingConv<[ 332 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 333 CCIfType<[f32, f64, f128], 334 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 335 336 // Return integers in the standard way. 337 CCDelegateTo<RetCC_X86Common> 338]>; 339 340// X86-64 C return-value convention. 341def RetCC_X86_64_C : CallingConv<[ 342 // The X86-64 calling convention always returns FP values in XMM0. 343 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>, 344 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 345 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 346 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 347 348 // MMX vector types are always returned in XMM0. 349 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 350 351 // Pointers are always returned in full 64-bit registers. 352 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 353 354 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 355 356 CCDelegateTo<RetCC_X86Common> 357]>; 358 359// X86-Win64 C return-value convention. 360def RetCC_X86_Win64_C : CallingConv<[ 361 // The X86-Win64 calling convention always returns __m64 values in RAX. 362 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 363 364 // GCC returns FP values in RAX on Win64. 365 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 366 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 367 368 // Otherwise, everything is the same as 'normal' X86-64 C CC. 369 CCDelegateTo<RetCC_X86_64_C> 370]>; 371 372// X86-64 vectorcall return-value convention. 373def RetCC_X86_64_Vectorcall : CallingConv<[ 374 // Vectorcall calling convention always returns FP values in XMMs. 375 CCIfType<[f32, f64, f128], 376 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 377 378 // Otherwise, everything is the same as Windows X86-64 C CC. 379 CCDelegateTo<RetCC_X86_Win64_C> 380]>; 381 382// X86-64 HiPE return-value convention. 383def RetCC_X86_64_HiPE : CallingConv<[ 384 // Promote all types to i64 385 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 386 387 // Return: HP, P, VAL1, VAL2 388 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 389]>; 390 391// X86-64 WebKit_JS return-value convention. 392def RetCC_X86_64_WebKit_JS : CallingConv<[ 393 // Promote all types to i64 394 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 395 396 // Return: RAX 397 CCIfType<[i64], CCAssignToReg<[RAX]>> 398]>; 399 400def RetCC_X86_64_Swift : CallingConv<[ 401 402 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 403 404 // For integers, ECX, R8D can be used as extra return registers. 405 CCIfType<[v1i1], CCPromoteToType<i8>>, 406 CCIfType<[i1], CCPromoteToType<i8>>, 407 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 408 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 409 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 410 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 411 412 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 413 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 414 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 415 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 416 417 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 418 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 419 CCDelegateTo<RetCC_X86Common> 420]>; 421 422// X86-64 AnyReg return-value convention. No explicit register is specified for 423// the return-value. The register allocator is allowed and expected to choose 424// any free register. 425// 426// This calling convention is currently only supported by the stackmap and 427// patchpoint intrinsics. All other uses will result in an assert on Debug 428// builds. On Release builds we fallback to the X86 C calling convention. 429def RetCC_X86_64_AnyReg : CallingConv<[ 430 CCCustom<"CC_X86_AnyReg_Error"> 431]>; 432 433 434defm X86_32_RegCall : 435 X86_RegCall_base<RC_X86_32_RegCall>; 436defm X86_Win64_RegCall : 437 X86_RegCall_base<RC_X86_64_RegCall_Win>; 438defm X86_SysV64_RegCall : 439 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 440 441// This is the root return-value convention for the X86-32 backend. 442def RetCC_X86_32 : CallingConv<[ 443 // If FastCC, use RetCC_X86_32_Fast. 444 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 445 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 446 // CFGuard_Check never returns a value so does not need a RetCC. 447 // If HiPE, use RetCC_X86_32_HiPE. 448 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 449 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 450 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 451 452 // Otherwise, use RetCC_X86_32_C. 453 CCDelegateTo<RetCC_X86_32_C> 454]>; 455 456// This is the root return-value convention for the X86-64 backend. 457def RetCC_X86_64 : CallingConv<[ 458 // HiPE uses RetCC_X86_64_HiPE 459 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 460 461 // Handle JavaScript calls. 462 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 463 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 464 465 // Handle Swift calls. 466 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 467 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>, 468 469 // Handle explicit CC selection 470 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 471 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 472 473 // Handle Vectorcall CC 474 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 475 476 CCIfCC<"CallingConv::X86_RegCall", 477 CCIfSubtarget<"isTargetWin64()", 478 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 479 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 480 481 // Mingw64 and native Win64 use Win64 CC 482 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 483 484 // Otherwise, drop to normal X86-64 CC 485 CCDelegateTo<RetCC_X86_64_C> 486]>; 487 488// This is the return-value convention used for the entire X86 backend. 489let Entry = 1 in 490def RetCC_X86 : CallingConv<[ 491 492 // Check if this is the Intel OpenCL built-ins calling convention 493 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 494 495 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 496 CCDelegateTo<RetCC_X86_32> 497]>; 498 499//===----------------------------------------------------------------------===// 500// X86-64 Argument Calling Conventions 501//===----------------------------------------------------------------------===// 502 503def CC_X86_64_C : CallingConv<[ 504 // Handles byval parameters. 505 CCIfByVal<CCPassByVal<8, 8>>, 506 507 // Promote i1/i8/i16/v1i1 arguments to i32. 508 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 509 510 // The 'nest' parameter, if any, is passed in R10. 511 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 512 CCIfNest<CCAssignToReg<[R10]>>, 513 514 // Pass SwiftSelf in a callee saved register. 515 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 516 517 // A SwiftError is passed in R12. 518 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 519 520 // Pass SwiftAsync in an otherwise callee saved register so that calls to 521 // normal functions don't need to save it somewhere. 522 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 523 524 // For Swift Calling Conventions, pass sret in %rax. 525 CCIfCC<"CallingConv::Swift", 526 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 527 CCIfCC<"CallingConv::SwiftTail", 528 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 529 530 // Pointers are always passed in full 64-bit registers. 531 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 532 533 // The first 6 integer arguments are passed in integer registers. 534 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 535 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 536 537 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 538 CCIfType<[x86mmx], 539 CCIfSubtarget<"isTargetDarwin()", 540 CCIfSubtarget<"hasSSE2()", 541 CCPromoteToType<v2i64>>>>, 542 543 // Boolean vectors of AVX-512 are passed in SIMD registers. 544 // The call from AVX to AVX-512 function should work, 545 // since the boolean types in AVX/AVX2 are promoted by default. 546 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 547 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 548 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 549 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 550 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 551 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 552 553 // The first 8 FP/Vector arguments are passed in XMM registers. 554 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 555 CCIfSubtarget<"hasSSE1()", 556 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 557 558 // The first 8 256-bit vector arguments are passed in YMM registers, unless 559 // this is a vararg function. 560 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 561 // fixed arguments to vararg functions are supposed to be passed in 562 // registers. Actually modeling that would be a lot of work, though. 563 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 564 CCIfSubtarget<"hasAVX()", 565 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 566 YMM4, YMM5, YMM6, YMM7]>>>>, 567 568 // The first 8 512-bit vector arguments are passed in ZMM registers. 569 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 570 CCIfSubtarget<"hasAVX512()", 571 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 572 573 // Integer/FP values get stored in stack slots that are 8 bytes in size and 574 // 8-byte aligned if there are no more registers to hold them. 575 CCIfType<[i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>, 576 577 // Long doubles get stack slots whose size and alignment depends on the 578 // subtarget. 579 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 580 581 // Vectors get 16-byte stack slots that are 16-byte aligned. 582 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCAssignToStack<16, 16>>, 583 584 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 585 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 586 CCAssignToStack<32, 32>>, 587 588 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 589 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 590 CCAssignToStack<64, 64>> 591]>; 592 593// Calling convention used on Win64 594def CC_X86_Win64_C : CallingConv<[ 595 // FIXME: Handle varargs. 596 597 // Byval aggregates are passed by pointer 598 CCIfByVal<CCPassIndirect<i64>>, 599 600 // Promote i1/v1i1 arguments to i8. 601 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 602 603 // The 'nest' parameter, if any, is passed in R10. 604 CCIfNest<CCAssignToReg<[R10]>>, 605 606 // A SwiftError is passed in R12. 607 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 608 609 // Pass SwiftSelf in a callee saved register. 610 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 611 612 // Pass SwiftAsync in an otherwise callee saved register so that calls to 613 // normal functions don't need to save it somewhere. 614 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 615 616 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 617 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 618 619 // 128 bit vectors are passed by pointer 620 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>, 621 622 // 256 bit vectors are passed by pointer 623 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>, 624 625 // 512 bit vectors are passed by pointer 626 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 627 628 // Long doubles are passed by pointer 629 CCIfType<[f80], CCPassIndirect<i64>>, 630 631 // The first 4 MMX vector arguments are passed in GPRs. 632 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 633 634 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 635 // GPRs or on the stack. 636 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 637 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 638 639 // The first 4 FP/Vector arguments are passed in XMM registers. 640 CCIfType<[f16, f32, f64], 641 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 642 [RCX , RDX , R8 , R9 ]>>, 643 644 // The first 4 integer arguments are passed in integer registers. 645 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 646 [XMM0, XMM1, XMM2, XMM3]>>, 647 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 648 [XMM0, XMM1, XMM2, XMM3]>>, 649 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 650 [XMM0, XMM1, XMM2, XMM3]>>, 651 652 // Do not pass the sret argument in RCX, the Win64 thiscall calling 653 // convention requires "this" to be passed in RCX. 654 CCIfCC<"CallingConv::X86_ThisCall", 655 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 656 [XMM1, XMM2, XMM3]>>>>, 657 658 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 659 [XMM0, XMM1, XMM2, XMM3]>>, 660 661 // Integer/FP values get stored in stack slots that are 8 bytes in size and 662 // 8-byte aligned if there are no more registers to hold them. 663 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> 664]>; 665 666def CC_X86_Win64_VectorCall : CallingConv<[ 667 CCCustom<"CC_X86_64_VectorCall">, 668 669 // Delegate to fastcall to handle integer types. 670 CCDelegateTo<CC_X86_Win64_C> 671]>; 672 673 674def CC_X86_64_GHC : CallingConv<[ 675 // Promote i8/i16/i32 arguments to i64. 676 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 677 678 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 679 CCIfType<[i64], 680 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 681 682 // Pass in STG registers: F1, F2, F3, F4, D1, D2 683 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 684 CCIfSubtarget<"hasSSE1()", 685 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 686 // AVX 687 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 688 CCIfSubtarget<"hasAVX()", 689 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 690 // AVX-512 691 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 692 CCIfSubtarget<"hasAVX512()", 693 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 694]>; 695 696def CC_X86_64_HiPE : CallingConv<[ 697 // Promote i8/i16/i32 arguments to i64. 698 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 699 700 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 701 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 702 703 // Integer/FP values get stored in stack slots that are 8 bytes in size and 704 // 8-byte aligned if there are no more registers to hold them. 705 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 706]>; 707 708def CC_X86_64_WebKit_JS : CallingConv<[ 709 // Promote i8/i16 arguments to i32. 710 CCIfType<[i8, i16], CCPromoteToType<i32>>, 711 712 // Only the first integer argument is passed in register. 713 CCIfType<[i32], CCAssignToReg<[EAX]>>, 714 CCIfType<[i64], CCAssignToReg<[RAX]>>, 715 716 // The remaining integer arguments are passed on the stack. 32bit integer and 717 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 718 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 719 // in 8 byte stack slots. 720 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 721 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 722]>; 723 724// No explicit register is specified for the AnyReg calling convention. The 725// register allocator may assign the arguments to any free register. 726// 727// This calling convention is currently only supported by the stackmap and 728// patchpoint intrinsics. All other uses will result in an assert on Debug 729// builds. On Release builds we fallback to the X86 C calling convention. 730def CC_X86_64_AnyReg : CallingConv<[ 731 CCCustom<"CC_X86_AnyReg_Error"> 732]>; 733 734//===----------------------------------------------------------------------===// 735// X86 C Calling Convention 736//===----------------------------------------------------------------------===// 737 738/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 739/// values are spilled on the stack. 740def CC_X86_32_Vector_Common : CallingConv<[ 741 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 742 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 743 CCAssignToStack<16, 16>>, 744 745 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 746 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 747 CCAssignToStack<32, 32>>, 748 749 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 750 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 751 CCAssignToStack<64, 64>> 752]>; 753 754/// CC_X86_Win32_Vector - In X86 Win32 calling conventions, extra vector 755/// values are spilled on the stack. 756def CC_X86_Win32_Vector : CallingConv<[ 757 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned. 758 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 759 CCAssignToStack<16, 4>>, 760 761 // 256-bit AVX vectors get 32-byte stack slots that are 4-byte aligned. 762 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 763 CCAssignToStack<32, 4>>, 764 765 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 4-byte aligned. 766 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 767 CCAssignToStack<64, 4>> 768]>; 769 770// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 771// vector registers 772def CC_X86_32_Vector_Standard : CallingConv<[ 773 // SSE vector arguments are passed in XMM registers. 774 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 775 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 776 777 // AVX 256-bit vector arguments are passed in YMM registers. 778 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 779 CCIfSubtarget<"hasAVX()", 780 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 781 782 // AVX 512-bit vector arguments are passed in ZMM registers. 783 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 784 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 785 786 CCIfIsVarArgOnWin<CCDelegateTo<CC_X86_Win32_Vector>>, 787 CCDelegateTo<CC_X86_32_Vector_Common> 788]>; 789 790// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 791// vector registers. 792def CC_X86_32_Vector_Darwin : CallingConv<[ 793 // SSE vector arguments are passed in XMM registers. 794 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 795 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 796 797 // AVX 256-bit vector arguments are passed in YMM registers. 798 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 799 CCIfSubtarget<"hasAVX()", 800 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 801 802 // AVX 512-bit vector arguments are passed in ZMM registers. 803 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 804 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 805 806 CCDelegateTo<CC_X86_32_Vector_Common> 807]>; 808 809/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 810/// values are spilled on the stack. 811def CC_X86_32_Common : CallingConv<[ 812 // Handles byval/preallocated parameters. 813 CCIfByVal<CCPassByVal<4, 4>>, 814 CCIfPreallocated<CCPassByVal<4, 4>>, 815 816 // The first 3 float or double arguments, if marked 'inreg' and if the call 817 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 818 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 819 CCIfSubtarget<"hasSSE2()", 820 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 821 822 CCIfNotVarArg<CCIfInReg<CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 823 824 // The first 3 __m64 vector arguments are passed in mmx registers if the 825 // call is not a vararg call. 826 CCIfNotVarArg<CCIfType<[x86mmx], 827 CCAssignToReg<[MM0, MM1, MM2]>>>, 828 829 CCIfType<[f16], CCAssignToStack<4, 4>>, 830 831 // Integer/Float values get stored in stack slots that are 4 bytes in 832 // size and 4-byte aligned. 833 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 834 835 // Doubles get 8-byte slots that are 4-byte aligned. 836 CCIfType<[f64], CCAssignToStack<8, 4>>, 837 838 // Long doubles get slots whose size and alignment depends on the subtarget. 839 CCIfType<[f80], CCAssignToStack<0, 0>>, 840 841 // Boolean vectors of AVX-512 are passed in SIMD registers. 842 // The call from AVX to AVX-512 function should work, 843 // since the boolean types in AVX/AVX2 are promoted by default. 844 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 845 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 846 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 847 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 848 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 849 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 850 851 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 852 // passed in the parameter area. 853 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 854 855 // Darwin passes vectors in a form that differs from the i386 psABI 856 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 857 858 // Otherwise, drop to 'normal' X86-32 CC 859 CCDelegateTo<CC_X86_32_Vector_Standard> 860]>; 861 862def CC_X86_32_C : CallingConv<[ 863 // Promote i1/i8/i16/v1i1 arguments to i32. 864 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 865 866 // The 'nest' parameter, if any, is passed in ECX. 867 CCIfNest<CCAssignToReg<[ECX]>>, 868 869 // On swifttailcc pass swiftself in ECX. 870 CCIfCC<"CallingConv::SwiftTail", 871 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>, 872 873 // The first 3 integer arguments, if marked 'inreg' and if the call is not 874 // a vararg call, are passed in integer registers. 875 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 876 877 // Otherwise, same as everything else. 878 CCDelegateTo<CC_X86_32_Common> 879]>; 880 881def CC_X86_32_MCU : CallingConv<[ 882 // Handles byval parameters. Note that, like FastCC, we can't rely on 883 // the delegation to CC_X86_32_Common because that happens after code that 884 // puts arguments in registers. 885 CCIfByVal<CCPassByVal<4, 4>>, 886 887 // Promote i1/i8/i16/v1i1 arguments to i32. 888 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 889 890 // If the call is not a vararg call, some arguments may be passed 891 // in integer registers. 892 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 893 894 // Otherwise, same as everything else. 895 CCDelegateTo<CC_X86_32_Common> 896]>; 897 898def CC_X86_32_FastCall : CallingConv<[ 899 // Promote i1 to i8. 900 CCIfType<[i1], CCPromoteToType<i8>>, 901 902 // The 'nest' parameter, if any, is passed in EAX. 903 CCIfNest<CCAssignToReg<[EAX]>>, 904 905 // The first 2 integer arguments are passed in ECX/EDX 906 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 907 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 908 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 909 910 // Otherwise, same as everything else. 911 CCDelegateTo<CC_X86_32_Common> 912]>; 913 914def CC_X86_Win32_VectorCall : CallingConv<[ 915 // Pass floating point in XMMs 916 CCCustom<"CC_X86_32_VectorCall">, 917 918 // Delegate to fastcall to handle integer types. 919 CCDelegateTo<CC_X86_32_FastCall> 920]>; 921 922def CC_X86_32_ThisCall_Common : CallingConv<[ 923 // The first integer argument is passed in ECX 924 CCIfType<[i32], CCAssignToReg<[ECX]>>, 925 926 // Otherwise, same as everything else. 927 CCDelegateTo<CC_X86_32_Common> 928]>; 929 930def CC_X86_32_ThisCall_Mingw : CallingConv<[ 931 // Promote i1/i8/i16/v1i1 arguments to i32. 932 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 933 934 CCDelegateTo<CC_X86_32_ThisCall_Common> 935]>; 936 937def CC_X86_32_ThisCall_Win : CallingConv<[ 938 // Promote i1/i8/i16/v1i1 arguments to i32. 939 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 940 941 // Pass sret arguments indirectly through stack. 942 CCIfSRet<CCAssignToStack<4, 4>>, 943 944 CCDelegateTo<CC_X86_32_ThisCall_Common> 945]>; 946 947def CC_X86_32_ThisCall : CallingConv<[ 948 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 949 CCDelegateTo<CC_X86_32_ThisCall_Win> 950]>; 951 952def CC_X86_32_FastCC : CallingConv<[ 953 // Handles byval parameters. Note that we can't rely on the delegation 954 // to CC_X86_32_Common for this because that happens after code that 955 // puts arguments in registers. 956 CCIfByVal<CCPassByVal<4, 4>>, 957 958 // Promote i1/i8/i16/v1i1 arguments to i32. 959 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 960 961 // The 'nest' parameter, if any, is passed in EAX. 962 CCIfNest<CCAssignToReg<[EAX]>>, 963 964 // The first 2 integer arguments are passed in ECX/EDX 965 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 966 967 // The first 3 float or double arguments, if the call is not a vararg 968 // call and if SSE2 is available, are passed in SSE registers. 969 CCIfNotVarArg<CCIfType<[f32,f64], 970 CCIfSubtarget<"hasSSE2()", 971 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 972 973 // Doubles get 8-byte slots that are 8-byte aligned. 974 CCIfType<[f64], CCAssignToStack<8, 8>>, 975 976 // Otherwise, same as everything else. 977 CCDelegateTo<CC_X86_32_Common> 978]>; 979 980def CC_X86_Win32_CFGuard_Check : CallingConv<[ 981 // The CFGuard check call takes exactly one integer argument 982 // (i.e. the target function address), which is passed in ECX. 983 CCIfType<[i32], CCAssignToReg<[ECX]>> 984]>; 985 986def CC_X86_32_GHC : CallingConv<[ 987 // Promote i8/i16 arguments to i32. 988 CCIfType<[i8, i16], CCPromoteToType<i32>>, 989 990 // Pass in STG registers: Base, Sp, Hp, R1 991 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 992]>; 993 994def CC_X86_32_HiPE : CallingConv<[ 995 // Promote i8/i16 arguments to i32. 996 CCIfType<[i8, i16], CCPromoteToType<i32>>, 997 998 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 999 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 1000 1001 // Integer/Float values get stored in stack slots that are 4 bytes in 1002 // size and 4-byte aligned. 1003 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 1004]>; 1005 1006// X86-64 Intel OpenCL built-ins calling convention. 1007def CC_Intel_OCL_BI : CallingConv<[ 1008 1009 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 1010 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 1011 1012 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 1013 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 1014 1015 CCIfType<[i32], CCAssignToStack<4, 4>>, 1016 1017 // The SSE vector arguments are passed in XMM registers. 1018 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 1019 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 1020 1021 // The 256-bit vector arguments are passed in YMM registers. 1022 CCIfType<[v8f32, v4f64, v8i32, v4i64], 1023 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 1024 1025 // The 512-bit vector arguments are passed in ZMM registers. 1026 CCIfType<[v16f32, v8f64, v16i32, v8i64], 1027 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 1028 1029 // Pass masks in mask registers 1030 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1031 1032 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1033 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1034 CCDelegateTo<CC_X86_32_C> 1035]>; 1036 1037//===----------------------------------------------------------------------===// 1038// X86 Root Argument Calling Conventions 1039//===----------------------------------------------------------------------===// 1040 1041// This is the root argument convention for the X86-32 backend. 1042def CC_X86_32 : CallingConv<[ 1043 // X86_INTR calling convention is valid in MCU target and should override the 1044 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1045 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1046 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1047 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1048 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1049 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1050 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1051 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1052 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1053 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1054 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1055 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1056 1057 // Otherwise, drop to normal X86-32 CC 1058 CCDelegateTo<CC_X86_32_C> 1059]>; 1060 1061// This is the root argument convention for the X86-64 backend. 1062def CC_X86_64 : CallingConv<[ 1063 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1064 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1065 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 1066 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1067 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1068 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1069 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1070 CCIfCC<"CallingConv::X86_RegCall", 1071 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1072 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1073 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1074 1075 // Mingw64 and native Win64 use Win64 CC 1076 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1077 1078 // Otherwise, drop to normal X86-64 CC 1079 CCDelegateTo<CC_X86_64_C> 1080]>; 1081 1082// This is the argument convention used for the entire X86 backend. 1083let Entry = 1 in 1084def CC_X86 : CallingConv<[ 1085 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1086 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1087 CCDelegateTo<CC_X86_32> 1088]>; 1089 1090//===----------------------------------------------------------------------===// 1091// Callee-saved Registers. 1092//===----------------------------------------------------------------------===// 1093 1094def CSR_NoRegs : CalleeSavedRegs<(add)>; 1095 1096def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1097def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1098 1099def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1100def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>; 1101 1102def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1103def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1104 1105def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1106 1107def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1108 (sequence "XMM%u", 6, 15))>; 1109 1110def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1111def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>; 1112 1113// The function used by Darwin to obtain the address of a thread-local variable 1114// uses rdi to pass a single parameter and rax for the return value. All other 1115// GPRs are preserved. 1116def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1117 R8, R9, R10, R11)>; 1118 1119// CSRs that are handled by prologue, epilogue. 1120def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1121 1122// CSRs that are handled explicitly via copies. 1123def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1124 1125// All GPRs - except r11 and return registers. 1126def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1127 R8, R9, R10)>; 1128 1129// All registers - except r11 and return registers. 1130def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1131 (sequence "XMM%u", 0, 15))>; 1132def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1133 (sequence "YMM%u", 0, 15))>; 1134 1135def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1136 R11, R12, R13, R14, R15, RBP, 1137 (sequence "XMM%u", 0, 15))>; 1138 1139def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1140 EDI)>; 1141def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1142 (sequence "XMM%u", 0, 7))>; 1143def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1144 (sequence "YMM%u", 0, 7))>; 1145def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1146 (sequence "ZMM%u", 0, 7), 1147 (sequence "K%u", 0, 7))>; 1148 1149def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1150def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1151 R10, R11, R12, R13, R14, R15, RBP)>; 1152def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1153 (sequence "YMM%u", 0, 15)), 1154 (sequence "XMM%u", 0, 15))>; 1155def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1156 (sequence "ZMM%u", 0, 31), 1157 (sequence "K%u", 0, 7)), 1158 (sequence "XMM%u", 0, 15))>; 1159 1160// Standard C + YMM6-15 1161def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1162 R13, R14, R15, 1163 (sequence "YMM%u", 6, 15))>; 1164 1165def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1166 R12, R13, R14, R15, 1167 (sequence "ZMM%u", 6, 21), 1168 K4, K5, K6, K7)>; 1169//Standard C + XMM 8-15 1170def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1171 (sequence "XMM%u", 8, 15))>; 1172 1173//Standard C + YMM 8-15 1174def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1175 (sequence "YMM%u", 8, 15))>; 1176 1177def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15, 1178 (sequence "ZMM%u", 16, 31), 1179 K4, K5, K6, K7)>; 1180 1181// Register calling convention preserves few GPR and XMM8-15 1182def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1183def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1184 (sequence "XMM%u", 4, 7))>; 1185def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1186def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1187def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1188 (sequence "R%u", 10, 15))>; 1189def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1190 (sequence "XMM%u", 8, 15))>; 1191def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1192 (sequence "R%u", 12, 15))>; 1193def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1194 (sequence "XMM%u", 8, 15))>; 1195