1//===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the X86-32 and X86-64 10// architectures. 11// 12//===----------------------------------------------------------------------===// 13 14/// CCIfSubtarget - Match if the current subtarget has a feature F. 15class CCIfSubtarget<string F, CCAction A> 16 : CCIf<!strconcat("static_cast<const X86Subtarget&>" 17 "(State.getMachineFunction().getSubtarget()).", F), 18 A>; 19 20/// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F. 21class CCIfNotSubtarget<string F, CCAction A> 22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>" 23 "(State.getMachineFunction().getSubtarget()).", F), 24 A>; 25 26/// CCIfIsVarArgOnWin - Match if isVarArg on Windows 32bits. 27class CCIfIsVarArgOnWin<CCAction A> 28 : CCIf<"State.isVarArg() && " 29 "State.getMachineFunction().getSubtarget().getTargetTriple()." 30 "isWindowsMSVCEnvironment()", 31 A>; 32 33// Register classes for RegCall 34class RC_X86_RegCall { 35 list<Register> GPR_8 = []; 36 list<Register> GPR_16 = []; 37 list<Register> GPR_32 = []; 38 list<Register> GPR_64 = []; 39 list<Register> FP_CALL = [FP0]; 40 list<Register> FP_RET = [FP0, FP1]; 41 list<Register> XMM = []; 42 list<Register> YMM = []; 43 list<Register> ZMM = []; 44} 45 46// RegCall register classes for 32 bits 47def RC_X86_32_RegCall : RC_X86_RegCall { 48 let GPR_8 = [AL, CL, DL, DIL, SIL]; 49 let GPR_16 = [AX, CX, DX, DI, SI]; 50 let GPR_32 = [EAX, ECX, EDX, EDI, ESI]; 51 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle [] 52 ///< \todo Fix AssignToReg to enable empty lists 53 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]; 54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7]; 55 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]; 56} 57 58class RC_X86_64_RegCall : RC_X86_RegCall { 59 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 60 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15]; 61 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, 62 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15]; 63 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, 64 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15]; 65} 66 67def RC_X86_64_RegCall_Win : RC_X86_64_RegCall { 68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B]; 69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W]; 70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D]; 71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15]; 72} 73 74def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall { 75 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B]; 76 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W]; 77 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D]; 78 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15]; 79} 80 81// X86-64 Intel regcall calling convention. 82multiclass X86_RegCall_base<RC_X86_RegCall RC> { 83def CC_#NAME : CallingConv<[ 84 // Handles byval parameters. 85 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>, 86 CCIfByVal<CCPassByVal<4, 4>>, 87 88 // Promote i1/i8/i16/v1i1 arguments to i32. 89 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 90 91 // Promote v8i1/v16i1/v32i1 arguments to i32. 92 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>, 93 94 // bool, char, int, enum, long, pointer --> GPR 95 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 96 97 // long long, __int64 --> GPR 98 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 99 100 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 101 CCIfType<[v64i1], CCPromoteToType<i64>>, 102 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 103 CCAssignToReg<RC.GPR_64>>>, 104 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 105 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 106 107 // float, double, float128 --> XMM 108 // In the case of SSE disabled --> save to stack 109 CCIfType<[f32, f64, f128], 110 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 111 112 // long double --> FP 113 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>, 114 115 // __m128, __m128i, __m128d --> XMM 116 // In the case of SSE disabled --> save to stack 117 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 118 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 119 120 // __m256, __m256i, __m256d --> YMM 121 // In the case of SSE disabled --> save to stack 122 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 123 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 124 125 // __m512, __m512i, __m512d --> ZMM 126 // In the case of SSE disabled --> save to stack 127 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 128 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>, 129 130 // If no register was found -> assign to stack 131 132 // In 64 bit, assign 64/32 bit values to 8 byte stack 133 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64], 134 CCAssignToStack<8, 8>>>, 135 136 // In 32 bit, assign 64/32 bit values to 8/4 byte stack 137 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 138 CCIfType<[i64, f64], CCAssignToStack<8, 4>>, 139 140 // MMX type gets 8 byte slot in stack , while alignment depends on target 141 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>, 142 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 143 144 // float 128 get stack slots whose size and alignment depends 145 // on the subtarget. 146 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 147 148 // Vectors get 16-byte stack slots that are 16-byte aligned. 149 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 150 CCAssignToStack<16, 16>>, 151 152 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 153 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 154 CCAssignToStack<32, 32>>, 155 156 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 157 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 158 CCAssignToStack<64, 64>> 159]>; 160 161def RetCC_#NAME : CallingConv<[ 162 // Promote i1, v1i1, v8i1 arguments to i8. 163 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>, 164 165 // Promote v16i1 arguments to i16. 166 CCIfType<[v16i1], CCPromoteToType<i16>>, 167 168 // Promote v32i1 arguments to i32. 169 CCIfType<[v32i1], CCPromoteToType<i32>>, 170 171 // bool, char, int, enum, long, pointer --> GPR 172 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>, 173 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>, 174 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>, 175 176 // long long, __int64 --> GPR 177 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>, 178 179 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32) 180 CCIfType<[v64i1], CCPromoteToType<i64>>, 181 CCIfSubtarget<"is64Bit()", CCIfType<[i64], 182 CCAssignToReg<RC.GPR_64>>>, 183 CCIfSubtarget<"is32Bit()", CCIfType<[i64], 184 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>, 185 186 // long double --> FP 187 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>, 188 189 // float, double, float128 --> XMM 190 CCIfType<[f32, f64, f128], 191 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 192 193 // __m128, __m128i, __m128d --> XMM 194 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 195 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>, 196 197 // __m256, __m256i, __m256d --> YMM 198 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 199 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>, 200 201 // __m512, __m512i, __m512d --> ZMM 202 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 203 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>> 204]>; 205} 206 207//===----------------------------------------------------------------------===// 208// Return Value Calling Conventions 209//===----------------------------------------------------------------------===// 210 211// Return-value conventions common to all X86 CC's. 212def RetCC_X86Common : CallingConv<[ 213 // Scalar values are returned in AX first, then DX. For i8, the ABI 214 // requires the values to be in AL and AH, however this code uses AL and DL 215 // instead. This is because using AH for the second register conflicts with 216 // the way LLVM does multiple return values -- a return of {i16,i8} would end 217 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI 218 // for functions that return two i8 values are currently expected to pack the 219 // values into an i16 (which uses AX, and thus AL:AH). 220 // 221 // For code that doesn't care about the ABI, we allow returning more than two 222 // integer values in registers. 223 CCIfType<[v1i1], CCPromoteToType<i8>>, 224 CCIfType<[i1], CCPromoteToType<i8>>, 225 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>, 226 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 227 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 228 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>, 229 230 // Boolean vectors of AVX-512 are returned in SIMD registers. 231 // The call from AVX to AVX-512 function should work, 232 // since the boolean types in AVX/AVX2 are promoted by default. 233 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 234 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 235 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 236 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 237 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 238 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 239 240 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3 241 // can only be used by ABI non-compliant code. If the target doesn't have XMM 242 // registers, it won't have vector types. 243 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 244 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 245 246 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3 247 // can only be used by ABI non-compliant code. This vector type is only 248 // supported while using the AVX target feature. 249 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 250 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 251 252 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3 253 // can only be used by ABI non-compliant code. This vector type is only 254 // supported while using the AVX-512 target feature. 255 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 256 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 257 258 // MMX vector types are always returned in MM0. If the target doesn't have 259 // MM0, it doesn't support these vector types. 260 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>, 261 262 // Long double types are always returned in FP0 (even with SSE), 263 // except on Win64. 264 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>> 265]>; 266 267// X86-32 C return-value convention. 268def RetCC_X86_32_C : CallingConv<[ 269 // The X86-32 calling convention returns FP values in FP0, unless marked 270 // with "inreg" (used here to distinguish one kind of reg from another, 271 // weirdly; this is really the sse-regparm calling convention) in which 272 // case they use XMM0, otherwise it is the same as the common X86 calling 273 // conv. 274 CCIfInReg<CCIfSubtarget<"hasSSE2()", 275 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 276 CCIfSubtarget<"hasX87()", 277 CCIfType<[f32, f64], CCAssignToReg<[FP0, FP1]>>>, 278 CCIfNotSubtarget<"hasX87()", 279 CCIfType<[f32], CCAssignToReg<[EAX, EDX, ECX]>>>, 280 CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>, 281 CCDelegateTo<RetCC_X86Common> 282]>; 283 284// X86-32 FastCC return-value convention. 285def RetCC_X86_32_Fast : CallingConv<[ 286 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has 287 // SSE2. 288 // This can happen when a float, 2 x float, or 3 x float vector is split by 289 // target lowering, and is returned in 1-3 sse regs. 290 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 291 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>, 292 293 // For integers, ECX can be used as an extra return register 294 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>, 295 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>, 296 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>, 297 298 // Otherwise, it is the same as the common X86 calling convention. 299 CCDelegateTo<RetCC_X86Common> 300]>; 301 302// Intel_OCL_BI return-value convention. 303def RetCC_Intel_OCL_BI : CallingConv<[ 304 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3. 305 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 306 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 307 308 // 256-bit FP vectors 309 // No more than 4 registers 310 CCIfType<[v8f32, v4f64, v8i32, v4i64], 311 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>, 312 313 // 512-bit FP vectors 314 CCIfType<[v16f32, v8f64, v16i32, v8i64], 315 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>, 316 317 // i32, i64 in the standard way 318 CCDelegateTo<RetCC_X86Common> 319]>; 320 321// X86-32 HiPE return-value convention. 322def RetCC_X86_32_HiPE : CallingConv<[ 323 // Promote all types to i32 324 CCIfType<[i8, i16], CCPromoteToType<i32>>, 325 326 // Return: HP, P, VAL1, VAL2 327 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>> 328]>; 329 330// X86-32 Vectorcall return-value convention. 331def RetCC_X86_32_VectorCall : CallingConv<[ 332 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3. 333 CCIfType<[f32, f64, f128], 334 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>, 335 336 // Return integers in the standard way. 337 CCDelegateTo<RetCC_X86Common> 338]>; 339 340// X86-64 C return-value convention. 341def RetCC_X86_64_C : CallingConv<[ 342 // The X86-64 calling convention always returns FP values in XMM0. 343 CCIfType<[f16], CCAssignToReg<[XMM0, XMM1]>>, 344 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>, 345 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>, 346 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>, 347 348 // MMX vector types are always returned in XMM0. 349 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>, 350 351 // Pointers are always returned in full 64-bit registers. 352 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 353 354 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 355 356 CCDelegateTo<RetCC_X86Common> 357]>; 358 359// X86-Win64 C return-value convention. 360def RetCC_X86_Win64_C : CallingConv<[ 361 // The X86-Win64 calling convention always returns __m64 values in RAX. 362 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 363 364 // GCC returns FP values in RAX on Win64. 365 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 366 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 367 368 // Otherwise, everything is the same as 'normal' X86-64 C CC. 369 CCDelegateTo<RetCC_X86_64_C> 370]>; 371 372// X86-64 vectorcall return-value convention. 373def RetCC_X86_64_Vectorcall : CallingConv<[ 374 // Vectorcall calling convention always returns FP values in XMMs. 375 CCIfType<[f32, f64, f128], 376 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 377 378 // Otherwise, everything is the same as Windows X86-64 C CC. 379 CCDelegateTo<RetCC_X86_Win64_C> 380]>; 381 382// X86-64 HiPE return-value convention. 383def RetCC_X86_64_HiPE : CallingConv<[ 384 // Promote all types to i64 385 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 386 387 // Return: HP, P, VAL1, VAL2 388 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>> 389]>; 390 391// X86-64 WebKit_JS return-value convention. 392def RetCC_X86_64_WebKit_JS : CallingConv<[ 393 // Promote all types to i64 394 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 395 396 // Return: RAX 397 CCIfType<[i64], CCAssignToReg<[RAX]>> 398]>; 399 400def RetCC_X86_64_Swift : CallingConv<[ 401 402 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 403 404 // For integers, ECX, R8D can be used as extra return registers. 405 CCIfType<[v1i1], CCPromoteToType<i8>>, 406 CCIfType<[i1], CCPromoteToType<i8>>, 407 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>, 408 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>, 409 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>, 410 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>, 411 412 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values. 413 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 414 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 415 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 416 417 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3. 418 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 419 CCDelegateTo<RetCC_X86Common> 420]>; 421 422// X86-64 AnyReg return-value convention. No explicit register is specified for 423// the return-value. The register allocator is allowed and expected to choose 424// any free register. 425// 426// This calling convention is currently only supported by the stackmap and 427// patchpoint intrinsics. All other uses will result in an assert on Debug 428// builds. On Release builds we fallback to the X86 C calling convention. 429def RetCC_X86_64_AnyReg : CallingConv<[ 430 CCCustom<"CC_X86_AnyReg_Error"> 431]>; 432 433// X86-64 HHVM return-value convention. 434def RetCC_X86_64_HHVM: CallingConv<[ 435 // Promote all types to i64 436 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 437 438 // Return: could return in any GP register save RSP and R12. 439 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9, 440 RAX, R10, R11, R13, R14, R15]>> 441]>; 442 443 444defm X86_32_RegCall : 445 X86_RegCall_base<RC_X86_32_RegCall>; 446defm X86_Win64_RegCall : 447 X86_RegCall_base<RC_X86_64_RegCall_Win>; 448defm X86_SysV64_RegCall : 449 X86_RegCall_base<RC_X86_64_RegCall_SysV>; 450 451// This is the root return-value convention for the X86-32 backend. 452def RetCC_X86_32 : CallingConv<[ 453 // If FastCC, use RetCC_X86_32_Fast. 454 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>, 455 CCIfCC<"CallingConv::Tail", CCDelegateTo<RetCC_X86_32_Fast>>, 456 // CFGuard_Check never returns a value so does not need a RetCC. 457 // If HiPE, use RetCC_X86_32_HiPE. 458 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>, 459 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>, 460 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>, 461 462 // Otherwise, use RetCC_X86_32_C. 463 CCDelegateTo<RetCC_X86_32_C> 464]>; 465 466// This is the root return-value convention for the X86-64 backend. 467def RetCC_X86_64 : CallingConv<[ 468 // HiPE uses RetCC_X86_64_HiPE 469 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>, 470 471 // Handle JavaScript calls. 472 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>, 473 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>, 474 475 // Handle Swift calls. 476 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>, 477 CCIfCC<"CallingConv::SwiftTail", CCDelegateTo<RetCC_X86_64_Swift>>, 478 479 // Handle explicit CC selection 480 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>, 481 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>, 482 483 // Handle Vectorcall CC 484 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>, 485 486 // Handle HHVM calls. 487 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>, 488 489 CCIfCC<"CallingConv::X86_RegCall", 490 CCIfSubtarget<"isTargetWin64()", 491 CCDelegateTo<RetCC_X86_Win64_RegCall>>>, 492 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>, 493 494 // Mingw64 and native Win64 use Win64 CC 495 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>, 496 497 // Otherwise, drop to normal X86-64 CC 498 CCDelegateTo<RetCC_X86_64_C> 499]>; 500 501// This is the return-value convention used for the entire X86 backend. 502let Entry = 1 in 503def RetCC_X86 : CallingConv<[ 504 505 // Check if this is the Intel OpenCL built-ins calling convention 506 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>, 507 508 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>, 509 CCDelegateTo<RetCC_X86_32> 510]>; 511 512//===----------------------------------------------------------------------===// 513// X86-64 Argument Calling Conventions 514//===----------------------------------------------------------------------===// 515 516def CC_X86_64_C : CallingConv<[ 517 // Handles byval parameters. 518 CCIfByVal<CCPassByVal<8, 8>>, 519 520 // Promote i1/i8/i16/v1i1 arguments to i32. 521 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 522 523 // The 'nest' parameter, if any, is passed in R10. 524 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>, 525 CCIfNest<CCAssignToReg<[R10]>>, 526 527 // Pass SwiftSelf in a callee saved register. 528 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 529 530 // A SwiftError is passed in R12. 531 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 532 533 // Pass SwiftAsync in an otherwise callee saved register so that calls to 534 // normal functions don't need to save it somewhere. 535 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 536 537 // For Swift Calling Conventions, pass sret in %rax. 538 CCIfCC<"CallingConv::Swift", 539 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 540 CCIfCC<"CallingConv::SwiftTail", 541 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>, 542 543 // Pointers are always passed in full 64-bit registers. 544 CCIfPtr<CCCustom<"CC_X86_64_Pointer">>, 545 546 // The first 6 integer arguments are passed in integer registers. 547 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>, 548 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>, 549 550 // The first 8 MMX vector arguments are passed in XMM registers on Darwin. 551 CCIfType<[x86mmx], 552 CCIfSubtarget<"isTargetDarwin()", 553 CCIfSubtarget<"hasSSE2()", 554 CCPromoteToType<v2i64>>>>, 555 556 // Boolean vectors of AVX-512 are passed in SIMD registers. 557 // The call from AVX to AVX-512 function should work, 558 // since the boolean types in AVX/AVX2 are promoted by default. 559 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 560 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 561 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 562 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 563 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 564 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 565 566 // The first 8 FP/Vector arguments are passed in XMM registers. 567 CCIfType<[f16, f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 568 CCIfSubtarget<"hasSSE1()", 569 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>, 570 571 // The first 8 256-bit vector arguments are passed in YMM registers, unless 572 // this is a vararg function. 573 // FIXME: This isn't precisely correct; the x86-64 ABI document says that 574 // fixed arguments to vararg functions are supposed to be passed in 575 // registers. Actually modeling that would be a lot of work, though. 576 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 577 CCIfSubtarget<"hasAVX()", 578 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3, 579 YMM4, YMM5, YMM6, YMM7]>>>>, 580 581 // The first 8 512-bit vector arguments are passed in ZMM registers. 582 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 583 CCIfSubtarget<"hasAVX512()", 584 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>, 585 586 // Integer/FP values get stored in stack slots that are 8 bytes in size and 587 // 8-byte aligned if there are no more registers to hold them. 588 CCIfType<[i32, i64, f16, f32, f64], CCAssignToStack<8, 8>>, 589 590 // Long doubles get stack slots whose size and alignment depends on the 591 // subtarget. 592 CCIfType<[f80, f128], CCAssignToStack<0, 0>>, 593 594 // Vectors get 16-byte stack slots that are 16-byte aligned. 595 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCAssignToStack<16, 16>>, 596 597 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned. 598 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 599 CCAssignToStack<32, 32>>, 600 601 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 602 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 603 CCAssignToStack<64, 64>> 604]>; 605 606// Calling convention for X86-64 HHVM. 607def CC_X86_64_HHVM : CallingConv<[ 608 // Use all/any GP registers for args, except RSP. 609 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15, 610 RDI, RSI, RDX, RCX, R8, R9, 611 RAX, R10, R11, R13, R14]>> 612]>; 613 614// Calling convention for helper functions in HHVM. 615def CC_X86_64_HHVM_C : CallingConv<[ 616 // Pass the first argument in RBP. 617 CCIfType<[i64], CCAssignToReg<[RBP]>>, 618 619 // Otherwise it's the same as the regular C calling convention. 620 CCDelegateTo<CC_X86_64_C> 621]>; 622 623// Calling convention used on Win64 624def CC_X86_Win64_C : CallingConv<[ 625 // FIXME: Handle varargs. 626 627 // Byval aggregates are passed by pointer 628 CCIfByVal<CCPassIndirect<i64>>, 629 630 // Promote i1/v1i1 arguments to i8. 631 CCIfType<[i1, v1i1], CCPromoteToType<i8>>, 632 633 // The 'nest' parameter, if any, is passed in R10. 634 CCIfNest<CCAssignToReg<[R10]>>, 635 636 // A SwiftError is passed in R12. 637 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>, 638 639 // Pass SwiftSelf in a callee saved register. 640 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>, 641 642 // Pass SwiftAsync in an otherwise callee saved register so that calls to 643 // normal functions don't need to save it somewhere. 644 CCIfSwiftAsync<CCIfType<[i64], CCAssignToReg<[R14]>>>, 645 646 // The 'CFGuardTarget' parameter, if any, is passed in RAX. 647 CCIfCFGuardTarget<CCAssignToReg<[RAX]>>, 648 649 // 128 bit vectors are passed by pointer 650 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], CCPassIndirect<i64>>, 651 652 // 256 bit vectors are passed by pointer 653 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], CCPassIndirect<i64>>, 654 655 // 512 bit vectors are passed by pointer 656 CCIfType<[v64i8, v32i16, v16i32, v32f16, v16f32, v8f64, v8i64], CCPassIndirect<i64>>, 657 658 // Long doubles are passed by pointer 659 CCIfType<[f80], CCPassIndirect<i64>>, 660 661 // The first 4 MMX vector arguments are passed in GPRs. 662 CCIfType<[x86mmx], CCBitConvertToType<i64>>, 663 664 // If SSE was disabled, pass FP values smaller than 64-bits as integers in 665 // GPRs or on the stack. 666 CCIfType<[f32], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i32>>>, 667 CCIfType<[f64], CCIfNotSubtarget<"hasSSE1()", CCBitConvertToType<i64>>>, 668 669 // The first 4 FP/Vector arguments are passed in XMM registers. 670 CCIfType<[f16, f32, f64], 671 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3], 672 [RCX , RDX , R8 , R9 ]>>, 673 674 // The first 4 integer arguments are passed in integer registers. 675 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ], 676 [XMM0, XMM1, XMM2, XMM3]>>, 677 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ], 678 [XMM0, XMM1, XMM2, XMM3]>>, 679 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ], 680 [XMM0, XMM1, XMM2, XMM3]>>, 681 682 // Do not pass the sret argument in RCX, the Win64 thiscall calling 683 // convention requires "this" to be passed in RCX. 684 CCIfCC<"CallingConv::X86_ThisCall", 685 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ], 686 [XMM1, XMM2, XMM3]>>>>, 687 688 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ], 689 [XMM0, XMM1, XMM2, XMM3]>>, 690 691 // Integer/FP values get stored in stack slots that are 8 bytes in size and 692 // 8-byte aligned if there are no more registers to hold them. 693 CCIfType<[i8, i16, i32, i64, f16, f32, f64], CCAssignToStack<8, 8>> 694]>; 695 696def CC_X86_Win64_VectorCall : CallingConv<[ 697 CCCustom<"CC_X86_64_VectorCall">, 698 699 // Delegate to fastcall to handle integer types. 700 CCDelegateTo<CC_X86_Win64_C> 701]>; 702 703 704def CC_X86_64_GHC : CallingConv<[ 705 // Promote i8/i16/i32 arguments to i64. 706 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 707 708 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim 709 CCIfType<[i64], 710 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>, 711 712 // Pass in STG registers: F1, F2, F3, F4, D1, D2 713 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 714 CCIfSubtarget<"hasSSE1()", 715 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>, 716 // AVX 717 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], 718 CCIfSubtarget<"hasAVX()", 719 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>, 720 // AVX-512 721 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64], 722 CCIfSubtarget<"hasAVX512()", 723 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>> 724]>; 725 726def CC_X86_64_HiPE : CallingConv<[ 727 // Promote i8/i16/i32 arguments to i64. 728 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 729 730 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3 731 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>, 732 733 // Integer/FP values get stored in stack slots that are 8 bytes in size and 734 // 8-byte aligned if there are no more registers to hold them. 735 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>> 736]>; 737 738def CC_X86_64_WebKit_JS : CallingConv<[ 739 // Promote i8/i16 arguments to i32. 740 CCIfType<[i8, i16], CCPromoteToType<i32>>, 741 742 // Only the first integer argument is passed in register. 743 CCIfType<[i32], CCAssignToReg<[EAX]>>, 744 CCIfType<[i64], CCAssignToReg<[RAX]>>, 745 746 // The remaining integer arguments are passed on the stack. 32bit integer and 747 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots. 748 // 64bit integer and floating-point arguments are aligned to 8 byte and stored 749 // in 8 byte stack slots. 750 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 751 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 752]>; 753 754// No explicit register is specified for the AnyReg calling convention. The 755// register allocator may assign the arguments to any free register. 756// 757// This calling convention is currently only supported by the stackmap and 758// patchpoint intrinsics. All other uses will result in an assert on Debug 759// builds. On Release builds we fallback to the X86 C calling convention. 760def CC_X86_64_AnyReg : CallingConv<[ 761 CCCustom<"CC_X86_AnyReg_Error"> 762]>; 763 764//===----------------------------------------------------------------------===// 765// X86 C Calling Convention 766//===----------------------------------------------------------------------===// 767 768/// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector 769/// values are spilled on the stack. 770def CC_X86_32_Vector_Common : CallingConv<[ 771 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned. 772 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 773 CCAssignToStack<16, 16>>, 774 775 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned. 776 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 777 CCAssignToStack<32, 32>>, 778 779 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned. 780 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 781 CCAssignToStack<64, 64>> 782]>; 783 784/// CC_X86_Win32_Vector - In X86 Win32 calling conventions, extra vector 785/// values are spilled on the stack. 786def CC_X86_Win32_Vector : CallingConv<[ 787 // Other SSE vectors get 16-byte stack slots that are 4-byte aligned. 788 CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 789 CCAssignToStack<16, 4>>, 790 791 // 256-bit AVX vectors get 32-byte stack slots that are 4-byte aligned. 792 CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 793 CCAssignToStack<32, 4>>, 794 795 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 4-byte aligned. 796 CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 797 CCAssignToStack<64, 4>> 798]>; 799 800// CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in 801// vector registers 802def CC_X86_32_Vector_Standard : CallingConv<[ 803 // SSE vector arguments are passed in XMM registers. 804 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 805 CCAssignToReg<[XMM0, XMM1, XMM2]>>>, 806 807 // AVX 256-bit vector arguments are passed in YMM registers. 808 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 809 CCIfSubtarget<"hasAVX()", 810 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>, 811 812 // AVX 512-bit vector arguments are passed in ZMM registers. 813 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 814 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>, 815 816 CCIfIsVarArgOnWin<CCDelegateTo<CC_X86_Win32_Vector>>, 817 CCDelegateTo<CC_X86_32_Vector_Common> 818]>; 819 820// CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in 821// vector registers. 822def CC_X86_32_Vector_Darwin : CallingConv<[ 823 // SSE vector arguments are passed in XMM registers. 824 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 825 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>, 826 827 // AVX 256-bit vector arguments are passed in YMM registers. 828 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v16f16, v8f32, v4f64], 829 CCIfSubtarget<"hasAVX()", 830 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>, 831 832 // AVX 512-bit vector arguments are passed in ZMM registers. 833 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v32f16, v16f32, v8f64], 834 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>, 835 836 CCDelegateTo<CC_X86_32_Vector_Common> 837]>; 838 839/// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP 840/// values are spilled on the stack. 841def CC_X86_32_Common : CallingConv<[ 842 // Handles byval/preallocated parameters. 843 CCIfByVal<CCPassByVal<4, 4>>, 844 CCIfPreallocated<CCPassByVal<4, 4>>, 845 846 // The first 3 float or double arguments, if marked 'inreg' and if the call 847 // is not a vararg call and if SSE2 is available, are passed in SSE registers. 848 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64], 849 CCIfSubtarget<"hasSSE2()", 850 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>, 851 852 CCIfNotVarArg<CCIfInReg<CCIfType<[f16], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 853 854 // The first 3 __m64 vector arguments are passed in mmx registers if the 855 // call is not a vararg call. 856 CCIfNotVarArg<CCIfType<[x86mmx], 857 CCAssignToReg<[MM0, MM1, MM2]>>>, 858 859 CCIfType<[f16], CCAssignToStack<4, 4>>, 860 861 // Integer/Float values get stored in stack slots that are 4 bytes in 862 // size and 4-byte aligned. 863 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 864 865 // Doubles get 8-byte slots that are 4-byte aligned. 866 CCIfType<[f64], CCAssignToStack<8, 4>>, 867 868 // Long doubles get slots whose size and alignment depends on the subtarget. 869 CCIfType<[f80], CCAssignToStack<0, 0>>, 870 871 // Boolean vectors of AVX-512 are passed in SIMD registers. 872 // The call from AVX to AVX-512 function should work, 873 // since the boolean types in AVX/AVX2 are promoted by default. 874 CCIfType<[v2i1], CCPromoteToType<v2i64>>, 875 CCIfType<[v4i1], CCPromoteToType<v4i32>>, 876 CCIfType<[v8i1], CCPromoteToType<v8i16>>, 877 CCIfType<[v16i1], CCPromoteToType<v16i8>>, 878 CCIfType<[v32i1], CCPromoteToType<v32i8>>, 879 CCIfType<[v64i1], CCPromoteToType<v64i8>>, 880 881 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are 882 // passed in the parameter area. 883 CCIfType<[x86mmx], CCAssignToStack<8, 4>>, 884 885 // Darwin passes vectors in a form that differs from the i386 psABI 886 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>, 887 888 // Otherwise, drop to 'normal' X86-32 CC 889 CCDelegateTo<CC_X86_32_Vector_Standard> 890]>; 891 892def CC_X86_32_C : CallingConv<[ 893 // Promote i1/i8/i16/v1i1 arguments to i32. 894 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 895 896 // The 'nest' parameter, if any, is passed in ECX. 897 CCIfNest<CCAssignToReg<[ECX]>>, 898 899 // On swifttailcc pass swiftself in ECX. 900 CCIfCC<"CallingConv::SwiftTail", 901 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[ECX]>>>>, 902 903 // The first 3 integer arguments, if marked 'inreg' and if the call is not 904 // a vararg call, are passed in integer registers. 905 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>, 906 907 // Otherwise, same as everything else. 908 CCDelegateTo<CC_X86_32_Common> 909]>; 910 911def CC_X86_32_MCU : CallingConv<[ 912 // Handles byval parameters. Note that, like FastCC, we can't rely on 913 // the delegation to CC_X86_32_Common because that happens after code that 914 // puts arguments in registers. 915 CCIfByVal<CCPassByVal<4, 4>>, 916 917 // Promote i1/i8/i16/v1i1 arguments to i32. 918 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 919 920 // If the call is not a vararg call, some arguments may be passed 921 // in integer registers. 922 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>, 923 924 // Otherwise, same as everything else. 925 CCDelegateTo<CC_X86_32_Common> 926]>; 927 928def CC_X86_32_FastCall : CallingConv<[ 929 // Promote i1 to i8. 930 CCIfType<[i1], CCPromoteToType<i8>>, 931 932 // The 'nest' parameter, if any, is passed in EAX. 933 CCIfNest<CCAssignToReg<[EAX]>>, 934 935 // The first 2 integer arguments are passed in ECX/EDX 936 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>, 937 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>, 938 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>, 939 940 // Otherwise, same as everything else. 941 CCDelegateTo<CC_X86_32_Common> 942]>; 943 944def CC_X86_Win32_VectorCall : CallingConv<[ 945 // Pass floating point in XMMs 946 CCCustom<"CC_X86_32_VectorCall">, 947 948 // Delegate to fastcall to handle integer types. 949 CCDelegateTo<CC_X86_32_FastCall> 950]>; 951 952def CC_X86_32_ThisCall_Common : CallingConv<[ 953 // The first integer argument is passed in ECX 954 CCIfType<[i32], CCAssignToReg<[ECX]>>, 955 956 // Otherwise, same as everything else. 957 CCDelegateTo<CC_X86_32_Common> 958]>; 959 960def CC_X86_32_ThisCall_Mingw : CallingConv<[ 961 // Promote i1/i8/i16/v1i1 arguments to i32. 962 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 963 964 CCDelegateTo<CC_X86_32_ThisCall_Common> 965]>; 966 967def CC_X86_32_ThisCall_Win : CallingConv<[ 968 // Promote i1/i8/i16/v1i1 arguments to i32. 969 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 970 971 // Pass sret arguments indirectly through stack. 972 CCIfSRet<CCAssignToStack<4, 4>>, 973 974 CCDelegateTo<CC_X86_32_ThisCall_Common> 975]>; 976 977def CC_X86_32_ThisCall : CallingConv<[ 978 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>, 979 CCDelegateTo<CC_X86_32_ThisCall_Win> 980]>; 981 982def CC_X86_32_FastCC : CallingConv<[ 983 // Handles byval parameters. Note that we can't rely on the delegation 984 // to CC_X86_32_Common for this because that happens after code that 985 // puts arguments in registers. 986 CCIfByVal<CCPassByVal<4, 4>>, 987 988 // Promote i1/i8/i16/v1i1 arguments to i32. 989 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>, 990 991 // The 'nest' parameter, if any, is passed in EAX. 992 CCIfNest<CCAssignToReg<[EAX]>>, 993 994 // The first 2 integer arguments are passed in ECX/EDX 995 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>, 996 997 // The first 3 float or double arguments, if the call is not a vararg 998 // call and if SSE2 is available, are passed in SSE registers. 999 CCIfNotVarArg<CCIfType<[f32,f64], 1000 CCIfSubtarget<"hasSSE2()", 1001 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>, 1002 1003 // Doubles get 8-byte slots that are 8-byte aligned. 1004 CCIfType<[f64], CCAssignToStack<8, 8>>, 1005 1006 // Otherwise, same as everything else. 1007 CCDelegateTo<CC_X86_32_Common> 1008]>; 1009 1010def CC_X86_Win32_CFGuard_Check : CallingConv<[ 1011 // The CFGuard check call takes exactly one integer argument 1012 // (i.e. the target function address), which is passed in ECX. 1013 CCIfType<[i32], CCAssignToReg<[ECX]>> 1014]>; 1015 1016def CC_X86_32_GHC : CallingConv<[ 1017 // Promote i8/i16 arguments to i32. 1018 CCIfType<[i8, i16], CCPromoteToType<i32>>, 1019 1020 // Pass in STG registers: Base, Sp, Hp, R1 1021 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>> 1022]>; 1023 1024def CC_X86_32_HiPE : CallingConv<[ 1025 // Promote i8/i16 arguments to i32. 1026 CCIfType<[i8, i16], CCPromoteToType<i32>>, 1027 1028 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2 1029 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>, 1030 1031 // Integer/Float values get stored in stack slots that are 4 bytes in 1032 // size and 4-byte aligned. 1033 CCIfType<[i32, f32], CCAssignToStack<4, 4>> 1034]>; 1035 1036// X86-64 Intel OpenCL built-ins calling convention. 1037def CC_Intel_OCL_BI : CallingConv<[ 1038 1039 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>, 1040 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>, 1041 1042 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>, 1043 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>, 1044 1045 CCIfType<[i32], CCAssignToStack<4, 4>>, 1046 1047 // The SSE vector arguments are passed in XMM registers. 1048 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64], 1049 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>, 1050 1051 // The 256-bit vector arguments are passed in YMM registers. 1052 CCIfType<[v8f32, v4f64, v8i32, v4i64], 1053 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>, 1054 1055 // The 512-bit vector arguments are passed in ZMM registers. 1056 CCIfType<[v16f32, v8f64, v16i32, v8i64], 1057 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>, 1058 1059 // Pass masks in mask registers 1060 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>, 1061 1062 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1063 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>, 1064 CCDelegateTo<CC_X86_32_C> 1065]>; 1066 1067//===----------------------------------------------------------------------===// 1068// X86 Root Argument Calling Conventions 1069//===----------------------------------------------------------------------===// 1070 1071// This is the root argument convention for the X86-32 backend. 1072def CC_X86_32 : CallingConv<[ 1073 // X86_INTR calling convention is valid in MCU target and should override the 1074 // MCU calling convention. Thus, this should be checked before isTargetMCU(). 1075 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1076 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>, 1077 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>, 1078 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>, 1079 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>, 1080 CCIfCC<"CallingConv::CFGuard_Check", CCDelegateTo<CC_X86_Win32_CFGuard_Check>>, 1081 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>, 1082 CCIfCC<"CallingConv::Tail", CCDelegateTo<CC_X86_32_FastCC>>, 1083 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>, 1084 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>, 1085 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>, 1086 1087 // Otherwise, drop to normal X86-32 CC 1088 CCDelegateTo<CC_X86_32_C> 1089]>; 1090 1091// This is the root argument convention for the X86-64 backend. 1092def CC_X86_64 : CallingConv<[ 1093 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>, 1094 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>, 1095 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>, 1096 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>, 1097 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>, 1098 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>, 1099 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>, 1100 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>, 1101 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>, 1102 CCIfCC<"CallingConv::X86_RegCall", 1103 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>, 1104 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>, 1105 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>, 1106 1107 // Mingw64 and native Win64 use Win64 CC 1108 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>, 1109 1110 // Otherwise, drop to normal X86-64 CC 1111 CCDelegateTo<CC_X86_64_C> 1112]>; 1113 1114// This is the argument convention used for the entire X86 backend. 1115let Entry = 1 in 1116def CC_X86 : CallingConv<[ 1117 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>, 1118 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>, 1119 CCDelegateTo<CC_X86_32> 1120]>; 1121 1122//===----------------------------------------------------------------------===// 1123// Callee-saved Registers. 1124//===----------------------------------------------------------------------===// 1125 1126def CSR_NoRegs : CalleeSavedRegs<(add)>; 1127 1128def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1129def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>; 1130 1131def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>; 1132def CSR_64_SwiftTail : CalleeSavedRegs<(sub CSR_64, R13, R14)>; 1133 1134def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>; 1135def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>; 1136 1137def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>; 1138 1139def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE, 1140 (sequence "XMM%u", 6, 15))>; 1141 1142def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>; 1143def CSR_Win64_SwiftTail : CalleeSavedRegs<(sub CSR_Win64, R13, R14)>; 1144 1145// The function used by Darwin to obtain the address of a thread-local variable 1146// uses rdi to pass a single parameter and rax for the return value. All other 1147// GPRs are preserved. 1148def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI, 1149 R8, R9, R10, R11)>; 1150 1151// CSRs that are handled by prologue, epilogue. 1152def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>; 1153 1154// CSRs that are handled explicitly via copies. 1155def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>; 1156 1157// All GPRs - except r11 1158def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI, 1159 R8, R9, R10)>; 1160 1161// All registers - except r11 1162def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1163 (sequence "XMM%u", 0, 15))>; 1164def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs, 1165 (sequence "YMM%u", 0, 15))>; 1166 1167def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10, 1168 R11, R12, R13, R14, R15, RBP, 1169 (sequence "XMM%u", 0, 15))>; 1170 1171def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI, 1172 EDI)>; 1173def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs, 1174 (sequence "XMM%u", 0, 7))>; 1175def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs, 1176 (sequence "YMM%u", 0, 7))>; 1177def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs, 1178 (sequence "ZMM%u", 0, 7), 1179 (sequence "K%u", 0, 7))>; 1180 1181def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>; 1182def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9, 1183 R10, R11, R12, R13, R14, R15, RBP)>; 1184def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1185 (sequence "YMM%u", 0, 15)), 1186 (sequence "XMM%u", 0, 15))>; 1187def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX, 1188 (sequence "ZMM%u", 0, 31), 1189 (sequence "K%u", 0, 7)), 1190 (sequence "XMM%u", 0, 15))>; 1191 1192// Standard C + YMM6-15 1193def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, 1194 R13, R14, R15, 1195 (sequence "YMM%u", 6, 15))>; 1196 1197def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, 1198 R12, R13, R14, R15, 1199 (sequence "ZMM%u", 6, 21), 1200 K4, K5, K6, K7)>; 1201//Standard C + XMM 8-15 1202def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64, 1203 (sequence "XMM%u", 8, 15))>; 1204 1205//Standard C + YMM 8-15 1206def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64, 1207 (sequence "YMM%u", 8, 15))>; 1208 1209def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RSI, R14, R15, 1210 (sequence "ZMM%u", 16, 31), 1211 K4, K5, K6, K7)>; 1212 1213// Only R12 is preserved for PHP calls in HHVM. 1214def CSR_64_HHVM : CalleeSavedRegs<(add R12)>; 1215 1216// Register calling convention preserves few GPR and XMM8-15 1217def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>; 1218def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, 1219 (sequence "XMM%u", 4, 7))>; 1220def CSR_Win32_CFGuard_Check_NoSSE : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE, ECX)>; 1221def CSR_Win32_CFGuard_Check : CalleeSavedRegs<(add CSR_32_RegCall, ECX)>; 1222def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1223 (sequence "R%u", 10, 15))>; 1224def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE, 1225 (sequence "XMM%u", 8, 15))>; 1226def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, 1227 (sequence "R%u", 12, 15))>; 1228def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE, 1229 (sequence "XMM%u", 8, 15))>; 1230