1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This is a target description file for the Intel i386 architecture, referred 10// to here as the "X86" architecture. 11// 12//===----------------------------------------------------------------------===// 13 14// Get the target-independent interfaces which we are implementing... 15// 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// X86 Subtarget state 20// 21 22def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", 23 "64-bit mode (x86_64)">; 24def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", 25 "32-bit mode (80386)">; 26def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", 27 "16-bit mode (i8086)">; 28 29//===----------------------------------------------------------------------===// 30// X86 Subtarget features 31//===----------------------------------------------------------------------===// 32 33def FeatureX87 : SubtargetFeature<"x87","HasX87", "true", 34 "Enable X87 float instructions">; 35 36def FeatureNOPL : SubtargetFeature<"nopl", "HasNOPL", "true", 37 "Enable NOPL instruction">; 38 39def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", 40 "Enable conditional move instructions">; 41 42def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true", 43 "Support CMPXCHG8B instructions">; 44 45def FeaturePOPCNT : SubtargetFeature<"popcnt", "HasPOPCNT", "true", 46 "Support POPCNT instruction">; 47 48def FeatureFXSR : SubtargetFeature<"fxsr", "HasFXSR", "true", 49 "Support fxsave/fxrestore instructions">; 50 51def FeatureXSAVE : SubtargetFeature<"xsave", "HasXSAVE", "true", 52 "Support xsave instructions">; 53 54def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true", 55 "Support xsaveopt instructions">; 56 57def FeatureXSAVEC : SubtargetFeature<"xsavec", "HasXSAVEC", "true", 58 "Support xsavec instructions">; 59 60def FeatureXSAVES : SubtargetFeature<"xsaves", "HasXSAVES", "true", 61 "Support xsaves instructions">; 62 63def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", 64 "Enable SSE instructions">; 65def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2", 66 "Enable SSE2 instructions", 67 [FeatureSSE1]>; 68def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3", 69 "Enable SSE3 instructions", 70 [FeatureSSE2]>; 71def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3", 72 "Enable SSSE3 instructions", 73 [FeatureSSE3]>; 74def FeatureSSE41 : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41", 75 "Enable SSE 4.1 instructions", 76 [FeatureSSSE3]>; 77def FeatureSSE42 : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42", 78 "Enable SSE 4.2 instructions", 79 [FeatureSSE41]>; 80// The MMX subtarget feature is separate from the rest of the SSE features 81// because it's important (for odd compatibility reasons) to be able to 82// turn it off explicitly while allowing SSE+ to be on. 83def FeatureMMX : SubtargetFeature<"mmx","X863DNowLevel", "MMX", 84 "Enable MMX instructions">; 85def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow", 86 "Enable 3DNow! instructions", 87 [FeatureMMX]>; 88def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA", 89 "Enable 3DNow! Athlon instructions", 90 [Feature3DNow]>; 91// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied 92// feature, because SSE2 can be disabled (e.g. for compiling OS kernels) 93// without disabling 64-bit mode. Nothing should imply this feature bit. It 94// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode. 95def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", 96 "Support 64-bit instructions">; 97def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", 98 "64-bit with cmpxchg16b", 99 [FeatureCMPXCHG8B]>; 100def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true", 101 "SHLD instruction is slow">; 102def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true", 103 "PMULLD instruction is slow">; 104def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow", 105 "true", 106 "PMADDWD is slower than PMULLD">; 107// FIXME: This should not apply to CPUs that do not have SSE. 108def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", 109 "IsUAMem16Slow", "true", 110 "Slow unaligned 16-byte memory access">; 111def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", 112 "IsUAMem32Slow", "true", 113 "Slow unaligned 32-byte memory access">; 114def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", 115 "Support SSE 4a instructions", 116 [FeatureSSE3]>; 117 118def FeatureAVX : SubtargetFeature<"avx", "X86SSELevel", "AVX", 119 "Enable AVX instructions", 120 [FeatureSSE42]>; 121def FeatureAVX2 : SubtargetFeature<"avx2", "X86SSELevel", "AVX2", 122 "Enable AVX2 instructions", 123 [FeatureAVX]>; 124def FeatureFMA : SubtargetFeature<"fma", "HasFMA", "true", 125 "Enable three-operand fused multiple-add", 126 [FeatureAVX]>; 127def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", 128 "Support 16-bit floating point conversion instructions", 129 [FeatureAVX]>; 130def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", 131 "Enable AVX-512 instructions", 132 [FeatureAVX2, FeatureFMA, FeatureF16C]>; 133def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", 134 "Enable AVX-512 Exponential and Reciprocal Instructions", 135 [FeatureAVX512]>; 136def FeatureCDI : SubtargetFeature<"avx512cd", "HasCDI", "true", 137 "Enable AVX-512 Conflict Detection Instructions", 138 [FeatureAVX512]>; 139def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ", 140 "true", "Enable AVX-512 Population Count Instructions", 141 [FeatureAVX512]>; 142def FeaturePFI : SubtargetFeature<"avx512pf", "HasPFI", "true", 143 "Enable AVX-512 PreFetch Instructions", 144 [FeatureAVX512]>; 145def FeaturePREFETCHWT1 : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1", 146 "true", 147 "Prefetch with Intent to Write and T1 Hint">; 148def FeatureDQI : SubtargetFeature<"avx512dq", "HasDQI", "true", 149 "Enable AVX-512 Doubleword and Quadword Instructions", 150 [FeatureAVX512]>; 151def FeatureBWI : SubtargetFeature<"avx512bw", "HasBWI", "true", 152 "Enable AVX-512 Byte and Word Instructions", 153 [FeatureAVX512]>; 154def FeatureVLX : SubtargetFeature<"avx512vl", "HasVLX", "true", 155 "Enable AVX-512 Vector Length eXtensions", 156 [FeatureAVX512]>; 157def FeatureVBMI : SubtargetFeature<"avx512vbmi", "HasVBMI", "true", 158 "Enable AVX-512 Vector Byte Manipulation Instructions", 159 [FeatureBWI]>; 160def FeatureVBMI2 : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true", 161 "Enable AVX-512 further Vector Byte Manipulation Instructions", 162 [FeatureBWI]>; 163def FeatureIFMA : SubtargetFeature<"avx512ifma", "HasIFMA", "true", 164 "Enable AVX-512 Integer Fused Multiple-Add", 165 [FeatureAVX512]>; 166def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true", 167 "Enable protection keys">; 168def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true", 169 "Enable AVX-512 Vector Neural Network Instructions", 170 [FeatureAVX512]>; 171def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true", 172 "Support bfloat16 floating point", 173 [FeatureBWI]>; 174def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true", 175 "Enable AVX-512 Bit Algorithms", 176 [FeatureBWI]>; 177def FeatureVP2INTERSECT : SubtargetFeature<"avx512vp2intersect", 178 "HasVP2INTERSECT", "true", 179 "Enable AVX-512 vp2intersect", 180 [FeatureAVX512]>; 181def FeaturePCLMUL : SubtargetFeature<"pclmul", "HasPCLMUL", "true", 182 "Enable packed carry-less multiplication instructions", 183 [FeatureSSE2]>; 184def FeatureGFNI : SubtargetFeature<"gfni", "HasGFNI", "true", 185 "Enable Galois Field Arithmetic Instructions", 186 [FeatureSSE2]>; 187def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true", 188 "Enable vpclmulqdq instructions", 189 [FeatureAVX, FeaturePCLMUL]>; 190def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true", 191 "Enable four-operand fused multiple-add", 192 [FeatureAVX, FeatureSSE4A]>; 193def FeatureXOP : SubtargetFeature<"xop", "HasXOP", "true", 194 "Enable XOP instructions", 195 [FeatureFMA4]>; 196def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem", 197 "HasSSEUnalignedMem", "true", 198 "Allow unaligned memory operands with SSE instructions">; 199def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", 200 "Enable AES instructions", 201 [FeatureSSE2]>; 202def FeatureVAES : SubtargetFeature<"vaes", "HasVAES", "true", 203 "Promote selected AES instructions to AVX512/AVX registers", 204 [FeatureAVX, FeatureAES]>; 205def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true", 206 "Enable TBM instructions">; 207def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true", 208 "Enable LWP instructions">; 209def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true", 210 "Support MOVBE instruction">; 211def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true", 212 "Support RDRAND instruction">; 213def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true", 214 "Support FS/GS Base instructions">; 215def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true", 216 "Support LZCNT instruction">; 217def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true", 218 "Support BMI instructions">; 219def FeatureBMI2 : SubtargetFeature<"bmi2", "HasBMI2", "true", 220 "Support BMI2 instructions">; 221def FeatureRTM : SubtargetFeature<"rtm", "HasRTM", "true", 222 "Support RTM instructions">; 223def FeatureADX : SubtargetFeature<"adx", "HasADX", "true", 224 "Support ADX instructions">; 225def FeatureSHA : SubtargetFeature<"sha", "HasSHA", "true", 226 "Enable SHA instructions", 227 [FeatureSSE2]>; 228def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true", 229 "Support CET Shadow-Stack instructions">; 230def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true", 231 "Support PRFCHW instructions">; 232def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true", 233 "Support RDSEED instruction">; 234def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true", 235 "Support LAHF and SAHF instructions">; 236def FeatureMWAITX : SubtargetFeature<"mwaitx", "HasMWAITX", "true", 237 "Enable MONITORX/MWAITX timer functionality">; 238def FeatureCLZERO : SubtargetFeature<"clzero", "HasCLZERO", "true", 239 "Enable Cache Line Zero">; 240def FeatureCLDEMOTE : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true", 241 "Enable Cache Demote">; 242def FeaturePTWRITE : SubtargetFeature<"ptwrite", "HasPTWRITE", "true", 243 "Support ptwrite instruction">; 244def FeatureMPX : SubtargetFeature<"mpx", "HasMPX", "true", 245 "Support MPX instructions">; 246def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", 247 "Use LEA for adjusting the stack pointer">; 248def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb", 249 "HasSlowDivide32", "true", 250 "Use 8-bit divide for positive values less than 256">; 251def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl", 252 "HasSlowDivide64", "true", 253 "Use 32-bit divide for positive values less than 2^32">; 254def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions", 255 "PadShortFunctions", "true", 256 "Pad short functions">; 257def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true", 258 "Invalidate Process-Context Identifier">; 259def FeatureSGX : SubtargetFeature<"sgx", "HasSGX", "true", 260 "Enable Software Guard Extensions">; 261def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true", 262 "Flush A Cache Line Optimized">; 263def FeatureCLWB : SubtargetFeature<"clwb", "HasCLWB", "true", 264 "Cache Line Write Back">; 265def FeatureWBNOINVD : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true", 266 "Write Back No Invalidate">; 267def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true", 268 "Support RDPID instructions">; 269def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true", 270 "Wait and pause enhancements">; 271def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true", 272 "Has ENQCMD instructions">; 273// On some processors, instructions that implicitly take two memory operands are 274// slow. In practice, this means that CALL, PUSH, and POP with memory operands 275// should be avoided in favor of a MOV + register CALL/PUSH/POP. 276def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops", 277 "SlowTwoMemOps", "true", 278 "Two memory operand instructions are slow">; 279def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", 280 "LEA instruction needs inputs at AG stage">; 281def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", 282 "LEA instruction with certain arguments is slow">; 283def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true", 284 "LEA instruction with 3 ops or certain registers is slow">; 285def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true", 286 "INC and DEC instructions are slower than ADD and SUB">; 287def FeatureSoftFloat 288 : SubtargetFeature<"soft-float", "UseSoftFloat", "true", 289 "Use software floating point features">; 290def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt", 291 "HasPOPCNTFalseDeps", "true", 292 "POPCNT has a false dependency on dest register">; 293def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt", 294 "HasLZCNTFalseDeps", "true", 295 "LZCNT/TZCNT have a false dependency on dest register">; 296def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true", 297 "platform configuration instruction">; 298// On recent X86 (port bound) processors, its preferable to combine to a single shuffle 299// using a variable mask over multiple fixed shuffles. 300def FeatureFastVariableShuffle 301 : SubtargetFeature<"fast-variable-shuffle", 302 "HasFastVariableShuffle", 303 "true", "Shuffles with variable masks are fast">; 304// On some X86 processors, there is no performance hazard to writing only the 305// lower parts of a YMM or ZMM register without clearing the upper part. 306def FeatureFastPartialYMMorZMMWrite 307 : SubtargetFeature<"fast-partial-ymm-or-zmm-write", 308 "HasFastPartialYMMorZMMWrite", 309 "true", "Partial writes to YMM/ZMM registers are fast">; 310// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency 311// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if 312// vector FSQRT has higher throughput than the corresponding NR code. 313// The idea is that throughput bound code is likely to be vectorized, so for 314// vectorized code we should care about the throughput of SQRT operations. 315// But if the code is scalar that probably means that the code has some kind of 316// dependency and we should care more about reducing the latency. 317def FeatureFastScalarFSQRT 318 : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT", 319 "true", "Scalar SQRT is fast (disable Newton-Raphson)">; 320def FeatureFastVectorFSQRT 321 : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT", 322 "true", "Vector SQRT is fast (disable Newton-Raphson)">; 323// If lzcnt has equivalent latency/throughput to most simple integer ops, it can 324// be used to replace test/set sequences. 325def FeatureFastLZCNT 326 : SubtargetFeature< 327 "fast-lzcnt", "HasFastLZCNT", "true", 328 "LZCNT instructions are as fast as most simple integer ops">; 329// If the target can efficiently decode NOPs upto 11-bytes in length. 330def FeatureFast11ByteNOP 331 : SubtargetFeature< 332 "fast-11bytenop", "HasFast11ByteNOP", "true", 333 "Target can quickly decode up to 11 byte NOPs">; 334// If the target can efficiently decode NOPs upto 15-bytes in length. 335def FeatureFast15ByteNOP 336 : SubtargetFeature< 337 "fast-15bytenop", "HasFast15ByteNOP", "true", 338 "Target can quickly decode up to 15 byte NOPs">; 339// Sandy Bridge and newer processors can use SHLD with the same source on both 340// inputs to implement rotate to avoid the partial flag update of the normal 341// rotate instructions. 342def FeatureFastSHLDRotate 343 : SubtargetFeature< 344 "fast-shld-rotate", "HasFastSHLDRotate", "true", 345 "SHLD can be used as a faster rotate">; 346 347// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka 348// "string operations"). See "REP String Enhancement" in the Intel Software 349// Development Manual. This feature essentially means that REP MOVSB will copy 350// using the largest available size instead of copying bytes one by one, making 351// it at least as fast as REPMOVS{W,D,Q}. 352def FeatureERMSB 353 : SubtargetFeature< 354 "ermsb", "HasERMSB", "true", 355 "REP MOVS/STOS are fast">; 356 357// Bulldozer and newer processors can merge CMP/TEST (but not other 358// instructions) with conditional branches. 359def FeatureBranchFusion 360 : SubtargetFeature<"branchfusion", "HasBranchFusion", "true", 361 "CMP/TEST can be fused with conditional branches">; 362 363// Sandy Bridge and newer processors have many instructions that can be 364// fused with conditional branches and pass through the CPU as a single 365// operation. 366def FeatureMacroFusion 367 : SubtargetFeature<"macrofusion", "HasMacroFusion", "true", 368 "Various instructions can be fused with conditional branches">; 369 370// Gather is available since Haswell (AVX2 set). So technically, we can 371// generate Gathers on all AVX2 processors. But the overhead on HSW is high. 372// Skylake Client processor has faster Gathers than HSW and performance is 373// similar to Skylake Server (AVX-512). 374def FeatureHasFastGather 375 : SubtargetFeature<"fast-gather", "HasFastGather", "true", 376 "Indicates if gather is reasonably fast">; 377 378def FeaturePrefer256Bit 379 : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true", 380 "Prefer 256-bit AVX instructions">; 381 382// Lower indirect calls using a special construct called a `retpoline` to 383// mitigate potential Spectre v2 attacks against them. 384def FeatureRetpolineIndirectCalls 385 : SubtargetFeature< 386 "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true", 387 "Remove speculation of indirect calls from the generated code">; 388 389// Lower indirect branches and switches either using conditional branch trees 390// or using a special construct called a `retpoline` to mitigate potential 391// Spectre v2 attacks against them. 392def FeatureRetpolineIndirectBranches 393 : SubtargetFeature< 394 "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true", 395 "Remove speculation of indirect branches from the generated code">; 396 397// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and 398// `retpoline-indirect-branches` above. 399def FeatureRetpoline 400 : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true", 401 "Remove speculation of indirect branches from the " 402 "generated code, either by avoiding them entirely or " 403 "lowering them with a speculation blocking construct", 404 [FeatureRetpolineIndirectCalls, 405 FeatureRetpolineIndirectBranches]>; 406 407// Rely on external thunks for the emitted retpoline calls. This allows users 408// to provide their own custom thunk definitions in highly specialized 409// environments such as a kernel that does boot-time hot patching. 410def FeatureRetpolineExternalThunk 411 : SubtargetFeature< 412 "retpoline-external-thunk", "UseRetpolineExternalThunk", "true", 413 "When lowering an indirect call or branch using a `retpoline`, rely " 414 "on the specified user provided thunk rather than emitting one " 415 "ourselves. Only has effect when combined with some other retpoline " 416 "feature", [FeatureRetpolineIndirectCalls]>; 417 418// Direct Move instructions. 419def FeatureMOVDIRI : SubtargetFeature<"movdiri", "HasMOVDIRI", "true", 420 "Support movdiri instruction">; 421def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true", 422 "Support movdir64b instruction">; 423 424def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true", 425 "Indicates that the BEXTR instruction is implemented as a single uop " 426 "with good throughput">; 427 428// Combine vector math operations with shuffles into horizontal math 429// instructions if a CPU implements horizontal operations (introduced with 430// SSE3) with better latency/throughput than the alternative sequence. 431def FeatureFastHorizontalOps 432 : SubtargetFeature< 433 "fast-hops", "HasFastHorizontalOps", "true", 434 "Prefer horizontal vector math instructions (haddp, phsub, etc.) over " 435 "normal vector instructions with shuffles", [FeatureSSE3]>; 436 437def FeatureFastScalarShiftMasks 438 : SubtargetFeature< 439 "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true", 440 "Prefer a left/right scalar logical shift pair over a shift+and pair">; 441 442def FeatureFastVectorShiftMasks 443 : SubtargetFeature< 444 "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true", 445 "Prefer a left/right vector logical shift pair over a shift+and pair">; 446 447// Merge branches using three-way conditional code. 448def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch", 449 "ThreewayBranchProfitable", "true", 450 "Merge branches to a three-way " 451 "conditional branch">; 452 453// Bonnell 454def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; 455// Silvermont 456def ProcIntelSLM : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">; 457// Goldmont 458def ProcIntelGLM : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">; 459// Goldmont Plus 460def ProcIntelGLP : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">; 461// Tremont 462def ProcIntelTRM : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">; 463 464//===----------------------------------------------------------------------===// 465// Register File Description 466//===----------------------------------------------------------------------===// 467 468include "X86RegisterInfo.td" 469include "X86RegisterBanks.td" 470 471//===----------------------------------------------------------------------===// 472// Instruction Descriptions 473//===----------------------------------------------------------------------===// 474 475include "X86Schedule.td" 476include "X86InstrInfo.td" 477include "X86SchedPredicates.td" 478 479def X86InstrInfo : InstrInfo; 480 481//===----------------------------------------------------------------------===// 482// X86 Scheduler Models 483//===----------------------------------------------------------------------===// 484 485include "X86ScheduleAtom.td" 486include "X86SchedSandyBridge.td" 487include "X86SchedHaswell.td" 488include "X86SchedBroadwell.td" 489include "X86ScheduleSLM.td" 490include "X86ScheduleZnver1.td" 491include "X86ScheduleBdVer2.td" 492include "X86ScheduleBtVer2.td" 493include "X86SchedSkylakeClient.td" 494include "X86SchedSkylakeServer.td" 495 496//===----------------------------------------------------------------------===// 497// X86 Processor Feature Lists 498//===----------------------------------------------------------------------===// 499 500def ProcessorFeatures { 501 // Nehalem 502 list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87, 503 FeatureCMPXCHG8B, 504 FeatureCMOV, 505 FeatureMMX, 506 FeatureSSE42, 507 FeatureFXSR, 508 FeatureNOPL, 509 Feature64Bit, 510 FeatureCMPXCHG16B, 511 FeaturePOPCNT, 512 FeatureLAHFSAHF, 513 FeatureMacroFusion]; 514 list<SubtargetFeature> NHMSpecificFeatures = []; 515 list<SubtargetFeature> NHMFeatures = 516 !listconcat(NHMInheritableFeatures, NHMSpecificFeatures); 517 518 // Westmere 519 list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL]; 520 list<SubtargetFeature> WSMSpecificFeatures = []; 521 list<SubtargetFeature> WSMInheritableFeatures = 522 !listconcat(NHMInheritableFeatures, WSMAdditionalFeatures); 523 list<SubtargetFeature> WSMFeatures = 524 !listconcat(WSMInheritableFeatures, WSMSpecificFeatures); 525 526 // Sandybridge 527 list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX, 528 FeatureSlowDivide64, 529 FeatureXSAVE, 530 FeatureXSAVEOPT, 531 FeatureSlow3OpsLEA, 532 FeatureFastScalarFSQRT, 533 FeatureFastSHLDRotate, 534 FeatureMergeToThreeWayBranch]; 535 list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32, 536 FeaturePOPCNTFalseDeps]; 537 list<SubtargetFeature> SNBInheritableFeatures = 538 !listconcat(WSMInheritableFeatures, SNBAdditionalFeatures); 539 list<SubtargetFeature> SNBFeatures = 540 !listconcat(SNBInheritableFeatures, SNBSpecificFeatures); 541 542 // Ivybridge 543 list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND, 544 FeatureF16C, 545 FeatureFSGSBase]; 546 list<SubtargetFeature> IVBSpecificFeatures = [FeatureSlowUAMem32, 547 FeaturePOPCNTFalseDeps]; 548 list<SubtargetFeature> IVBInheritableFeatures = 549 !listconcat(SNBInheritableFeatures, IVBAdditionalFeatures); 550 list<SubtargetFeature> IVBFeatures = 551 !listconcat(IVBInheritableFeatures, IVBSpecificFeatures); 552 553 // Haswell 554 list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2, 555 FeatureBMI, 556 FeatureBMI2, 557 FeatureERMSB, 558 FeatureFMA, 559 FeatureINVPCID, 560 FeatureLZCNT, 561 FeatureMOVBE, 562 FeatureFastVariableShuffle]; 563 list<SubtargetFeature> HSWSpecificFeatures = [FeaturePOPCNTFalseDeps, 564 FeatureLZCNTFalseDeps]; 565 list<SubtargetFeature> HSWInheritableFeatures = 566 !listconcat(IVBInheritableFeatures, HSWAdditionalFeatures); 567 list<SubtargetFeature> HSWFeatures = 568 !listconcat(HSWInheritableFeatures, HSWSpecificFeatures); 569 570 // Broadwell 571 list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX, 572 FeatureRDSEED, 573 FeaturePRFCHW]; 574 list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps, 575 FeatureLZCNTFalseDeps]; 576 list<SubtargetFeature> BDWInheritableFeatures = 577 !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures); 578 list<SubtargetFeature> BDWFeatures = 579 !listconcat(BDWInheritableFeatures, BDWSpecificFeatures); 580 581 // Skylake 582 list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES, 583 FeatureMPX, 584 FeatureXSAVEC, 585 FeatureXSAVES, 586 FeatureCLFLUSHOPT, 587 FeatureFastVectorFSQRT]; 588 list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather, 589 FeaturePOPCNTFalseDeps, 590 FeatureSGX]; 591 list<SubtargetFeature> SKLInheritableFeatures = 592 !listconcat(BDWInheritableFeatures, SKLAdditionalFeatures); 593 list<SubtargetFeature> SKLFeatures = 594 !listconcat(SKLInheritableFeatures, SKLSpecificFeatures); 595 596 // Skylake-AVX512 597 list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512, 598 FeatureCDI, 599 FeatureDQI, 600 FeatureBWI, 601 FeatureVLX, 602 FeaturePKU, 603 FeatureCLWB]; 604 list<SubtargetFeature> SKXSpecificFeatures = [FeatureHasFastGather, 605 FeaturePOPCNTFalseDeps]; 606 list<SubtargetFeature> SKXInheritableFeatures = 607 !listconcat(SKLInheritableFeatures, SKXAdditionalFeatures); 608 list<SubtargetFeature> SKXFeatures = 609 !listconcat(SKXInheritableFeatures, SKXSpecificFeatures); 610 611 // Cascadelake 612 list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI]; 613 list<SubtargetFeature> CLXSpecificFeatures = [FeatureHasFastGather, 614 FeaturePOPCNTFalseDeps]; 615 list<SubtargetFeature> CLXInheritableFeatures = 616 !listconcat(SKXInheritableFeatures, CLXAdditionalFeatures); 617 list<SubtargetFeature> CLXFeatures = 618 !listconcat(CLXInheritableFeatures, CLXSpecificFeatures); 619 620 // Cooperlake 621 list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16]; 622 list<SubtargetFeature> CPXSpecificFeatures = [FeatureHasFastGather, 623 FeaturePOPCNTFalseDeps]; 624 list<SubtargetFeature> CPXInheritableFeatures = 625 !listconcat(CLXInheritableFeatures, CPXAdditionalFeatures); 626 list<SubtargetFeature> CPXFeatures = 627 !listconcat(CPXInheritableFeatures, CPXSpecificFeatures); 628 629 // Cannonlake 630 list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512, 631 FeatureCDI, 632 FeatureDQI, 633 FeatureBWI, 634 FeatureVLX, 635 FeaturePKU, 636 FeatureVBMI, 637 FeatureIFMA, 638 FeatureSHA, 639 FeatureSGX]; 640 list<SubtargetFeature> CNLSpecificFeatures = [FeatureHasFastGather]; 641 list<SubtargetFeature> CNLInheritableFeatures = 642 !listconcat(SKLInheritableFeatures, CNLAdditionalFeatures); 643 list<SubtargetFeature> CNLFeatures = 644 !listconcat(CNLInheritableFeatures, CNLSpecificFeatures); 645 646 // Icelake 647 list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG, 648 FeatureVAES, 649 FeatureVBMI2, 650 FeatureVNNI, 651 FeatureVPCLMULQDQ, 652 FeatureVPOPCNTDQ, 653 FeatureGFNI, 654 FeatureCLWB, 655 FeatureRDPID]; 656 list<SubtargetFeature> ICLSpecificFeatures = [FeatureHasFastGather]; 657 list<SubtargetFeature> ICLInheritableFeatures = 658 !listconcat(CNLInheritableFeatures, ICLAdditionalFeatures); 659 list<SubtargetFeature> ICLFeatures = 660 !listconcat(ICLInheritableFeatures, ICLSpecificFeatures); 661 662 // Icelake Server 663 list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG, 664 FeatureWBNOINVD, 665 FeatureHasFastGather]; 666 list<SubtargetFeature> ICXFeatures = 667 !listconcat(ICLInheritableFeatures, ICXSpecificFeatures); 668 669 // Atom 670 list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87, 671 FeatureCMPXCHG8B, 672 FeatureCMOV, 673 FeatureMMX, 674 FeatureSSSE3, 675 FeatureFXSR, 676 FeatureNOPL, 677 Feature64Bit, 678 FeatureCMPXCHG16B, 679 FeatureMOVBE, 680 FeatureSlowTwoMemOps, 681 FeatureLAHFSAHF]; 682 list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom, 683 FeatureSlowUAMem16, 684 FeatureLEAForSP, 685 FeatureSlowDivide32, 686 FeatureSlowDivide64, 687 FeatureLEAUsesAG, 688 FeaturePadShortFunctions]; 689 list<SubtargetFeature> AtomFeatures = 690 !listconcat(AtomInheritableFeatures, AtomSpecificFeatures); 691 692 // Silvermont 693 list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42, 694 FeaturePOPCNT, 695 FeaturePCLMUL, 696 FeaturePRFCHW, 697 FeatureSlowLEA, 698 FeatureSlowIncDec, 699 FeatureRDRAND]; 700 list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM, 701 FeatureSlowDivide64, 702 FeatureSlowPMULLD, 703 FeaturePOPCNTFalseDeps]; 704 list<SubtargetFeature> SLMInheritableFeatures = 705 !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures); 706 list<SubtargetFeature> SLMFeatures = 707 !listconcat(SLMInheritableFeatures, SLMSpecificFeatures); 708 709 // Goldmont 710 list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES, 711 FeatureMPX, 712 FeatureSHA, 713 FeatureRDSEED, 714 FeatureXSAVE, 715 FeatureXSAVEOPT, 716 FeatureXSAVEC, 717 FeatureXSAVES, 718 FeatureCLFLUSHOPT, 719 FeatureFSGSBase]; 720 list<SubtargetFeature> GLMSpecificFeatures = [ProcIntelGLM, 721 FeaturePOPCNTFalseDeps]; 722 list<SubtargetFeature> GLMInheritableFeatures = 723 !listconcat(SLMInheritableFeatures, GLMAdditionalFeatures); 724 list<SubtargetFeature> GLMFeatures = 725 !listconcat(GLMInheritableFeatures, GLMSpecificFeatures); 726 727 // Goldmont Plus 728 list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE, 729 FeatureRDPID, 730 FeatureSGX]; 731 list<SubtargetFeature> GLPSpecificFeatures = [ProcIntelGLP]; 732 list<SubtargetFeature> GLPInheritableFeatures = 733 !listconcat(GLMInheritableFeatures, GLPAdditionalFeatures); 734 list<SubtargetFeature> GLPFeatures = 735 !listconcat(GLPInheritableFeatures, GLPSpecificFeatures); 736 737 // Tremont 738 list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE, 739 FeatureGFNI, 740 FeatureMOVDIRI, 741 FeatureMOVDIR64B, 742 FeatureWAITPKG]; 743 list<SubtargetFeature> TRMSpecificFeatures = [ProcIntelTRM]; 744 list<SubtargetFeature> TRMFeatures = 745 !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures, 746 TRMSpecificFeatures); 747 748 // Knights Landing 749 list<SubtargetFeature> KNLFeatures = [FeatureX87, 750 FeatureCMPXCHG8B, 751 FeatureCMOV, 752 FeatureMMX, 753 FeatureFXSR, 754 FeatureNOPL, 755 Feature64Bit, 756 FeatureCMPXCHG16B, 757 FeaturePOPCNT, 758 FeatureSlowDivide64, 759 FeaturePCLMUL, 760 FeatureXSAVE, 761 FeatureXSAVEOPT, 762 FeatureLAHFSAHF, 763 FeatureSlow3OpsLEA, 764 FeatureSlowIncDec, 765 FeatureAES, 766 FeatureRDRAND, 767 FeatureF16C, 768 FeatureFSGSBase, 769 FeatureAVX512, 770 FeatureERI, 771 FeatureCDI, 772 FeaturePFI, 773 FeaturePREFETCHWT1, 774 FeatureADX, 775 FeatureRDSEED, 776 FeatureMOVBE, 777 FeatureLZCNT, 778 FeatureBMI, 779 FeatureBMI2, 780 FeatureFMA, 781 FeaturePRFCHW, 782 FeatureSlowTwoMemOps, 783 FeatureFastPartialYMMorZMMWrite, 784 FeatureHasFastGather, 785 FeatureSlowPMADDWD]; 786 // TODO Add AVX5124FMAPS/AVX5124VNNIW features 787 list<SubtargetFeature> KNMFeatures = 788 !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]); 789 790 791 // Bobcat 792 list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87, 793 FeatureCMPXCHG8B, 794 FeatureCMOV, 795 FeatureMMX, 796 FeatureSSSE3, 797 FeatureSSE4A, 798 FeatureFXSR, 799 FeatureNOPL, 800 Feature64Bit, 801 FeatureCMPXCHG16B, 802 FeaturePRFCHW, 803 FeatureLZCNT, 804 FeaturePOPCNT, 805 FeatureSlowSHLD, 806 FeatureLAHFSAHF, 807 FeatureFast15ByteNOP, 808 FeatureFastScalarShiftMasks, 809 FeatureFastVectorShiftMasks]; 810 list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures; 811 812 // Jaguar 813 list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX, 814 FeatureAES, 815 FeaturePCLMUL, 816 FeatureBMI, 817 FeatureF16C, 818 FeatureMOVBE, 819 FeatureXSAVE, 820 FeatureXSAVEOPT]; 821 list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT, 822 FeatureFastBEXTR, 823 FeatureFastPartialYMMorZMMWrite, 824 FeatureFastHorizontalOps]; 825 list<SubtargetFeature> BtVer2InheritableFeatures = 826 !listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures); 827 list<SubtargetFeature> BtVer2Features = 828 !listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures); 829 830 // Bulldozer 831 list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87, 832 FeatureCMPXCHG8B, 833 FeatureCMOV, 834 FeatureXOP, 835 Feature64Bit, 836 FeatureCMPXCHG16B, 837 FeatureAES, 838 FeaturePRFCHW, 839 FeaturePCLMUL, 840 FeatureMMX, 841 FeatureFXSR, 842 FeatureNOPL, 843 FeatureLZCNT, 844 FeaturePOPCNT, 845 FeatureXSAVE, 846 FeatureLWP, 847 FeatureSlowSHLD, 848 FeatureLAHFSAHF, 849 FeatureFast11ByteNOP, 850 FeatureFastScalarShiftMasks, 851 FeatureBranchFusion]; 852 list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures; 853 854 // PileDriver 855 list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C, 856 FeatureBMI, 857 FeatureTBM, 858 FeatureFMA, 859 FeatureFastBEXTR]; 860 list<SubtargetFeature> BdVer2InheritableFeatures = 861 !listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures); 862 list<SubtargetFeature> BdVer2Features = BdVer2InheritableFeatures; 863 864 // Steamroller 865 list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT, 866 FeatureFSGSBase]; 867 list<SubtargetFeature> BdVer3InheritableFeatures = 868 !listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures); 869 list<SubtargetFeature> BdVer3Features = BdVer3InheritableFeatures; 870 871 // Excavator 872 list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2, 873 FeatureBMI2, 874 FeatureMWAITX]; 875 list<SubtargetFeature> BdVer4InheritableFeatures = 876 !listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures); 877 list<SubtargetFeature> BdVer4Features = BdVer4InheritableFeatures; 878 879 880 // AMD Zen Processors common ISAs 881 list<SubtargetFeature> ZNFeatures = [FeatureADX, 882 FeatureAES, 883 FeatureAVX2, 884 FeatureBMI, 885 FeatureBMI2, 886 FeatureCLFLUSHOPT, 887 FeatureCLZERO, 888 FeatureCMOV, 889 Feature64Bit, 890 FeatureCMPXCHG16B, 891 FeatureF16C, 892 FeatureFMA, 893 FeatureFSGSBase, 894 FeatureFXSR, 895 FeatureNOPL, 896 FeatureFastLZCNT, 897 FeatureLAHFSAHF, 898 FeatureLZCNT, 899 FeatureFastBEXTR, 900 FeatureFast15ByteNOP, 901 FeatureBranchFusion, 902 FeatureFastScalarShiftMasks, 903 FeatureMMX, 904 FeatureMOVBE, 905 FeatureMWAITX, 906 FeaturePCLMUL, 907 FeaturePOPCNT, 908 FeaturePRFCHW, 909 FeatureRDRAND, 910 FeatureRDSEED, 911 FeatureSHA, 912 FeatureSSE4A, 913 FeatureSlowSHLD, 914 FeatureX87, 915 FeatureXSAVE, 916 FeatureXSAVEC, 917 FeatureXSAVEOPT, 918 FeatureXSAVES]; 919 list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB, 920 FeatureRDPID, 921 FeatureWBNOINVD]; 922 list<SubtargetFeature> ZN2Features = 923 !listconcat(ZNFeatures, ZN2AdditionalFeatures); 924} 925 926//===----------------------------------------------------------------------===// 927// X86 processors supported. 928//===----------------------------------------------------------------------===// 929 930class Proc<string Name, list<SubtargetFeature> Features> 931 : ProcessorModel<Name, GenericModel, Features>; 932 933// NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled 934// if i386/i486 is specifically requested. 935def : Proc<"generic", [FeatureX87, FeatureSlowUAMem16, 936 FeatureCMPXCHG8B]>; 937def : Proc<"i386", [FeatureX87, FeatureSlowUAMem16]>; 938def : Proc<"i486", [FeatureX87, FeatureSlowUAMem16]>; 939def : Proc<"i586", [FeatureX87, FeatureSlowUAMem16, 940 FeatureCMPXCHG8B]>; 941def : Proc<"pentium", [FeatureX87, FeatureSlowUAMem16, 942 FeatureCMPXCHG8B]>; 943def : Proc<"pentium-mmx", [FeatureX87, FeatureSlowUAMem16, 944 FeatureCMPXCHG8B, FeatureMMX]>; 945 946def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 947 FeatureCMOV]>; 948def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 949 FeatureCMOV, FeatureNOPL]>; 950 951def : Proc<"pentium2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 952 FeatureMMX, FeatureCMOV, FeatureFXSR, 953 FeatureNOPL]>; 954 955foreach P = ["pentium3", "pentium3m"] in { 956 def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX, 957 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>; 958} 959 960// Enable the PostRAScheduler for SSE2 and SSE3 class cpus. 961// The intent is to enable it for pentium4 which is the current default 962// processor in a vanilla 32-bit clang compilation when no specific 963// architecture is specified. This generally gives a nice performance 964// increase on silvermont, with largely neutral behavior on other 965// contemporary large core processors. 966// pentium-m, pentium4m, prescott and nocona are included as a preventative 967// measure to avoid performance surprises, in case clang's default cpu 968// changes slightly. 969 970def : ProcessorModel<"pentium-m", GenericPostRAModel, 971 [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 972 FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, 973 FeatureCMOV]>; 974 975foreach P = ["pentium4", "pentium4m"] in { 976 def : ProcessorModel<P, GenericPostRAModel, 977 [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 978 FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL, 979 FeatureCMOV]>; 980} 981 982// Intel Quark. 983def : Proc<"lakemont", []>; 984 985// Intel Core Duo. 986def : ProcessorModel<"yonah", SandyBridgeModel, 987 [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 988 FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, 989 FeatureCMOV]>; 990 991// NetBurst. 992def : ProcessorModel<"prescott", GenericPostRAModel, 993 [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 994 FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL, 995 FeatureCMOV]>; 996def : ProcessorModel<"nocona", GenericPostRAModel, [ 997 FeatureX87, 998 FeatureSlowUAMem16, 999 FeatureCMPXCHG8B, 1000 FeatureCMOV, 1001 FeatureMMX, 1002 FeatureSSE3, 1003 FeatureFXSR, 1004 FeatureNOPL, 1005 Feature64Bit, 1006 FeatureCMPXCHG16B 1007]>; 1008 1009// Intel Core 2 Solo/Duo. 1010def : ProcessorModel<"core2", SandyBridgeModel, [ 1011 FeatureX87, 1012 FeatureSlowUAMem16, 1013 FeatureCMPXCHG8B, 1014 FeatureCMOV, 1015 FeatureMMX, 1016 FeatureSSSE3, 1017 FeatureFXSR, 1018 FeatureNOPL, 1019 Feature64Bit, 1020 FeatureCMPXCHG16B, 1021 FeatureLAHFSAHF, 1022 FeatureMacroFusion 1023]>; 1024def : ProcessorModel<"penryn", SandyBridgeModel, [ 1025 FeatureX87, 1026 FeatureSlowUAMem16, 1027 FeatureCMPXCHG8B, 1028 FeatureCMOV, 1029 FeatureMMX, 1030 FeatureSSE41, 1031 FeatureFXSR, 1032 FeatureNOPL, 1033 Feature64Bit, 1034 FeatureCMPXCHG16B, 1035 FeatureLAHFSAHF, 1036 FeatureMacroFusion 1037]>; 1038 1039// Atom CPUs. 1040foreach P = ["bonnell", "atom"] in { 1041 def : ProcessorModel<P, AtomModel, ProcessorFeatures.AtomFeatures>; 1042} 1043 1044foreach P = ["silvermont", "slm"] in { 1045 def : ProcessorModel<P, SLMModel, ProcessorFeatures.SLMFeatures>; 1046} 1047 1048def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>; 1049def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>; 1050def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>; 1051 1052// "Arrandale" along with corei3 and corei5 1053foreach P = ["nehalem", "corei7"] in { 1054 def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures>; 1055} 1056 1057// Westmere is the corei3/i5/i7 path from nehalem to sandybridge 1058def : ProcessorModel<"westmere", SandyBridgeModel, 1059 ProcessorFeatures.WSMFeatures>; 1060 1061foreach P = ["sandybridge", "corei7-avx"] in { 1062 def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures>; 1063} 1064 1065foreach P = ["ivybridge", "core-avx-i"] in { 1066 def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures>; 1067} 1068 1069foreach P = ["haswell", "core-avx2"] in { 1070 def : ProcessorModel<P, HaswellModel, ProcessorFeatures.HSWFeatures>; 1071} 1072 1073def : ProcessorModel<"broadwell", BroadwellModel, 1074 ProcessorFeatures.BDWFeatures>; 1075 1076def : ProcessorModel<"skylake", SkylakeClientModel, 1077 ProcessorFeatures.SKLFeatures>; 1078 1079// FIXME: define KNL scheduler model 1080def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>; 1081def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>; 1082 1083foreach P = ["skylake-avx512", "skx"] in { 1084 def : ProcessorModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures>; 1085} 1086 1087def : ProcessorModel<"cascadelake", SkylakeServerModel, 1088 ProcessorFeatures.CLXFeatures>; 1089def : ProcessorModel<"cooperlake", SkylakeServerModel, 1090 ProcessorFeatures.CPXFeatures>; 1091def : ProcessorModel<"cannonlake", SkylakeServerModel, 1092 ProcessorFeatures.CNLFeatures>; 1093def : ProcessorModel<"icelake-client", SkylakeServerModel, 1094 ProcessorFeatures.ICLFeatures>; 1095def : ProcessorModel<"icelake-server", SkylakeServerModel, 1096 ProcessorFeatures.ICXFeatures>; 1097 1098// AMD CPUs. 1099 1100def : Proc<"k6", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1101 FeatureMMX]>; 1102def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1103 Feature3DNow]>; 1104def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1105 Feature3DNow]>; 1106 1107foreach P = ["athlon", "athlon-tbird"] in { 1108 def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, 1109 Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>; 1110} 1111 1112foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in { 1113 def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV, 1114 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL, 1115 FeatureSlowSHLD]>; 1116} 1117 1118foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in { 1119 def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1120 FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL, 1121 Feature64Bit, FeatureSlowSHLD, FeatureCMOV, 1122 FeatureFastScalarShiftMasks]>; 1123} 1124 1125foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in { 1126 def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3, 1127 Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, 1128 FeatureSlowSHLD, FeatureCMOV, Feature64Bit, 1129 FeatureFastScalarShiftMasks]>; 1130} 1131 1132foreach P = ["amdfam10", "barcelona"] in { 1133 def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE4A, Feature3DNowA, 1134 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureLZCNT, 1135 FeaturePOPCNT, FeatureSlowSHLD, FeatureLAHFSAHF, FeatureCMOV, 1136 Feature64Bit, FeatureFastScalarShiftMasks]>; 1137} 1138 1139// Bobcat 1140def : Proc<"btver1", ProcessorFeatures.BtVer1Features>; 1141// Jaguar 1142def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>; 1143 1144// Bulldozer 1145def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>; 1146// Piledriver 1147def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>; 1148// Steamroller 1149def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>; 1150// Excavator 1151def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>; 1152 1153def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>; 1154def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>; 1155 1156def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1157 Feature3DNowA]>; 1158 1159def : Proc<"winchip-c6", [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>; 1160def : Proc<"winchip2", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 1161def : Proc<"c3", [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>; 1162def : Proc<"c3-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, 1163 FeatureMMX, FeatureSSE1, FeatureFXSR, 1164 FeatureCMOV]>; 1165 1166// We also provide a generic 64-bit specific x86 processor model which tries to 1167// be good for modern chips without enabling instruction set encodings past the 1168// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and 1169// modern 64-bit x86 chip, and enables features that are generally beneficial. 1170// 1171// We currently use the Sandy Bridge model as the default scheduling model as 1172// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which 1173// covers a huge swath of x86 processors. If there are specific scheduling 1174// knobs which need to be tuned differently for AMD chips, we might consider 1175// forming a common base for them. 1176def : ProcessorModel<"x86-64", SandyBridgeModel, [ 1177 FeatureX87, 1178 FeatureCMPXCHG8B, 1179 FeatureCMOV, 1180 FeatureMMX, 1181 FeatureSSE2, 1182 FeatureFXSR, 1183 FeatureNOPL, 1184 Feature64Bit, 1185 FeatureSlow3OpsLEA, 1186 FeatureSlowIncDec, 1187 FeatureMacroFusion 1188]>; 1189 1190//===----------------------------------------------------------------------===// 1191// Calling Conventions 1192//===----------------------------------------------------------------------===// 1193 1194include "X86CallingConv.td" 1195 1196 1197//===----------------------------------------------------------------------===// 1198// Assembly Parser 1199//===----------------------------------------------------------------------===// 1200 1201def ATTAsmParserVariant : AsmParserVariant { 1202 int Variant = 0; 1203 1204 // Variant name. 1205 string Name = "att"; 1206 1207 // Discard comments in assembly strings. 1208 string CommentDelimiter = "#"; 1209 1210 // Recognize hard coded registers. 1211 string RegisterPrefix = "%"; 1212} 1213 1214def IntelAsmParserVariant : AsmParserVariant { 1215 int Variant = 1; 1216 1217 // Variant name. 1218 string Name = "intel"; 1219 1220 // Discard comments in assembly strings. 1221 string CommentDelimiter = ";"; 1222 1223 // Recognize hard coded registers. 1224 string RegisterPrefix = ""; 1225} 1226 1227//===----------------------------------------------------------------------===// 1228// Assembly Printers 1229//===----------------------------------------------------------------------===// 1230 1231// The X86 target supports two different syntaxes for emitting machine code. 1232// This is controlled by the -x86-asm-syntax={att|intel} 1233def ATTAsmWriter : AsmWriter { 1234 string AsmWriterClassName = "ATTInstPrinter"; 1235 int Variant = 0; 1236} 1237def IntelAsmWriter : AsmWriter { 1238 string AsmWriterClassName = "IntelInstPrinter"; 1239 int Variant = 1; 1240} 1241 1242def X86 : Target { 1243 // Information about the instructions... 1244 let InstructionSet = X86InstrInfo; 1245 let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant]; 1246 let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter]; 1247 let AllowRegisterRenaming = 1; 1248} 1249 1250//===----------------------------------------------------------------------===// 1251// Pfm Counters 1252//===----------------------------------------------------------------------===// 1253 1254include "X86PfmCounters.td" 1255