xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86.td (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is a target description file for the Intel i386 architecture, referred
10// to here as the "X86" architecture.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing...
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// X86 Subtarget state
20//
21// disregarding specific ABI / programming model
22def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
23                               "64-bit mode (x86_64)">;
24def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
25                               "32-bit mode (80386)">;
26def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
27                               "16-bit mode (i8086)">;
28
29//===----------------------------------------------------------------------===//
30// X86 Subtarget ISA features
31//===----------------------------------------------------------------------===//
32
33def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
34                                      "Enable X87 float instructions">;
35
36def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
37                                      "Enable NOPL instruction (generally pentium pro+)">;
38
39def FeatureCMOV    : SubtargetFeature<"cmov","HasCMOV", "true",
40                                      "Enable conditional move instructions">;
41
42def FeatureCX8     : SubtargetFeature<"cx8", "HasCX8", "true",
43                                      "Support CMPXCHG8B instructions">;
44
45def FeatureCRC32   : SubtargetFeature<"crc32", "HasCRC32", "true",
46                                      "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
47
48def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
49                                       "Support POPCNT instruction">;
50
51def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
52                                      "Support fxsave/fxrestore instructions">;
53
54def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
55                                       "Support xsave instructions">;
56
57def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
58                                       "Support xsaveopt instructions",
59                                       [FeatureXSAVE]>;
60
61def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
62                                       "Support xsavec instructions",
63                                       [FeatureXSAVE]>;
64
65def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
66                                       "Support xsaves instructions",
67                                       [FeatureXSAVE]>;
68
69def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
70                                      "Enable SSE instructions">;
71def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
72                                      "Enable SSE2 instructions",
73                                      [FeatureSSE1]>;
74def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
75                                      "Enable SSE3 instructions",
76                                      [FeatureSSE2]>;
77def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
78                                      "Enable SSSE3 instructions",
79                                      [FeatureSSE3]>;
80def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
81                                      "Enable SSE 4.1 instructions",
82                                      [FeatureSSSE3]>;
83def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
84                                      "Enable SSE 4.2 instructions",
85                                      [FeatureSSE41]>;
86// The MMX subtarget feature is separate from the rest of the SSE features
87// because it's important (for odd compatibility reasons) to be able to
88// turn it off explicitly while allowing SSE+ to be on.
89def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
90                                      "Enable MMX instructions">;
91def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
92                                      "Enable 3DNow! instructions",
93                                      [FeatureMMX]>;
94def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
95                                      "Enable 3DNow! Athlon instructions",
96                                      [Feature3DNow]>;
97// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
98// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
99// without disabling 64-bit mode. Nothing should imply this feature bit. It
100// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
101def FeatureX86_64   : SubtargetFeature<"64bit", "HasX86_64", "true",
102                                      "Support 64-bit instructions">;
103def FeatureCX16     : SubtargetFeature<"cx16", "HasCX16", "true",
104                                       "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
105                                       [FeatureCX8]>;
106def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
107                                      "Support SSE 4a instructions",
108                                      [FeatureSSE3]>;
109
110def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
111                                      "Enable AVX instructions",
112                                      [FeatureSSE42]>;
113def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
114                                      "Enable AVX2 instructions",
115                                      [FeatureAVX]>;
116def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
117                                      "Enable three-operand fused multiple-add",
118                                      [FeatureAVX]>;
119def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
120                       "Support 16-bit floating point conversion instructions",
121                       [FeatureAVX]>;
122def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",
123                                      "Enable AVX-512 instructions",
124                                      [FeatureAVX2, FeatureFMA, FeatureF16C]>;
125def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
126                      "Enable AVX-512 Exponential and Reciprocal Instructions",
127                                      [FeatureAVX512]>;
128def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
129                      "Enable AVX-512 Conflict Detection Instructions",
130                                      [FeatureAVX512]>;
131def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
132                       "true", "Enable AVX-512 Population Count Instructions",
133                                      [FeatureAVX512]>;
134def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
135                      "Enable AVX-512 PreFetch Instructions",
136                                      [FeatureAVX512]>;
137def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
138                                   "true",
139                                   "Prefetch with Intent to Write and T1 Hint">;
140def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
141                      "Enable AVX-512 Doubleword and Quadword Instructions",
142                                      [FeatureAVX512]>;
143def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
144                      "Enable AVX-512 Byte and Word Instructions",
145                                      [FeatureAVX512]>;
146def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
147                      "Enable AVX-512 Vector Length eXtensions",
148                                      [FeatureAVX512]>;
149def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
150                      "Enable AVX-512 Vector Byte Manipulation Instructions",
151                                      [FeatureBWI]>;
152def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
153                      "Enable AVX-512 further Vector Byte Manipulation Instructions",
154                                      [FeatureBWI]>;
155def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
156                      "Enable AVX-512 Integer Fused Multiple-Add",
157                                      [FeatureAVX512]>;
158def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
159                      "Enable protection keys">;
160def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
161                          "Enable AVX-512 Vector Neural Network Instructions",
162                                      [FeatureAVX512]>;
163def FeatureAVXVNNI    : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true",
164                           "Support AVX_VNNI encoding",
165                                      [FeatureAVX2]>;
166def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
167                           "Support bfloat16 floating point",
168                                      [FeatureBWI]>;
169def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
170                       "Enable AVX-512 Bit Algorithms",
171                        [FeatureBWI]>;
172def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
173                                            "HasVP2INTERSECT", "true",
174                                            "Enable AVX-512 vp2intersect",
175                                            [FeatureAVX512]>;
176// FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
177// guarded under condition hasVLX. So we imply it in FeatureFP16 currently.
178// FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
179// supposed to be guarded under condition hasDQI. So we imply it in FeatureFP16
180// currently.
181def FeatureFP16    : SubtargetFeature<"avx512fp16", "HasFP16", "true",
182                           "Support 16-bit floating point",
183                           [FeatureBWI, FeatureVLX, FeatureDQI]>;
184def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
185                         "Enable packed carry-less multiplication instructions",
186                               [FeatureSSE2]>;
187def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
188                         "Enable Galois Field Arithmetic Instructions",
189                               [FeatureSSE2]>;
190def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
191                                         "Enable vpclmulqdq instructions",
192                                         [FeatureAVX, FeaturePCLMUL]>;
193def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
194                                      "Enable four-operand fused multiple-add",
195                                      [FeatureAVX, FeatureSSE4A]>;
196def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
197                                      "Enable XOP instructions",
198                                      [FeatureFMA4]>;
199def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
200                                          "HasSSEUnalignedMem", "true",
201                      "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
202def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
203                                      "Enable AES instructions",
204                                      [FeatureSSE2]>;
205def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
206                       "Promote selected AES instructions to AVX512/AVX registers",
207                        [FeatureAVX, FeatureAES]>;
208def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
209                                      "Enable TBM instructions">;
210def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
211                                      "Enable LWP instructions">;
212def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
213                                      "Support MOVBE instruction">;
214def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
215                                      "Support RDRAND instruction">;
216def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
217                                       "Support FS/GS Base instructions">;
218def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
219                                      "Support LZCNT instruction">;
220def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
221                                      "Support BMI instructions">;
222def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
223                                      "Support BMI2 instructions">;
224def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
225                                      "Support RTM instructions">;
226def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
227                                      "Support ADX instructions">;
228def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
229                                      "Enable SHA instructions",
230                                      [FeatureSSE2]>;
231// Processor supports CET SHSTK - Control-Flow Enforcement Technology
232// using Shadow Stack
233def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
234                       "Support CET Shadow-Stack instructions">;
235def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
236                                      "Support PRFCHW instructions">;
237def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
238                                      "Support RDSEED instruction">;
239def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
240                           "Support LAHF and SAHF instructions in 64-bit mode">;
241def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
242                                      "Enable MONITORX/MWAITX timer functionality">;
243def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
244                                      "Enable Cache Line Zero">;
245def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
246                                      "Enable Cache Line Demote">;
247def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
248                                      "Support ptwrite instruction">;
249def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
250                                      "Support AMX-TILE instructions">;
251def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
252                                      "Support AMX-INT8 instructions",
253                                      [FeatureAMXTILE]>;
254def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
255                                      "Support AMX-BF16 instructions",
256                                      [FeatureAMXTILE]>;
257def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
258                                      "Invalidate Process-Context Identifier">;
259def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
260                                      "Enable Software Guard Extensions">;
261def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
262                                      "Flush A Cache Line Optimized">;
263def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
264                                      "Cache Line Write Back">;
265def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
266                                      "Write Back No Invalidate">;
267def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
268                                    "Support RDPID instructions">;
269def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true",
270                                    "Support RDPRU instructions">;
271def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
272                                      "Wait and pause enhancements">;
273def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
274                                     "Has ENQCMD instructions">;
275def FeatureKL  : SubtargetFeature<"kl", "HasKL", "true",
276                                  "Support Key Locker kl Instructions",
277                                  [FeatureSSE2]>;
278def FeatureWIDEKL  : SubtargetFeature<"widekl", "HasWIDEKL", "true",
279                                      "Support Key Locker wide Instructions",
280                                      [FeatureKL]>;
281def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",
282                                      "Has hreset instruction">;
283def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
284                                        "Has serialize instruction">;
285def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
286                                       "Support TSXLDTRK instructions">;
287def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
288                                    "Has UINTR Instructions">;
289def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
290                                      "platform configuration instruction">;
291def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
292                                       "Support movdiri instruction (direct store integer)">;
293def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
294                                        "Support movdir64b instruction (direct store 64 bytes)">;
295
296// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
297// "string operations"). See "REP String Enhancement" in the Intel Software
298// Development Manual. This feature essentially means that REP MOVSB will copy
299// using the largest available size instead of copying bytes one by one, making
300// it at least as fast as REPMOVS{W,D,Q}.
301def FeatureERMSB
302    : SubtargetFeature<
303          "ermsb", "HasERMSB", "true",
304          "REP MOVS/STOS are fast">;
305
306// Icelake and newer processors have Fast Short REP MOV.
307def FeatureFSRM
308    : SubtargetFeature<
309          "fsrm", "HasFSRM", "true",
310          "REP MOVSB of short lengths is faster">;
311
312def FeatureSoftFloat
313    : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
314                       "Use software floating point features">;
315
316//===----------------------------------------------------------------------===//
317// X86 Subtarget Security Mitigation features
318//===----------------------------------------------------------------------===//
319
320// Lower indirect calls using a special construct called a `retpoline` to
321// mitigate potential Spectre v2 attacks against them.
322def FeatureRetpolineIndirectCalls
323    : SubtargetFeature<
324          "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
325          "Remove speculation of indirect calls from the generated code">;
326
327// Lower indirect branches and switches either using conditional branch trees
328// or using a special construct called a `retpoline` to mitigate potential
329// Spectre v2 attacks against them.
330def FeatureRetpolineIndirectBranches
331    : SubtargetFeature<
332          "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
333          "Remove speculation of indirect branches from the generated code">;
334
335// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
336// `retpoline-indirect-branches` above.
337def FeatureRetpoline
338    : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
339                       "Remove speculation of indirect branches from the "
340                       "generated code, either by avoiding them entirely or "
341                       "lowering them with a speculation blocking construct",
342                       [FeatureRetpolineIndirectCalls,
343                        FeatureRetpolineIndirectBranches]>;
344
345// Rely on external thunks for the emitted retpoline calls. This allows users
346// to provide their own custom thunk definitions in highly specialized
347// environments such as a kernel that does boot-time hot patching.
348def FeatureRetpolineExternalThunk
349    : SubtargetFeature<
350          "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
351          "When lowering an indirect call or branch using a `retpoline`, rely "
352          "on the specified user provided thunk rather than emitting one "
353          "ourselves. Only has effect when combined with some other retpoline "
354          "feature", [FeatureRetpolineIndirectCalls]>;
355
356// Mitigate LVI attacks against indirect calls/branches and call returns
357def FeatureLVIControlFlowIntegrity
358    : SubtargetFeature<
359          "lvi-cfi", "UseLVIControlFlowIntegrity", "true",
360          "Prevent indirect calls/branches from using a memory operand, and "
361          "precede all indirect calls/branches from a register with an "
362          "LFENCE instruction to serialize control flow. Also decompose RET "
363          "instructions into a POP+LFENCE+JMP sequence.">;
364
365// Enable SESES to mitigate speculative execution attacks
366def FeatureSpeculativeExecutionSideEffectSuppression
367    : SubtargetFeature<
368          "seses", "UseSpeculativeExecutionSideEffectSuppression", "true",
369          "Prevent speculative execution side channel timing attacks by "
370          "inserting a speculation barrier before memory reads, memory writes, "
371          "and conditional branches. Implies LVI Control Flow integrity.",
372          [FeatureLVIControlFlowIntegrity]>;
373
374// Mitigate LVI attacks against data loads
375def FeatureLVILoadHardening
376    : SubtargetFeature<
377          "lvi-load-hardening", "UseLVILoadHardening", "true",
378          "Insert LFENCE instructions to prevent data speculatively injected "
379          "into loads from being used maliciously.">;
380
381def FeatureTaggedGlobals
382    : SubtargetFeature<
383          "tagged-globals", "AllowTaggedGlobals", "true",
384          "Use an instruction sequence for taking the address of a global "
385          "that allows a memory tag in the upper address bits.">;
386
387// Control codegen mitigation against Straight Line Speculation vulnerability.
388def FeatureHardenSlsRet
389    : SubtargetFeature<
390          "harden-sls-ret", "HardenSlsRet", "true",
391          "Harden against straight line speculation across RET instructions.">;
392
393def FeatureHardenSlsIJmp
394    : SubtargetFeature<
395          "harden-sls-ijmp", "HardenSlsIJmp", "true",
396          "Harden against straight line speculation across indirect JMP instructions.">;
397
398//===----------------------------------------------------------------------===//
399// X86 Subtarget Tuning features
400//===----------------------------------------------------------------------===//
401
402def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
403                                       "SHLD instruction is slow">;
404
405def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
406                                        "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;
407
408def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
409                                          "true",
410                                          "PMADDWD is slower than PMULLD">;
411
412// FIXME: This should not apply to CPUs that do not have SSE.
413def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
414                                "IsUnalignedMem16Slow", "true",
415                                "Slow unaligned 16-byte memory access">;
416
417def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
418                                "IsUnalignedMem32Slow", "true",
419                                "Slow unaligned 32-byte memory access">;
420
421def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
422                                     "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
423
424// True if 8-bit divisions are significantly faster than
425// 32-bit divisions and should be used when possible.
426def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
427                                     "HasSlowDivide32", "true",
428                                     "Use 8-bit divide for positive values less than 256">;
429
430// True if 32-bit divides are significantly faster than
431// 64-bit divisions and should be used when possible.
432def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
433                                     "HasSlowDivide64", "true",
434                                     "Use 32-bit divide for positive values less than 2^32">;
435
436def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
437                                     "PadShortFunctions", "true",
438                                     "Pad short functions (to prevent a stall when returning too early)">;
439
440// On some processors, instructions that implicitly take two memory operands are
441// slow. In practice, this means that CALL, PUSH, and POP with memory operands
442// should be avoided in favor of a MOV + register CALL/PUSH/POP.
443def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
444                                     "SlowTwoMemOps", "true",
445                                     "Two memory operand instructions are slow">;
446
447// True if the LEA instruction inputs have to be ready at address generation
448// (AG) time.
449def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",
450                                   "LEA instruction needs inputs at AG stage">;
451
452def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
453                                   "LEA instruction with certain arguments is slow">;
454
455// True if the LEA instruction has all three source operands: base, index,
456// and offset or if the LEA instruction uses base and index registers where
457// the base is EBP, RBP,or R13
458def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
459                                   "LEA instruction with 3 ops or certain registers is slow">;
460
461// True if INC and DEC instructions are slow when writing to flags
462def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
463                                   "INC and DEC instructions are slower than ADD and SUB">;
464
465def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
466                                     "HasPOPCNTFalseDeps", "true",
467                                     "POPCNT has a false dependency on dest register">;
468
469def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
470                                     "HasLZCNTFalseDeps", "true",
471                                     "LZCNT/TZCNT have a false dependency on dest register">;
472
473def TuningMULCFalseDeps : SubtargetFeature<"false-deps-mulc",
474                               "HasMULCFalseDeps", "true",
475                               "VF[C]MULCPH/SH has a false dependency on dest register">;
476
477def TuningPERMFalseDeps : SubtargetFeature<"false-deps-perm",
478                               "HasPERMFalseDeps", "true",
479                               "VPERMD/Q/PS/PD has a false dependency on dest register">;
480
481def TuningRANGEFalseDeps : SubtargetFeature<"false-deps-range",
482                               "HasRANGEFalseDeps", "true",
483                               "VRANGEPD/PS/SD/SS has a false dependency on dest register">;
484
485def TuningGETMANTFalseDeps : SubtargetFeature<"false-deps-getmant",
486                               "HasGETMANTFalseDeps", "true",
487                               "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a"
488                               " false dependency on dest register">;
489
490def TuningMULLQFalseDeps : SubtargetFeature<"false-deps-mullq",
491                               "HasMULLQFalseDeps", "true",
492                               "VPMULLQ has a false dependency on dest register">;
493
494def TuningSBBDepBreaking : SubtargetFeature<"sbb-dep-breaking",
495                                     "HasSBBDepBreaking", "true",
496                                     "SBB with same register has no source dependency">;
497
498// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
499// using a variable mask over multiple fixed shuffles.
500def TuningFastVariableCrossLaneShuffle
501    : SubtargetFeature<"fast-variable-crosslane-shuffle",
502                       "HasFastVariableCrossLaneShuffle",
503                       "true", "Cross-lane shuffles with variable masks are fast">;
504def TuningFastVariablePerLaneShuffle
505    : SubtargetFeature<"fast-variable-perlane-shuffle",
506                       "HasFastVariablePerLaneShuffle",
507                       "true", "Per-lane shuffles with variable masks are fast">;
508
509// On some X86 processors, a vzeroupper instruction should be inserted after
510// using ymm/zmm registers before executing code that may use SSE instructions.
511def TuningInsertVZEROUPPER
512    : SubtargetFeature<"vzeroupper",
513                       "InsertVZEROUPPER",
514                       "true", "Should insert vzeroupper instructions">;
515
516// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
517// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if
518// vector FSQRT has higher throughput than the corresponding NR code.
519// The idea is that throughput bound code is likely to be vectorized, so for
520// vectorized code we should care about the throughput of SQRT operations.
521// But if the code is scalar that probably means that the code has some kind of
522// dependency and we should care more about reducing the latency.
523
524// True if hardware SQRTSS instruction is at least as fast (latency) as
525// RSQRTSS followed by a Newton-Raphson iteration.
526def TuningFastScalarFSQRT
527    : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
528                       "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
529// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
530// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
531def TuningFastVectorFSQRT
532    : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
533                       "true", "Vector SQRT is fast (disable Newton-Raphson)">;
534
535// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
536// be used to replace test/set sequences.
537def TuningFastLZCNT
538    : SubtargetFeature<
539          "fast-lzcnt", "HasFastLZCNT", "true",
540          "LZCNT instructions are as fast as most simple integer ops">;
541
542// If the target can efficiently decode NOPs upto 7-bytes in length.
543def TuningFast7ByteNOP
544    : SubtargetFeature<
545          "fast-7bytenop", "HasFast7ByteNOP", "true",
546          "Target can quickly decode up to 7 byte NOPs">;
547
548// If the target can efficiently decode NOPs upto 11-bytes in length.
549def TuningFast11ByteNOP
550    : SubtargetFeature<
551          "fast-11bytenop", "HasFast11ByteNOP", "true",
552          "Target can quickly decode up to 11 byte NOPs">;
553
554// If the target can efficiently decode NOPs upto 15-bytes in length.
555def TuningFast15ByteNOP
556    : SubtargetFeature<
557          "fast-15bytenop", "HasFast15ByteNOP", "true",
558          "Target can quickly decode up to 15 byte NOPs">;
559
560// Sandy Bridge and newer processors can use SHLD with the same source on both
561// inputs to implement rotate to avoid the partial flag update of the normal
562// rotate instructions.
563def TuningFastSHLDRotate
564    : SubtargetFeature<
565          "fast-shld-rotate", "HasFastSHLDRotate", "true",
566          "SHLD can be used as a faster rotate">;
567
568// Bulldozer and newer processors can merge CMP/TEST (but not other
569// instructions) with conditional branches.
570def TuningBranchFusion
571    : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
572                 "CMP/TEST can be fused with conditional branches">;
573
574// Sandy Bridge and newer processors have many instructions that can be
575// fused with conditional branches and pass through the CPU as a single
576// operation.
577def TuningMacroFusion
578    : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
579                 "Various instructions can be fused with conditional branches">;
580
581// Gather is available since Haswell (AVX2 set). So technically, we can
582// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
583// Skylake Client processor has faster Gathers than HSW and performance is
584// similar to Skylake Server (AVX-512).
585def TuningFastGather
586    : SubtargetFeature<"fast-gather", "HasFastGather", "true",
587                       "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
588
589def TuningPrefer128Bit
590    : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
591                       "Prefer 128-bit AVX instructions">;
592
593def TuningPrefer256Bit
594    : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
595                       "Prefer 256-bit AVX instructions">;
596
597def TuningPreferMaskRegisters
598    : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
599                       "Prefer AVX512 mask registers over PTEST/MOVMSK">;
600
601def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
602          "Indicates that the BEXTR instruction is implemented as a single uop "
603          "with good throughput">;
604
605// Combine vector math operations with shuffles into horizontal math
606// instructions if a CPU implements horizontal operations (introduced with
607// SSE3) with better latency/throughput than the alternative sequence.
608def TuningFastHorizontalOps
609    : SubtargetFeature<
610        "fast-hops", "HasFastHorizontalOps", "true",
611        "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
612        "normal vector instructions with shuffles">;
613
614def TuningFastScalarShiftMasks
615    : SubtargetFeature<
616        "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
617        "Prefer a left/right scalar logical shift pair over a shift+and pair">;
618
619def TuningFastVectorShiftMasks
620    : SubtargetFeature<
621        "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
622        "Prefer a left/right vector logical shift pair over a shift+and pair">;
623
624def TuningFastMOVBE
625    : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
626    "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
627
628def TuningUseSLMArithCosts
629    : SubtargetFeature<"use-slm-arith-costs", "UseSLMArithCosts", "true",
630        "Use Silvermont specific arithmetic costs">;
631
632def TuningUseGLMDivSqrtCosts
633    : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
634        "Use Goldmont specific floating point div/sqrt costs">;
635
636//===----------------------------------------------------------------------===//
637// X86 CPU Families
638// TODO: Remove these - use general tuning features to determine codegen.
639//===----------------------------------------------------------------------===//
640
641// Bonnell
642def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">;
643
644//===----------------------------------------------------------------------===//
645// Register File Description
646//===----------------------------------------------------------------------===//
647
648include "X86RegisterInfo.td"
649include "X86RegisterBanks.td"
650
651//===----------------------------------------------------------------------===//
652// Instruction Descriptions
653//===----------------------------------------------------------------------===//
654
655include "X86Schedule.td"
656include "X86InstrInfo.td"
657include "X86SchedPredicates.td"
658
659def X86InstrInfo : InstrInfo;
660
661//===----------------------------------------------------------------------===//
662// X86 Scheduler Models
663//===----------------------------------------------------------------------===//
664
665include "X86ScheduleAtom.td"
666include "X86SchedSandyBridge.td"
667include "X86SchedHaswell.td"
668include "X86SchedBroadwell.td"
669include "X86ScheduleSLM.td"
670include "X86ScheduleZnver1.td"
671include "X86ScheduleZnver2.td"
672include "X86ScheduleZnver3.td"
673include "X86ScheduleBdVer2.td"
674include "X86ScheduleBtVer2.td"
675include "X86SchedSkylakeClient.td"
676include "X86SchedSkylakeServer.td"
677include "X86SchedIceLake.td"
678
679//===----------------------------------------------------------------------===//
680// X86 Processor Feature Lists
681//===----------------------------------------------------------------------===//
682
683def ProcessorFeatures {
684  // x86-64 and x86-64-v[234]
685  list<SubtargetFeature> X86_64V1Features = [
686    FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeatureSSE2,
687    FeatureFXSR, FeatureNOPL, FeatureX86_64,
688  ];
689  list<SubtargetFeature> X86_64V2Features = !listconcat(X86_64V1Features, [
690    FeatureCX16, FeatureLAHFSAHF64, FeatureCRC32, FeaturePOPCNT,
691    FeatureSSE42
692  ]);
693  list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [
694    FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT,
695    FeatureMOVBE, FeatureXSAVE
696  ]);
697  list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [
698    FeatureBWI,
699    FeatureCDI,
700    FeatureDQI,
701    FeatureVLX,
702  ]);
703
704  // Nehalem
705  list<SubtargetFeature> NHMFeatures = X86_64V2Features;
706  list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
707                                      TuningInsertVZEROUPPER];
708
709  // Westmere
710  list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
711  list<SubtargetFeature> WSMTuning = NHMTuning;
712  list<SubtargetFeature> WSMFeatures =
713    !listconcat(NHMFeatures, WSMAdditionalFeatures);
714
715  // Sandybridge
716  list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
717                                                  FeatureXSAVE,
718                                                  FeatureXSAVEOPT];
719  list<SubtargetFeature> SNBTuning = [TuningMacroFusion,
720                                      TuningSlow3OpsLEA,
721                                      TuningSlowDivide64,
722                                      TuningSlowUAMem32,
723                                      TuningFastScalarFSQRT,
724                                      TuningFastSHLDRotate,
725                                      TuningFast15ByteNOP,
726                                      TuningPOPCNTFalseDeps,
727                                      TuningInsertVZEROUPPER];
728  list<SubtargetFeature> SNBFeatures =
729    !listconcat(WSMFeatures, SNBAdditionalFeatures);
730
731  // Ivybridge
732  list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
733                                                  FeatureF16C,
734                                                  FeatureFSGSBase];
735  list<SubtargetFeature> IVBTuning = SNBTuning;
736  list<SubtargetFeature> IVBFeatures =
737    !listconcat(SNBFeatures, IVBAdditionalFeatures);
738
739  // Haswell
740  list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
741                                                  FeatureBMI,
742                                                  FeatureBMI2,
743                                                  FeatureERMSB,
744                                                  FeatureFMA,
745                                                  FeatureINVPCID,
746                                                  FeatureLZCNT,
747                                                  FeatureMOVBE];
748  list<SubtargetFeature> HSWTuning = [TuningMacroFusion,
749                                      TuningSlow3OpsLEA,
750                                      TuningSlowDivide64,
751                                      TuningFastScalarFSQRT,
752                                      TuningFastSHLDRotate,
753                                      TuningFast15ByteNOP,
754                                      TuningFastVariableCrossLaneShuffle,
755                                      TuningFastVariablePerLaneShuffle,
756                                      TuningPOPCNTFalseDeps,
757                                      TuningLZCNTFalseDeps,
758                                      TuningInsertVZEROUPPER];
759  list<SubtargetFeature> HSWFeatures =
760    !listconcat(IVBFeatures, HSWAdditionalFeatures);
761
762  // Broadwell
763  list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
764                                                  FeatureRDSEED,
765                                                  FeaturePRFCHW];
766  list<SubtargetFeature> BDWTuning = HSWTuning;
767  list<SubtargetFeature> BDWFeatures =
768    !listconcat(HSWFeatures, BDWAdditionalFeatures);
769
770  // Skylake
771  list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
772                                                  FeatureXSAVEC,
773                                                  FeatureXSAVES,
774                                                  FeatureCLFLUSHOPT];
775  list<SubtargetFeature> SKLTuning = [TuningFastGather,
776                                      TuningMacroFusion,
777                                      TuningSlow3OpsLEA,
778                                      TuningSlowDivide64,
779                                      TuningFastScalarFSQRT,
780                                      TuningFastVectorFSQRT,
781                                      TuningFastSHLDRotate,
782                                      TuningFast15ByteNOP,
783                                      TuningFastVariableCrossLaneShuffle,
784                                      TuningFastVariablePerLaneShuffle,
785                                      TuningPOPCNTFalseDeps,
786                                      TuningInsertVZEROUPPER];
787  list<SubtargetFeature> SKLFeatures =
788    !listconcat(BDWFeatures, SKLAdditionalFeatures);
789
790  // Skylake-AVX512
791  list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
792                                                  FeatureXSAVEC,
793                                                  FeatureXSAVES,
794                                                  FeatureCLFLUSHOPT,
795                                                  FeatureAVX512,
796                                                  FeatureCDI,
797                                                  FeatureDQI,
798                                                  FeatureBWI,
799                                                  FeatureVLX,
800                                                  FeaturePKU,
801                                                  FeatureCLWB];
802  list<SubtargetFeature> SKXTuning = [TuningFastGather,
803                                      TuningMacroFusion,
804                                      TuningSlow3OpsLEA,
805                                      TuningSlowDivide64,
806                                      TuningFastScalarFSQRT,
807                                      TuningFastVectorFSQRT,
808                                      TuningFastSHLDRotate,
809                                      TuningFast15ByteNOP,
810                                      TuningFastVariableCrossLaneShuffle,
811                                      TuningFastVariablePerLaneShuffle,
812                                      TuningPrefer256Bit,
813                                      TuningPOPCNTFalseDeps,
814                                      TuningInsertVZEROUPPER];
815  list<SubtargetFeature> SKXFeatures =
816    !listconcat(BDWFeatures, SKXAdditionalFeatures);
817
818  // Cascadelake
819  list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
820  list<SubtargetFeature> CLXTuning = SKXTuning;
821  list<SubtargetFeature> CLXFeatures =
822    !listconcat(SKXFeatures, CLXAdditionalFeatures);
823
824  // Cooperlake
825  list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
826  list<SubtargetFeature> CPXTuning = SKXTuning;
827  list<SubtargetFeature> CPXFeatures =
828    !listconcat(CLXFeatures, CPXAdditionalFeatures);
829
830  // Cannonlake
831  list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
832                                                  FeatureCDI,
833                                                  FeatureDQI,
834                                                  FeatureBWI,
835                                                  FeatureVLX,
836                                                  FeaturePKU,
837                                                  FeatureVBMI,
838                                                  FeatureIFMA,
839                                                  FeatureSHA];
840  list<SubtargetFeature> CNLTuning = [TuningFastGather,
841                                      TuningMacroFusion,
842                                      TuningSlow3OpsLEA,
843                                      TuningSlowDivide64,
844                                      TuningFastScalarFSQRT,
845                                      TuningFastVectorFSQRT,
846                                      TuningFastSHLDRotate,
847                                      TuningFast15ByteNOP,
848                                      TuningFastVariableCrossLaneShuffle,
849                                      TuningFastVariablePerLaneShuffle,
850                                      TuningPrefer256Bit,
851                                      TuningInsertVZEROUPPER];
852  list<SubtargetFeature> CNLFeatures =
853    !listconcat(SKLFeatures, CNLAdditionalFeatures);
854
855  // Icelake
856  list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
857                                                  FeatureVAES,
858                                                  FeatureVBMI2,
859                                                  FeatureVNNI,
860                                                  FeatureVPCLMULQDQ,
861                                                  FeatureVPOPCNTDQ,
862                                                  FeatureGFNI,
863                                                  FeatureRDPID,
864                                                  FeatureFSRM];
865  list<SubtargetFeature> ICLTuning = [TuningFastGather,
866                                      TuningMacroFusion,
867                                      TuningSlow3OpsLEA,
868                                      TuningSlowDivide64,
869                                      TuningFastScalarFSQRT,
870                                      TuningFastVectorFSQRT,
871                                      TuningFastSHLDRotate,
872                                      TuningFast15ByteNOP,
873                                      TuningFastVariableCrossLaneShuffle,
874                                      TuningFastVariablePerLaneShuffle,
875                                      TuningPrefer256Bit,
876                                      TuningInsertVZEROUPPER];
877  list<SubtargetFeature> ICLFeatures =
878    !listconcat(CNLFeatures, ICLAdditionalFeatures);
879
880  // Icelake Server
881  list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,
882                                                  FeatureCLWB,
883                                                  FeatureWBNOINVD];
884  list<SubtargetFeature> ICXTuning = ICLTuning;
885  list<SubtargetFeature> ICXFeatures =
886    !listconcat(ICLFeatures, ICXAdditionalFeatures);
887
888  // Tigerlake
889  list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
890                                                  FeatureCLWB,
891                                                  FeatureMOVDIRI,
892                                                  FeatureMOVDIR64B,
893                                                  FeatureSHSTK];
894  list<SubtargetFeature> TGLTuning = ICLTuning;
895  list<SubtargetFeature> TGLFeatures =
896    !listconcat(ICLFeatures, TGLAdditionalFeatures );
897
898  // Sapphirerapids
899  list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
900                                                  FeatureAMXINT8,
901                                                  FeatureAMXBF16,
902                                                  FeatureBF16,
903                                                  FeatureSERIALIZE,
904                                                  FeatureCLDEMOTE,
905                                                  FeatureWAITPKG,
906                                                  FeaturePTWRITE,
907                                                  FeatureFP16,
908                                                  FeatureAVXVNNI,
909                                                  FeatureTSXLDTRK,
910                                                  FeatureENQCMD,
911                                                  FeatureSHSTK,
912                                                  FeatureMOVDIRI,
913                                                  FeatureMOVDIR64B,
914                                                  FeatureUINTR];
915  list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps,
916                                                TuningPERMFalseDeps,
917                                                TuningRANGEFalseDeps,
918                                                TuningGETMANTFalseDeps,
919                                                TuningMULLQFalseDeps];
920  list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning);
921  list<SubtargetFeature> SPRFeatures =
922    !listconcat(ICXFeatures, SPRAdditionalFeatures);
923
924  // Atom
925  list<SubtargetFeature> AtomFeatures = [FeatureX87,
926                                         FeatureCX8,
927                                         FeatureCMOV,
928                                         FeatureMMX,
929                                         FeatureSSSE3,
930                                         FeatureFXSR,
931                                         FeatureNOPL,
932                                         FeatureX86_64,
933                                         FeatureCX16,
934                                         FeatureMOVBE,
935                                         FeatureLAHFSAHF64];
936  list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
937                                       TuningSlowUAMem16,
938                                       TuningLEAForSP,
939                                       TuningSlowDivide32,
940                                       TuningSlowDivide64,
941                                       TuningSlowTwoMemOps,
942                                       TuningLEAUsesAG,
943                                       TuningPadShortFunctions,
944                                       TuningInsertVZEROUPPER];
945
946  // Silvermont
947  list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
948                                                  FeatureCRC32,
949                                                  FeaturePOPCNT,
950                                                  FeaturePCLMUL,
951                                                  FeaturePRFCHW,
952                                                  FeatureRDRAND];
953  list<SubtargetFeature> SLMTuning = [TuningUseSLMArithCosts,
954                                      TuningSlowTwoMemOps,
955                                      TuningSlowLEA,
956                                      TuningSlowIncDec,
957                                      TuningSlowDivide64,
958                                      TuningSlowPMULLD,
959                                      TuningFast7ByteNOP,
960                                      TuningFastMOVBE,
961                                      TuningPOPCNTFalseDeps,
962                                      TuningInsertVZEROUPPER];
963  list<SubtargetFeature> SLMFeatures =
964    !listconcat(AtomFeatures, SLMAdditionalFeatures);
965
966  // Goldmont
967  list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
968                                                  FeatureSHA,
969                                                  FeatureRDSEED,
970                                                  FeatureXSAVE,
971                                                  FeatureXSAVEOPT,
972                                                  FeatureXSAVEC,
973                                                  FeatureXSAVES,
974                                                  FeatureCLFLUSHOPT,
975                                                  FeatureFSGSBase];
976  list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,
977                                      TuningSlowTwoMemOps,
978                                      TuningSlowLEA,
979                                      TuningSlowIncDec,
980                                      TuningFastMOVBE,
981                                      TuningPOPCNTFalseDeps,
982                                      TuningInsertVZEROUPPER];
983  list<SubtargetFeature> GLMFeatures =
984    !listconcat(SLMFeatures, GLMAdditionalFeatures);
985
986  // Goldmont Plus
987  list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
988                                                  FeatureRDPID];
989  list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,
990                                      TuningSlowTwoMemOps,
991                                      TuningSlowLEA,
992                                      TuningSlowIncDec,
993                                      TuningFastMOVBE,
994                                      TuningInsertVZEROUPPER];
995  list<SubtargetFeature> GLPFeatures =
996    !listconcat(GLMFeatures, GLPAdditionalFeatures);
997
998  // Tremont
999  list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
1000                                                  FeatureGFNI];
1001  list<SubtargetFeature> TRMTuning = GLPTuning;
1002  list<SubtargetFeature> TRMFeatures =
1003    !listconcat(GLPFeatures, TRMAdditionalFeatures);
1004
1005  // Alderlake
1006  list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,
1007                                                  FeaturePCONFIG,
1008                                                  FeatureSHSTK,
1009                                                  FeatureWIDEKL,
1010                                                  FeatureINVPCID,
1011                                                  FeatureADX,
1012                                                  FeatureFMA,
1013                                                  FeatureVAES,
1014                                                  FeatureVPCLMULQDQ,
1015                                                  FeatureF16C,
1016                                                  FeatureBMI,
1017                                                  FeatureBMI2,
1018                                                  FeatureLZCNT,
1019                                                  FeatureAVXVNNI,
1020                                                  FeaturePKU,
1021                                                  FeatureHRESET,
1022                                                  FeatureCLDEMOTE,
1023                                                  FeatureMOVDIRI,
1024                                                  FeatureMOVDIR64B,
1025                                                  FeatureWAITPKG];
1026  list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps];
1027  list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
1028  list<SubtargetFeature> ADLFeatures =
1029    !listconcat(TRMFeatures, ADLAdditionalFeatures);
1030
1031  // Knights Landing
1032  list<SubtargetFeature> KNLFeatures = [FeatureX87,
1033                                        FeatureCX8,
1034                                        FeatureCMOV,
1035                                        FeatureMMX,
1036                                        FeatureFXSR,
1037                                        FeatureNOPL,
1038                                        FeatureX86_64,
1039                                        FeatureCX16,
1040                                        FeatureCRC32,
1041                                        FeaturePOPCNT,
1042                                        FeaturePCLMUL,
1043                                        FeatureXSAVE,
1044                                        FeatureXSAVEOPT,
1045                                        FeatureLAHFSAHF64,
1046                                        FeatureAES,
1047                                        FeatureRDRAND,
1048                                        FeatureF16C,
1049                                        FeatureFSGSBase,
1050                                        FeatureAVX512,
1051                                        FeatureERI,
1052                                        FeatureCDI,
1053                                        FeaturePFI,
1054                                        FeaturePREFETCHWT1,
1055                                        FeatureADX,
1056                                        FeatureRDSEED,
1057                                        FeatureMOVBE,
1058                                        FeatureLZCNT,
1059                                        FeatureBMI,
1060                                        FeatureBMI2,
1061                                        FeatureFMA,
1062                                        FeaturePRFCHW];
1063  list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,
1064                                      TuningSlow3OpsLEA,
1065                                      TuningSlowIncDec,
1066                                      TuningSlowTwoMemOps,
1067                                      TuningPreferMaskRegisters,
1068                                      TuningFastGather,
1069                                      TuningFastMOVBE,
1070                                      TuningSlowPMADDWD];
1071  // TODO Add AVX5124FMAPS/AVX5124VNNIW features
1072  list<SubtargetFeature> KNMFeatures =
1073    !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
1074
1075  // Barcelona
1076  list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
1077                                              FeatureCX8,
1078                                              FeatureSSE4A,
1079                                              Feature3DNowA,
1080                                              FeatureFXSR,
1081                                              FeatureNOPL,
1082                                              FeatureCX16,
1083                                              FeaturePRFCHW,
1084                                              FeatureLZCNT,
1085                                              FeaturePOPCNT,
1086                                              FeatureLAHFSAHF64,
1087                                              FeatureCMOV,
1088                                              FeatureX86_64];
1089  list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
1090                                            TuningSlowSHLD,
1091                                            TuningSBBDepBreaking,
1092                                            TuningInsertVZEROUPPER];
1093
1094  // Bobcat
1095  list<SubtargetFeature> BtVer1Features = [FeatureX87,
1096                                           FeatureCX8,
1097                                           FeatureCMOV,
1098                                           FeatureMMX,
1099                                           FeatureSSSE3,
1100                                           FeatureSSE4A,
1101                                           FeatureFXSR,
1102                                           FeatureNOPL,
1103                                           FeatureX86_64,
1104                                           FeatureCX16,
1105                                           FeaturePRFCHW,
1106                                           FeatureLZCNT,
1107                                           FeaturePOPCNT,
1108                                           FeatureLAHFSAHF64];
1109  list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
1110                                         TuningFastScalarShiftMasks,
1111                                         TuningFastVectorShiftMasks,
1112                                         TuningSlowSHLD,
1113                                         TuningSBBDepBreaking,
1114                                         TuningInsertVZEROUPPER];
1115
1116  // Jaguar
1117  list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
1118                                                     FeatureAES,
1119                                                     FeatureCRC32,
1120                                                     FeaturePCLMUL,
1121                                                     FeatureBMI,
1122                                                     FeatureF16C,
1123                                                     FeatureMOVBE,
1124                                                     FeatureXSAVE,
1125                                                     FeatureXSAVEOPT];
1126  list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,
1127                                         TuningFastBEXTR,
1128                                         TuningFastHorizontalOps,
1129                                         TuningFast15ByteNOP,
1130                                         TuningFastScalarShiftMasks,
1131                                         TuningFastVectorShiftMasks,
1132                                         TuningFastMOVBE,
1133                                         TuningSBBDepBreaking,
1134                                         TuningSlowSHLD];
1135  list<SubtargetFeature> BtVer2Features =
1136    !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
1137
1138  // Bulldozer
1139  list<SubtargetFeature> BdVer1Features = [FeatureX87,
1140                                           FeatureCX8,
1141                                           FeatureCMOV,
1142                                           FeatureXOP,
1143                                           FeatureX86_64,
1144                                           FeatureCX16,
1145                                           FeatureAES,
1146                                           FeatureCRC32,
1147                                           FeaturePRFCHW,
1148                                           FeaturePCLMUL,
1149                                           FeatureMMX,
1150                                           FeatureFXSR,
1151                                           FeatureNOPL,
1152                                           FeatureLZCNT,
1153                                           FeaturePOPCNT,
1154                                           FeatureXSAVE,
1155                                           FeatureLWP,
1156                                           FeatureLAHFSAHF64];
1157  list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
1158                                         TuningFast11ByteNOP,
1159                                         TuningFastScalarShiftMasks,
1160                                         TuningBranchFusion,
1161                                         TuningSBBDepBreaking,
1162                                         TuningInsertVZEROUPPER];
1163
1164  // PileDriver
1165  list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
1166                                                     FeatureBMI,
1167                                                     FeatureTBM,
1168                                                     FeatureFMA];
1169  list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,
1170                                                   TuningFastMOVBE];
1171  list<SubtargetFeature> BdVer2Tuning =
1172    !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
1173  list<SubtargetFeature> BdVer2Features =
1174    !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
1175
1176  // Steamroller
1177  list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
1178                                                     FeatureFSGSBase];
1179  list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;
1180  list<SubtargetFeature> BdVer3Features =
1181    !listconcat(BdVer2Features, BdVer3AdditionalFeatures);
1182
1183  // Excavator
1184  list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
1185                                                     FeatureBMI2,
1186                                                     FeatureMOVBE,
1187                                                     FeatureRDRAND,
1188                                                     FeatureMWAITX];
1189  list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;
1190  list<SubtargetFeature> BdVer4Features =
1191    !listconcat(BdVer3Features, BdVer4AdditionalFeatures);
1192
1193
1194  // AMD Zen Processors common ISAs
1195  list<SubtargetFeature> ZNFeatures = [FeatureADX,
1196                                       FeatureAES,
1197                                       FeatureAVX2,
1198                                       FeatureBMI,
1199                                       FeatureBMI2,
1200                                       FeatureCLFLUSHOPT,
1201                                       FeatureCLZERO,
1202                                       FeatureCMOV,
1203                                       FeatureX86_64,
1204                                       FeatureCX16,
1205                                       FeatureCRC32,
1206                                       FeatureF16C,
1207                                       FeatureFMA,
1208                                       FeatureFSGSBase,
1209                                       FeatureFXSR,
1210                                       FeatureNOPL,
1211                                       FeatureLAHFSAHF64,
1212                                       FeatureLZCNT,
1213                                       FeatureMMX,
1214                                       FeatureMOVBE,
1215                                       FeatureMWAITX,
1216                                       FeaturePCLMUL,
1217                                       FeaturePOPCNT,
1218                                       FeaturePRFCHW,
1219                                       FeatureRDRAND,
1220                                       FeatureRDSEED,
1221                                       FeatureSHA,
1222                                       FeatureSSE4A,
1223                                       FeatureX87,
1224                                       FeatureXSAVE,
1225                                       FeatureXSAVEC,
1226                                       FeatureXSAVEOPT,
1227                                       FeatureXSAVES];
1228  list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
1229                                     TuningFastBEXTR,
1230                                     TuningFast15ByteNOP,
1231                                     TuningBranchFusion,
1232                                     TuningFastScalarFSQRT,
1233                                     TuningFastVectorFSQRT,
1234                                     TuningFastScalarShiftMasks,
1235                                     TuningFastVariablePerLaneShuffle,
1236                                     TuningFastMOVBE,
1237                                     TuningSlowSHLD,
1238                                     TuningSBBDepBreaking,
1239                                     TuningInsertVZEROUPPER];
1240  list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
1241                                                  FeatureRDPID,
1242                                                  FeatureRDPRU,
1243                                                  FeatureWBNOINVD];
1244  list<SubtargetFeature> ZN2Tuning = ZNTuning;
1245  list<SubtargetFeature> ZN2Features =
1246    !listconcat(ZNFeatures, ZN2AdditionalFeatures);
1247  list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
1248                                                  FeatureINVPCID,
1249                                                  FeaturePKU,
1250                                                  FeatureVAES,
1251                                                  FeatureVPCLMULQDQ];
1252  list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion];
1253  list<SubtargetFeature> ZN3Tuning =
1254    !listconcat(ZN2Tuning, ZN3AdditionalTuning);
1255  list<SubtargetFeature> ZN3Features =
1256    !listconcat(ZN2Features, ZN3AdditionalFeatures);
1257}
1258
1259//===----------------------------------------------------------------------===//
1260// X86 processors supported.
1261//===----------------------------------------------------------------------===//
1262
1263class Proc<string Name, list<SubtargetFeature> Features,
1264           list<SubtargetFeature> TuneFeatures>
1265 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>;
1266
1267class ProcModel<string Name, SchedMachineModel Model,
1268                list<SubtargetFeature> Features,
1269                list<SubtargetFeature> TuneFeatures>
1270 : ProcessorModel<Name, Model, Features, TuneFeatures>;
1271
1272// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
1273// if i386/i486 is specifically requested.
1274// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
1275// constructor checks that any CPU used in 64-bit mode has FeatureX86_64
1276// enabled. It has no effect on code generation.
1277// NOTE: As a default tuning, "generic" aims to produce code optimized for the
1278// most common X86 processors. The tunings might be changed over time. It is
1279// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.
1280def : ProcModel<"generic", SandyBridgeModel,
1281                [FeatureX87, FeatureCX8, FeatureX86_64],
1282                [TuningSlow3OpsLEA,
1283                 TuningSlowDivide64,
1284                 TuningMacroFusion,
1285                 TuningFastScalarFSQRT,
1286                 TuningFast15ByteNOP,
1287                 TuningInsertVZEROUPPER]>;
1288
1289def : Proc<"i386",            [FeatureX87],
1290                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1291def : Proc<"i486",            [FeatureX87],
1292                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1293def : Proc<"i586",            [FeatureX87, FeatureCX8],
1294                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1295def : Proc<"pentium",         [FeatureX87, FeatureCX8],
1296                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1297def : Proc<"pentium-mmx",     [FeatureX87, FeatureCX8, FeatureMMX],
1298                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1299
1300def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV],
1301                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1302def : Proc<"pentiumpro", [FeatureX87, FeatureCX8, FeatureCMOV,
1303                          FeatureNOPL],
1304                         [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1305
1306def : Proc<"pentium2", [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,
1307                        FeatureFXSR, FeatureNOPL],
1308                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1309
1310foreach P = ["pentium3", "pentium3m"] in {
1311  def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX,
1312                 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
1313                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1314}
1315
1316// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
1317// The intent is to enable it for pentium4 which is the current default
1318// processor in a vanilla 32-bit clang compilation when no specific
1319// architecture is specified.  This generally gives a nice performance
1320// increase on silvermont, with largely neutral behavior on other
1321// contemporary large core processors.
1322// pentium-m, pentium4m, prescott and nocona are included as a preventative
1323// measure to avoid performance surprises, in case clang's default cpu
1324// changes slightly.
1325
1326def : ProcModel<"pentium-m", GenericPostRAModel,
1327                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1328                FeatureFXSR, FeatureNOPL, FeatureCMOV],
1329                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1330
1331foreach P = ["pentium4", "pentium4m"] in {
1332  def : ProcModel<P, GenericPostRAModel,
1333                  [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1334                   FeatureFXSR, FeatureNOPL, FeatureCMOV],
1335                  [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1336}
1337
1338// Intel Quark.
1339def : Proc<"lakemont", [FeatureCX8],
1340                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1341
1342// Intel Core Duo.
1343def : ProcModel<"yonah", SandyBridgeModel,
1344                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1345                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1346                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1347
1348// NetBurst.
1349def : ProcModel<"prescott", GenericPostRAModel,
1350                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1351                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1352                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1353def : ProcModel<"nocona", GenericPostRAModel, [
1354  FeatureX87,
1355  FeatureCX8,
1356  FeatureCMOV,
1357  FeatureMMX,
1358  FeatureSSE3,
1359  FeatureFXSR,
1360  FeatureNOPL,
1361  FeatureX86_64,
1362  FeatureCX16,
1363],
1364[
1365  TuningSlowUAMem16,
1366  TuningInsertVZEROUPPER
1367]>;
1368
1369// Intel Core 2 Solo/Duo.
1370def : ProcModel<"core2", SandyBridgeModel, [
1371  FeatureX87,
1372  FeatureCX8,
1373  FeatureCMOV,
1374  FeatureMMX,
1375  FeatureSSSE3,
1376  FeatureFXSR,
1377  FeatureNOPL,
1378  FeatureX86_64,
1379  FeatureCX16,
1380  FeatureLAHFSAHF64
1381],
1382[
1383  TuningMacroFusion,
1384  TuningSlowUAMem16,
1385  TuningInsertVZEROUPPER
1386]>;
1387def : ProcModel<"penryn", SandyBridgeModel, [
1388  FeatureX87,
1389  FeatureCX8,
1390  FeatureCMOV,
1391  FeatureMMX,
1392  FeatureSSE41,
1393  FeatureFXSR,
1394  FeatureNOPL,
1395  FeatureX86_64,
1396  FeatureCX16,
1397  FeatureLAHFSAHF64
1398],
1399[
1400  TuningMacroFusion,
1401  TuningSlowUAMem16,
1402  TuningInsertVZEROUPPER
1403]>;
1404
1405// Atom CPUs.
1406foreach P = ["bonnell", "atom"] in {
1407  def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
1408                  ProcessorFeatures.AtomTuning>;
1409}
1410
1411foreach P = ["silvermont", "slm"] in {
1412  def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
1413                  ProcessorFeatures.SLMTuning>;
1414}
1415
1416def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
1417                ProcessorFeatures.GLMTuning>;
1418def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
1419                ProcessorFeatures.GLPTuning>;
1420def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
1421                ProcessorFeatures.TRMTuning>;
1422
1423// "Arrandale" along with corei3 and corei5
1424foreach P = ["nehalem", "corei7"] in {
1425  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
1426                  ProcessorFeatures.NHMTuning>;
1427}
1428
1429// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1430def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
1431                ProcessorFeatures.WSMTuning>;
1432
1433foreach P = ["sandybridge", "corei7-avx"] in {
1434  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
1435                  ProcessorFeatures.SNBTuning>;
1436}
1437
1438foreach P = ["ivybridge", "core-avx-i"] in {
1439  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
1440                  ProcessorFeatures.IVBTuning>;
1441}
1442
1443foreach P = ["haswell", "core-avx2"] in {
1444  def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
1445                  ProcessorFeatures.HSWTuning>;
1446}
1447
1448def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
1449                ProcessorFeatures.BDWTuning>;
1450
1451def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
1452                ProcessorFeatures.SKLTuning>;
1453
1454// FIXME: define KNL scheduler model
1455def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
1456                ProcessorFeatures.KNLTuning>;
1457def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
1458                ProcessorFeatures.KNLTuning>;
1459
1460foreach P = ["skylake-avx512", "skx"] in {
1461  def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
1462                  ProcessorFeatures.SKXTuning>;
1463}
1464
1465def : ProcModel<"cascadelake", SkylakeServerModel,
1466                ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
1467def : ProcModel<"cooperlake", SkylakeServerModel,
1468                ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
1469def : ProcModel<"cannonlake", SkylakeServerModel,
1470                ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
1471def : ProcModel<"icelake-client", IceLakeModel,
1472                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1473def : ProcModel<"rocketlake", IceLakeModel,
1474                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1475def : ProcModel<"icelake-server", IceLakeModel,
1476                ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
1477def : ProcModel<"tigerlake", IceLakeModel,
1478                ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
1479def : ProcModel<"sapphirerapids", SkylakeServerModel,
1480                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1481def : ProcModel<"alderlake", SkylakeClientModel,
1482                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1483
1484// AMD CPUs.
1485
1486def : Proc<"k6",   [FeatureX87, FeatureCX8, FeatureMMX],
1487                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1488def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
1489                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1490def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],
1491                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1492
1493foreach P = ["athlon", "athlon-tbird"] in {
1494  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, Feature3DNowA,
1495                 FeatureNOPL],
1496                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1497}
1498
1499foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1500  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
1501                 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
1502                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1503}
1504
1505foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1506  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, Feature3DNowA,
1507                 FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
1508                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1509                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1510}
1511
1512foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1513  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, Feature3DNowA,
1514                 FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,
1515                 FeatureX86_64],
1516                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1517                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1518}
1519
1520foreach P = ["amdfam10", "barcelona"] in {
1521  def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
1522             ProcessorFeatures.BarcelonaTuning>;
1523}
1524
1525// Bobcat
1526def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
1527           ProcessorFeatures.BtVer1Tuning>;
1528// Jaguar
1529def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,
1530                ProcessorFeatures.BtVer2Tuning>;
1531
1532// Bulldozer
1533def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,
1534                ProcessorFeatures.BdVer1Tuning>;
1535// Piledriver
1536def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,
1537                ProcessorFeatures.BdVer2Tuning>;
1538// Steamroller
1539def : Proc<"bdver3", ProcessorFeatures.BdVer3Features,
1540           ProcessorFeatures.BdVer3Tuning>;
1541// Excavator
1542def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
1543           ProcessorFeatures.BdVer4Tuning>;
1544
1545def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
1546                ProcessorFeatures.ZNTuning>;
1547def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
1548                ProcessorFeatures.ZN2Tuning>;
1549def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
1550                ProcessorFeatures.ZN3Tuning>;
1551
1552def : Proc<"geode",           [FeatureX87, FeatureCX8, Feature3DNowA],
1553                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1554
1555def : Proc<"winchip-c6",      [FeatureX87, FeatureMMX],
1556                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1557def : Proc<"winchip2",        [FeatureX87, Feature3DNow],
1558                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1559def : Proc<"c3",              [FeatureX87, Feature3DNow],
1560                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1561def : Proc<"c3-2",            [FeatureX87, FeatureCX8, FeatureMMX,
1562                               FeatureSSE1, FeatureFXSR, FeatureCMOV],
1563                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1564
1565// We also provide a generic 64-bit specific x86 processor model which tries to
1566// be good for modern chips without enabling instruction set encodings past the
1567// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1568// modern 64-bit x86 chip, and enables features that are generally beneficial.
1569//
1570// We currently use the Sandy Bridge model as the default scheduling model as
1571// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1572// covers a huge swath of x86 processors. If there are specific scheduling
1573// knobs which need to be tuned differently for AMD chips, we might consider
1574// forming a common base for them.
1575def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
1576[
1577  TuningSlow3OpsLEA,
1578  TuningSlowDivide64,
1579  TuningSlowIncDec,
1580  TuningMacroFusion,
1581  TuningInsertVZEROUPPER
1582]>;
1583
1584// x86-64 micro-architecture levels.
1585def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
1586                ProcessorFeatures.SNBTuning>;
1587// Close to Haswell.
1588def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
1589                ProcessorFeatures.HSWTuning>;
1590// Close to the AVX-512 level implemented by Xeon Scalable Processors.
1591def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,
1592                ProcessorFeatures.SKXTuning>;
1593
1594//===----------------------------------------------------------------------===//
1595// Calling Conventions
1596//===----------------------------------------------------------------------===//
1597
1598include "X86CallingConv.td"
1599
1600
1601//===----------------------------------------------------------------------===//
1602// Assembly Parser
1603//===----------------------------------------------------------------------===//
1604
1605def ATTAsmParserVariant : AsmParserVariant {
1606  int Variant = 0;
1607
1608  // Variant name.
1609  string Name = "att";
1610
1611  // Discard comments in assembly strings.
1612  string CommentDelimiter = "#";
1613
1614  // Recognize hard coded registers.
1615  string RegisterPrefix = "%";
1616}
1617
1618def IntelAsmParserVariant : AsmParserVariant {
1619  int Variant = 1;
1620
1621  // Variant name.
1622  string Name = "intel";
1623
1624  // Discard comments in assembly strings.
1625  string CommentDelimiter = ";";
1626
1627  // Recognize hard coded registers.
1628  string RegisterPrefix = "";
1629}
1630
1631//===----------------------------------------------------------------------===//
1632// Assembly Printers
1633//===----------------------------------------------------------------------===//
1634
1635// The X86 target supports two different syntaxes for emitting machine code.
1636// This is controlled by the -x86-asm-syntax={att|intel}
1637def ATTAsmWriter : AsmWriter {
1638  string AsmWriterClassName  = "ATTInstPrinter";
1639  int Variant = 0;
1640}
1641def IntelAsmWriter : AsmWriter {
1642  string AsmWriterClassName  = "IntelInstPrinter";
1643  int Variant = 1;
1644}
1645
1646def X86 : Target {
1647  // Information about the instructions...
1648  let InstructionSet = X86InstrInfo;
1649  let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1650  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1651  let AllowRegisterRenaming = 1;
1652}
1653
1654//===----------------------------------------------------------------------===//
1655// Pfm Counters
1656//===----------------------------------------------------------------------===//
1657
1658include "X86PfmCounters.td"
1659