xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86.td (revision ba3c1f5972d7b90feb6e6da47905ff2757e0fe57) 
1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is a target description file for the Intel i386 architecture, referred
10// to here as the "X86" architecture.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing...
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// X86 Subtarget state
20//
21// disregarding specific ABI / programming model
22def Is64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true",
23                               "64-bit mode (x86_64)">;
24def Is32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true",
25                               "32-bit mode (80386)">;
26def Is16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true",
27                               "16-bit mode (i8086)">;
28
29//===----------------------------------------------------------------------===//
30// X86 Subtarget ISA features
31//===----------------------------------------------------------------------===//
32
33def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
34                                      "Enable X87 float instructions">;
35
36def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
37                                      "Enable NOPL instruction (generally pentium pro+)">;
38
39def FeatureCMOV    : SubtargetFeature<"cmov","HasCMOV", "true",
40                                      "Enable conditional move instructions">;
41
42def FeatureCX8     : SubtargetFeature<"cx8", "HasCX8", "true",
43                                      "Support CMPXCHG8B instructions">;
44
45def FeatureCRC32   : SubtargetFeature<"crc32", "HasCRC32", "true",
46                                      "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)">;
47
48def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
49                                       "Support POPCNT instruction">;
50
51def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
52                                      "Support fxsave/fxrestore instructions">;
53
54def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
55                                       "Support xsave instructions">;
56
57def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
58                                       "Support xsaveopt instructions",
59                                       [FeatureXSAVE]>;
60
61def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
62                                       "Support xsavec instructions",
63                                       [FeatureXSAVE]>;
64
65def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
66                                       "Support xsaves instructions",
67                                       [FeatureXSAVE]>;
68
69def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
70                                      "Enable SSE instructions">;
71def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
72                                      "Enable SSE2 instructions",
73                                      [FeatureSSE1]>;
74def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
75                                      "Enable SSE3 instructions",
76                                      [FeatureSSE2]>;
77def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
78                                      "Enable SSSE3 instructions",
79                                      [FeatureSSE3]>;
80def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
81                                      "Enable SSE 4.1 instructions",
82                                      [FeatureSSSE3]>;
83def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
84                                      "Enable SSE 4.2 instructions",
85                                      [FeatureSSE41]>;
86// The MMX subtarget feature is separate from the rest of the SSE features
87// because it's important (for odd compatibility reasons) to be able to
88// turn it off explicitly while allowing SSE+ to be on.
89def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
90                                      "Enable MMX instructions">;
91def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
92                                      "Enable 3DNow! instructions",
93                                      [FeatureMMX]>;
94def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
95                                      "Enable 3DNow! Athlon instructions",
96                                      [Feature3DNow]>;
97// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
98// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
99// without disabling 64-bit mode. Nothing should imply this feature bit. It
100// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
101def FeatureX86_64   : SubtargetFeature<"64bit", "HasX86_64", "true",
102                                      "Support 64-bit instructions">;
103def FeatureCX16     : SubtargetFeature<"cx16", "HasCX16", "true",
104                                       "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
105                                       [FeatureCX8]>;
106def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
107                                      "Support SSE 4a instructions",
108                                      [FeatureSSE3]>;
109
110def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
111                                      "Enable AVX instructions",
112                                      [FeatureSSE42]>;
113def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
114                                      "Enable AVX2 instructions",
115                                      [FeatureAVX]>;
116def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
117                                      "Enable three-operand fused multiple-add",
118                                      [FeatureAVX]>;
119def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
120                       "Support 16-bit floating point conversion instructions",
121                       [FeatureAVX]>;
122def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512",
123                                      "Enable AVX-512 instructions",
124                                      [FeatureAVX2, FeatureFMA, FeatureF16C]>;
125def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
126                      "Enable AVX-512 Exponential and Reciprocal Instructions",
127                                      [FeatureAVX512]>;
128def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
129                      "Enable AVX-512 Conflict Detection Instructions",
130                                      [FeatureAVX512]>;
131def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
132                       "true", "Enable AVX-512 Population Count Instructions",
133                                      [FeatureAVX512]>;
134def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
135                      "Enable AVX-512 PreFetch Instructions",
136                                      [FeatureAVX512]>;
137def FeaturePREFETCHI  : SubtargetFeature<"prefetchi", "HasPREFETCHI",
138                                   "true",
139                                   "Prefetch instruction with T0 or T1 Hint">;
140def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
141                                   "true",
142                                   "Prefetch with Intent to Write and T1 Hint">;
143def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
144                      "Enable AVX-512 Doubleword and Quadword Instructions",
145                                      [FeatureAVX512]>;
146def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
147                      "Enable AVX-512 Byte and Word Instructions",
148                                      [FeatureAVX512]>;
149def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
150                      "Enable AVX-512 Vector Length eXtensions",
151                                      [FeatureAVX512]>;
152def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
153                      "Enable AVX-512 Vector Byte Manipulation Instructions",
154                                      [FeatureBWI]>;
155def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
156                      "Enable AVX-512 further Vector Byte Manipulation Instructions",
157                                      [FeatureBWI]>;
158def FeatureAVXIFMA    : SubtargetFeature<"avxifma", "HasAVXIFMA", "true",
159                           "Enable AVX-IFMA",
160                           [FeatureAVX2]>;
161def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
162                      "Enable AVX-512 Integer Fused Multiple-Add",
163                                      [FeatureAVX512]>;
164def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
165                      "Enable protection keys">;
166def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
167                          "Enable AVX-512 Vector Neural Network Instructions",
168                                      [FeatureAVX512]>;
169def FeatureAVXVNNI    : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true",
170                           "Support AVX_VNNI encoding",
171                                      [FeatureAVX2]>;
172def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
173                           "Support bfloat16 floating point",
174                                      [FeatureBWI]>;
175def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
176                       "Enable AVX-512 Bit Algorithms",
177                        [FeatureBWI]>;
178def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
179                                            "HasVP2INTERSECT", "true",
180                                            "Enable AVX-512 vp2intersect",
181                                            [FeatureAVX512]>;
182// FIXME: FP16 scalar intrinsics use the type v8f16, which is supposed to be
183// guarded under condition hasVLX. So we imply it in FeatureFP16 currently.
184// FIXME: FP16 conversion between f16 and i64 customize type v8i64, which is
185// supposed to be guarded under condition hasDQI. So we imply it in FeatureFP16
186// currently.
187def FeatureFP16    : SubtargetFeature<"avx512fp16", "HasFP16", "true",
188                           "Support 16-bit floating point",
189                           [FeatureBWI, FeatureVLX, FeatureDQI]>;
190def FeatureAVXVNNIINT8  : SubtargetFeature<"avxvnniint8",
191                             "HasAVXVNNIINT8", "true",
192                             "Enable AVX-VNNI-INT8",
193                             [FeatureAVX2]>;
194def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
195                         "Enable packed carry-less multiplication instructions",
196                               [FeatureSSE2]>;
197def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
198                         "Enable Galois Field Arithmetic Instructions",
199                               [FeatureSSE2]>;
200def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
201                                         "Enable vpclmulqdq instructions",
202                                         [FeatureAVX, FeaturePCLMUL]>;
203def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
204                                      "Enable four-operand fused multiple-add",
205                                      [FeatureAVX, FeatureSSE4A]>;
206def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
207                                      "Enable XOP instructions",
208                                      [FeatureFMA4]>;
209def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
210                                          "HasSSEUnalignedMem", "true",
211                      "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)">;
212def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
213                                      "Enable AES instructions",
214                                      [FeatureSSE2]>;
215def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
216                       "Promote selected AES instructions to AVX512/AVX registers",
217                        [FeatureAVX, FeatureAES]>;
218def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
219                                      "Enable TBM instructions">;
220def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
221                                      "Enable LWP instructions">;
222def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
223                                      "Support MOVBE instruction">;
224def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
225                                      "Support RDRAND instruction">;
226def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
227                                       "Support FS/GS Base instructions">;
228def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
229                                      "Support LZCNT instruction">;
230def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
231                                      "Support BMI instructions">;
232def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
233                                      "Support BMI2 instructions">;
234def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
235                                      "Support RTM instructions">;
236def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
237                                      "Support ADX instructions">;
238def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
239                                      "Enable SHA instructions",
240                                      [FeatureSSE2]>;
241// Processor supports CET SHSTK - Control-Flow Enforcement Technology
242// using Shadow Stack
243def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
244                       "Support CET Shadow-Stack instructions">;
245def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
246                                      "Support PRFCHW instructions">;
247def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
248                                      "Support RDSEED instruction">;
249def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
250                           "Support LAHF and SAHF instructions in 64-bit mode">;
251def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
252                                      "Enable MONITORX/MWAITX timer functionality">;
253def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
254                                      "Enable Cache Line Zero">;
255def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
256                                      "Enable Cache Line Demote">;
257def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
258                                      "Support ptwrite instruction">;
259def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
260                                      "Support AMX-TILE instructions">;
261def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
262                                      "Support AMX-INT8 instructions",
263                                      [FeatureAMXTILE]>;
264def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
265                                      "Support AMX-BF16 instructions",
266                                      [FeatureAMXTILE]>;
267def FeatureAMXFP16     : SubtargetFeature<"amx-fp16", "HasAMXFP16", "true",
268                                      "Support AMX amx-fp16 instructions",
269                                      [FeatureAMXTILE]>;
270def FeatureCMPCCXADD : SubtargetFeature<"cmpccxadd", "HasCMPCCXADD", "true",
271                                        "Support CMPCCXADD instructions">;
272def FeatureRAOINT : SubtargetFeature<"raoint", "HasRAOINT", "true",
273                                     "Support RAO-INT instructions",
274                                     []>;
275def FeatureAVXNECONVERT : SubtargetFeature<"avxneconvert", "HasAVXNECONVERT", "true",
276                                           "Support AVX-NE-CONVERT instructions",
277                                           [FeatureAVX2]>;
278def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
279                                      "Invalidate Process-Context Identifier">;
280def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
281                                      "Enable Software Guard Extensions">;
282def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
283                                      "Flush A Cache Line Optimized">;
284def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
285                                      "Cache Line Write Back">;
286def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
287                                      "Write Back No Invalidate">;
288def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
289                                    "Support RDPID instructions">;
290def FeatureRDPRU : SubtargetFeature<"rdpru", "HasRDPRU", "true",
291                                    "Support RDPRU instructions">;
292def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
293                                      "Wait and pause enhancements">;
294def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
295                                     "Has ENQCMD instructions">;
296def FeatureKL  : SubtargetFeature<"kl", "HasKL", "true",
297                                  "Support Key Locker kl Instructions",
298                                  [FeatureSSE2]>;
299def FeatureWIDEKL  : SubtargetFeature<"widekl", "HasWIDEKL", "true",
300                                      "Support Key Locker wide Instructions",
301                                      [FeatureKL]>;
302def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",
303                                      "Has hreset instruction">;
304def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
305                                        "Has serialize instruction">;
306def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
307                                       "Support TSXLDTRK instructions">;
308def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
309                                    "Has UINTR Instructions">;
310def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
311                                      "platform configuration instruction">;
312def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
313                                       "Support movdiri instruction (direct store integer)">;
314def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
315                                        "Support movdir64b instruction (direct store 64 bytes)">;
316
317// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
318// "string operations"). See "REP String Enhancement" in the Intel Software
319// Development Manual. This feature essentially means that REP MOVSB will copy
320// using the largest available size instead of copying bytes one by one, making
321// it at least as fast as REPMOVS{W,D,Q}.
322def FeatureERMSB
323    : SubtargetFeature<
324          "ermsb", "HasERMSB", "true",
325          "REP MOVS/STOS are fast">;
326
327// Icelake and newer processors have Fast Short REP MOV.
328def FeatureFSRM
329    : SubtargetFeature<
330          "fsrm", "HasFSRM", "true",
331          "REP MOVSB of short lengths is faster">;
332
333def FeatureSoftFloat
334    : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
335                       "Use software floating point features">;
336
337//===----------------------------------------------------------------------===//
338// X86 Subtarget Security Mitigation features
339//===----------------------------------------------------------------------===//
340
341// Lower indirect calls using a special construct called a `retpoline` to
342// mitigate potential Spectre v2 attacks against them.
343def FeatureRetpolineIndirectCalls
344    : SubtargetFeature<
345          "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
346          "Remove speculation of indirect calls from the generated code">;
347
348// Lower indirect branches and switches either using conditional branch trees
349// or using a special construct called a `retpoline` to mitigate potential
350// Spectre v2 attacks against them.
351def FeatureRetpolineIndirectBranches
352    : SubtargetFeature<
353          "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
354          "Remove speculation of indirect branches from the generated code">;
355
356// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
357// `retpoline-indirect-branches` above.
358def FeatureRetpoline
359    : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
360                       "Remove speculation of indirect branches from the "
361                       "generated code, either by avoiding them entirely or "
362                       "lowering them with a speculation blocking construct",
363                       [FeatureRetpolineIndirectCalls,
364                        FeatureRetpolineIndirectBranches]>;
365
366// Rely on external thunks for the emitted retpoline calls. This allows users
367// to provide their own custom thunk definitions in highly specialized
368// environments such as a kernel that does boot-time hot patching.
369def FeatureRetpolineExternalThunk
370    : SubtargetFeature<
371          "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
372          "When lowering an indirect call or branch using a `retpoline`, rely "
373          "on the specified user provided thunk rather than emitting one "
374          "ourselves. Only has effect when combined with some other retpoline "
375          "feature", [FeatureRetpolineIndirectCalls]>;
376
377// Mitigate LVI attacks against indirect calls/branches and call returns
378def FeatureLVIControlFlowIntegrity
379    : SubtargetFeature<
380          "lvi-cfi", "UseLVIControlFlowIntegrity", "true",
381          "Prevent indirect calls/branches from using a memory operand, and "
382          "precede all indirect calls/branches from a register with an "
383          "LFENCE instruction to serialize control flow. Also decompose RET "
384          "instructions into a POP+LFENCE+JMP sequence.">;
385
386// Enable SESES to mitigate speculative execution attacks
387def FeatureSpeculativeExecutionSideEffectSuppression
388    : SubtargetFeature<
389          "seses", "UseSpeculativeExecutionSideEffectSuppression", "true",
390          "Prevent speculative execution side channel timing attacks by "
391          "inserting a speculation barrier before memory reads, memory writes, "
392          "and conditional branches. Implies LVI Control Flow integrity.",
393          [FeatureLVIControlFlowIntegrity]>;
394
395// Mitigate LVI attacks against data loads
396def FeatureLVILoadHardening
397    : SubtargetFeature<
398          "lvi-load-hardening", "UseLVILoadHardening", "true",
399          "Insert LFENCE instructions to prevent data speculatively injected "
400          "into loads from being used maliciously.">;
401
402def FeatureTaggedGlobals
403    : SubtargetFeature<
404          "tagged-globals", "AllowTaggedGlobals", "true",
405          "Use an instruction sequence for taking the address of a global "
406          "that allows a memory tag in the upper address bits.">;
407
408// Control codegen mitigation against Straight Line Speculation vulnerability.
409def FeatureHardenSlsRet
410    : SubtargetFeature<
411          "harden-sls-ret", "HardenSlsRet", "true",
412          "Harden against straight line speculation across RET instructions.">;
413
414def FeatureHardenSlsIJmp
415    : SubtargetFeature<
416          "harden-sls-ijmp", "HardenSlsIJmp", "true",
417          "Harden against straight line speculation across indirect JMP instructions.">;
418
419//===----------------------------------------------------------------------===//
420// X86 Subtarget Tuning features
421//===----------------------------------------------------------------------===//
422
423def TuningSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
424                                       "SHLD instruction is slow">;
425
426def TuningSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
427                                        "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)">;
428
429def TuningSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
430                                          "true",
431                                          "PMADDWD is slower than PMULLD">;
432
433// FIXME: This should not apply to CPUs that do not have SSE.
434def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
435                                "IsUnalignedMem16Slow", "true",
436                                "Slow unaligned 16-byte memory access">;
437
438def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
439                                "IsUnalignedMem32Slow", "true",
440                                "Slow unaligned 32-byte memory access">;
441
442def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
443                                     "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)">;
444
445// True if 8-bit divisions are significantly faster than
446// 32-bit divisions and should be used when possible.
447def TuningSlowDivide32 : SubtargetFeature<"idivl-to-divb",
448                                     "HasSlowDivide32", "true",
449                                     "Use 8-bit divide for positive values less than 256">;
450
451// True if 32-bit divides are significantly faster than
452// 64-bit divisions and should be used when possible.
453def TuningSlowDivide64 : SubtargetFeature<"idivq-to-divl",
454                                     "HasSlowDivide64", "true",
455                                     "Use 32-bit divide for positive values less than 2^32">;
456
457def TuningPadShortFunctions : SubtargetFeature<"pad-short-functions",
458                                     "PadShortFunctions", "true",
459                                     "Pad short functions (to prevent a stall when returning too early)">;
460
461// On some processors, instructions that implicitly take two memory operands are
462// slow. In practice, this means that CALL, PUSH, and POP with memory operands
463// should be avoided in favor of a MOV + register CALL/PUSH/POP.
464def TuningSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
465                                     "SlowTwoMemOps", "true",
466                                     "Two memory operand instructions are slow">;
467
468// True if the LEA instruction inputs have to be ready at address generation
469// (AG) time.
470def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true",
471                                   "LEA instruction needs inputs at AG stage">;
472
473def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
474                                   "LEA instruction with certain arguments is slow">;
475
476// True if the LEA instruction has all three source operands: base, index,
477// and offset or if the LEA instruction uses base and index registers where
478// the base is EBP, RBP,or R13
479def TuningSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
480                                   "LEA instruction with 3 ops or certain registers is slow">;
481
482// True if INC and DEC instructions are slow when writing to flags
483def TuningSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
484                                   "INC and DEC instructions are slower than ADD and SUB">;
485
486def TuningPOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
487                                     "HasPOPCNTFalseDeps", "true",
488                                     "POPCNT has a false dependency on dest register">;
489
490def TuningLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
491                                     "HasLZCNTFalseDeps", "true",
492                                     "LZCNT/TZCNT have a false dependency on dest register">;
493
494def TuningMULCFalseDeps : SubtargetFeature<"false-deps-mulc",
495                               "HasMULCFalseDeps", "true",
496                               "VF[C]MULCPH/SH has a false dependency on dest register">;
497
498def TuningPERMFalseDeps : SubtargetFeature<"false-deps-perm",
499                               "HasPERMFalseDeps", "true",
500                               "VPERMD/Q/PS/PD has a false dependency on dest register">;
501
502def TuningRANGEFalseDeps : SubtargetFeature<"false-deps-range",
503                               "HasRANGEFalseDeps", "true",
504                               "VRANGEPD/PS/SD/SS has a false dependency on dest register">;
505
506def TuningGETMANTFalseDeps : SubtargetFeature<"false-deps-getmant",
507                               "HasGETMANTFalseDeps", "true",
508                               "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a"
509                               " false dependency on dest register">;
510
511def TuningMULLQFalseDeps : SubtargetFeature<"false-deps-mullq",
512                               "HasMULLQFalseDeps", "true",
513                               "VPMULLQ has a false dependency on dest register">;
514
515def TuningSBBDepBreaking : SubtargetFeature<"sbb-dep-breaking",
516                                     "HasSBBDepBreaking", "true",
517                                     "SBB with same register has no source dependency">;
518
519// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
520// using a variable mask over multiple fixed shuffles.
521def TuningFastVariableCrossLaneShuffle
522    : SubtargetFeature<"fast-variable-crosslane-shuffle",
523                       "HasFastVariableCrossLaneShuffle",
524                       "true", "Cross-lane shuffles with variable masks are fast">;
525def TuningFastVariablePerLaneShuffle
526    : SubtargetFeature<"fast-variable-perlane-shuffle",
527                       "HasFastVariablePerLaneShuffle",
528                       "true", "Per-lane shuffles with variable masks are fast">;
529
530// On some X86 processors, a vzeroupper instruction should be inserted after
531// using ymm/zmm registers before executing code that may use SSE instructions.
532def TuningInsertVZEROUPPER
533    : SubtargetFeature<"vzeroupper",
534                       "InsertVZEROUPPER",
535                       "true", "Should insert vzeroupper instructions">;
536
537// TuningFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
538// than the corresponding NR code. TuningFastVectorFSQRT should be enabled if
539// vector FSQRT has higher throughput than the corresponding NR code.
540// The idea is that throughput bound code is likely to be vectorized, so for
541// vectorized code we should care about the throughput of SQRT operations.
542// But if the code is scalar that probably means that the code has some kind of
543// dependency and we should care more about reducing the latency.
544
545// True if hardware SQRTSS instruction is at least as fast (latency) as
546// RSQRTSS followed by a Newton-Raphson iteration.
547def TuningFastScalarFSQRT
548    : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
549                       "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
550// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
551// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
552def TuningFastVectorFSQRT
553    : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
554                       "true", "Vector SQRT is fast (disable Newton-Raphson)">;
555
556// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
557// be used to replace test/set sequences.
558def TuningFastLZCNT
559    : SubtargetFeature<
560          "fast-lzcnt", "HasFastLZCNT", "true",
561          "LZCNT instructions are as fast as most simple integer ops">;
562
563// If the target can efficiently decode NOPs upto 7-bytes in length.
564def TuningFast7ByteNOP
565    : SubtargetFeature<
566          "fast-7bytenop", "HasFast7ByteNOP", "true",
567          "Target can quickly decode up to 7 byte NOPs">;
568
569// If the target can efficiently decode NOPs upto 11-bytes in length.
570def TuningFast11ByteNOP
571    : SubtargetFeature<
572          "fast-11bytenop", "HasFast11ByteNOP", "true",
573          "Target can quickly decode up to 11 byte NOPs">;
574
575// If the target can efficiently decode NOPs upto 15-bytes in length.
576def TuningFast15ByteNOP
577    : SubtargetFeature<
578          "fast-15bytenop", "HasFast15ByteNOP", "true",
579          "Target can quickly decode up to 15 byte NOPs">;
580
581// Sandy Bridge and newer processors can use SHLD with the same source on both
582// inputs to implement rotate to avoid the partial flag update of the normal
583// rotate instructions.
584def TuningFastSHLDRotate
585    : SubtargetFeature<
586          "fast-shld-rotate", "HasFastSHLDRotate", "true",
587          "SHLD can be used as a faster rotate">;
588
589// Bulldozer and newer processors can merge CMP/TEST (but not other
590// instructions) with conditional branches.
591def TuningBranchFusion
592    : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
593                 "CMP/TEST can be fused with conditional branches">;
594
595// Sandy Bridge and newer processors have many instructions that can be
596// fused with conditional branches and pass through the CPU as a single
597// operation.
598def TuningMacroFusion
599    : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
600                 "Various instructions can be fused with conditional branches">;
601
602// Gather is available since Haswell (AVX2 set). So technically, we can
603// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
604// Skylake Client processor has faster Gathers than HSW and performance is
605// similar to Skylake Server (AVX-512).
606def TuningFastGather
607    : SubtargetFeature<"fast-gather", "HasFastGather", "true",
608                       "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)">;
609
610def TuningPrefer128Bit
611    : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
612                       "Prefer 128-bit AVX instructions">;
613
614def TuningPrefer256Bit
615    : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
616                       "Prefer 256-bit AVX instructions">;
617
618def TuningAllowLight256Bit
619    : SubtargetFeature<"allow-light-256-bit", "AllowLight256Bit", "true",
620                       "Enable generation of 256-bit load/stores even if we prefer 128-bit">;
621
622def TuningPreferMaskRegisters
623    : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
624                       "Prefer AVX512 mask registers over PTEST/MOVMSK">;
625
626def TuningFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
627          "Indicates that the BEXTR instruction is implemented as a single uop "
628          "with good throughput">;
629
630// Combine vector math operations with shuffles into horizontal math
631// instructions if a CPU implements horizontal operations (introduced with
632// SSE3) with better latency/throughput than the alternative sequence.
633def TuningFastHorizontalOps
634    : SubtargetFeature<
635        "fast-hops", "HasFastHorizontalOps", "true",
636        "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
637        "normal vector instructions with shuffles">;
638
639def TuningFastScalarShiftMasks
640    : SubtargetFeature<
641        "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
642        "Prefer a left/right scalar logical shift pair over a shift+and pair">;
643
644def TuningFastVectorShiftMasks
645    : SubtargetFeature<
646        "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
647        "Prefer a left/right vector logical shift pair over a shift+and pair">;
648
649def TuningFastMOVBE
650    : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
651    "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
652
653def TuningUseSLMArithCosts
654    : SubtargetFeature<"use-slm-arith-costs", "UseSLMArithCosts", "true",
655        "Use Silvermont specific arithmetic costs">;
656
657def TuningUseGLMDivSqrtCosts
658    : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
659        "Use Goldmont specific floating point div/sqrt costs">;
660
661//===----------------------------------------------------------------------===//
662// X86 CPU Families
663// TODO: Remove these - use general tuning features to determine codegen.
664//===----------------------------------------------------------------------===//
665
666// Bonnell
667def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">;
668
669//===----------------------------------------------------------------------===//
670// Register File Description
671//===----------------------------------------------------------------------===//
672
673include "X86RegisterInfo.td"
674include "X86RegisterBanks.td"
675
676//===----------------------------------------------------------------------===//
677// Instruction Descriptions
678//===----------------------------------------------------------------------===//
679
680include "X86Schedule.td"
681include "X86InstrInfo.td"
682include "X86SchedPredicates.td"
683
684def X86InstrInfo : InstrInfo;
685
686//===----------------------------------------------------------------------===//
687// X86 Scheduler Models
688//===----------------------------------------------------------------------===//
689
690include "X86ScheduleAtom.td"
691include "X86SchedSandyBridge.td"
692include "X86SchedHaswell.td"
693include "X86SchedBroadwell.td"
694include "X86ScheduleSLM.td"
695include "X86ScheduleZnver1.td"
696include "X86ScheduleZnver2.td"
697include "X86ScheduleZnver3.td"
698include "X86ScheduleZnver4.td"
699include "X86ScheduleBdVer2.td"
700include "X86ScheduleBtVer2.td"
701include "X86SchedSkylakeClient.td"
702include "X86SchedSkylakeServer.td"
703include "X86SchedIceLake.td"
704include "X86SchedAlderlakeP.td"
705
706//===----------------------------------------------------------------------===//
707// X86 Processor Feature Lists
708//===----------------------------------------------------------------------===//
709
710def ProcessorFeatures {
711  // x86-64 and x86-64-v[234]
712  list<SubtargetFeature> X86_64V1Features = [
713    FeatureX87, FeatureCX8, FeatureCMOV, FeatureMMX, FeatureSSE2,
714    FeatureFXSR, FeatureNOPL, FeatureX86_64,
715  ];
716  list<SubtargetFeature> X86_64V2Features = !listconcat(X86_64V1Features, [
717    FeatureCX16, FeatureLAHFSAHF64, FeatureCRC32, FeaturePOPCNT,
718    FeatureSSE42
719  ]);
720  list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [
721    FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT,
722    FeatureMOVBE, FeatureXSAVE
723  ]);
724  list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [
725    FeatureBWI,
726    FeatureCDI,
727    FeatureDQI,
728    FeatureVLX,
729  ]);
730
731  // Nehalem
732  list<SubtargetFeature> NHMFeatures = X86_64V2Features;
733  list<SubtargetFeature> NHMTuning = [TuningMacroFusion,
734                                      TuningInsertVZEROUPPER];
735
736  // Westmere
737  list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
738  list<SubtargetFeature> WSMTuning = NHMTuning;
739  list<SubtargetFeature> WSMFeatures =
740    !listconcat(NHMFeatures, WSMAdditionalFeatures);
741
742  // Sandybridge
743  list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
744                                                  FeatureXSAVE,
745                                                  FeatureXSAVEOPT];
746  list<SubtargetFeature> SNBTuning = [TuningMacroFusion,
747                                      TuningSlow3OpsLEA,
748                                      TuningSlowDivide64,
749                                      TuningSlowUAMem32,
750                                      TuningFastScalarFSQRT,
751                                      TuningFastSHLDRotate,
752                                      TuningFast15ByteNOP,
753                                      TuningPOPCNTFalseDeps,
754                                      TuningInsertVZEROUPPER];
755  list<SubtargetFeature> SNBFeatures =
756    !listconcat(WSMFeatures, SNBAdditionalFeatures);
757
758  // Ivybridge
759  list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
760                                                  FeatureF16C,
761                                                  FeatureFSGSBase];
762  list<SubtargetFeature> IVBTuning = SNBTuning;
763  list<SubtargetFeature> IVBFeatures =
764    !listconcat(SNBFeatures, IVBAdditionalFeatures);
765
766  // Haswell
767  list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
768                                                  FeatureBMI,
769                                                  FeatureBMI2,
770                                                  FeatureERMSB,
771                                                  FeatureFMA,
772                                                  FeatureINVPCID,
773                                                  FeatureLZCNT,
774                                                  FeatureMOVBE];
775  list<SubtargetFeature> HSWTuning = [TuningMacroFusion,
776                                      TuningSlow3OpsLEA,
777                                      TuningSlowDivide64,
778                                      TuningFastScalarFSQRT,
779                                      TuningFastSHLDRotate,
780                                      TuningFast15ByteNOP,
781                                      TuningFastVariableCrossLaneShuffle,
782                                      TuningFastVariablePerLaneShuffle,
783                                      TuningPOPCNTFalseDeps,
784                                      TuningLZCNTFalseDeps,
785                                      TuningInsertVZEROUPPER,
786                                      TuningAllowLight256Bit];
787  list<SubtargetFeature> HSWFeatures =
788    !listconcat(IVBFeatures, HSWAdditionalFeatures);
789
790  // Broadwell
791  list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
792                                                  FeatureRDSEED,
793                                                  FeaturePRFCHW];
794  list<SubtargetFeature> BDWTuning = HSWTuning;
795  list<SubtargetFeature> BDWFeatures =
796    !listconcat(HSWFeatures, BDWAdditionalFeatures);
797
798  // Skylake
799  list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
800                                                  FeatureXSAVEC,
801                                                  FeatureXSAVES,
802                                                  FeatureCLFLUSHOPT];
803  list<SubtargetFeature> SKLTuning = [TuningFastGather,
804                                      TuningMacroFusion,
805                                      TuningSlow3OpsLEA,
806                                      TuningSlowDivide64,
807                                      TuningFastScalarFSQRT,
808                                      TuningFastVectorFSQRT,
809                                      TuningFastSHLDRotate,
810                                      TuningFast15ByteNOP,
811                                      TuningFastVariableCrossLaneShuffle,
812                                      TuningFastVariablePerLaneShuffle,
813                                      TuningPOPCNTFalseDeps,
814                                      TuningInsertVZEROUPPER,
815                                      TuningAllowLight256Bit];
816  list<SubtargetFeature> SKLFeatures =
817    !listconcat(BDWFeatures, SKLAdditionalFeatures);
818
819  // Skylake-AVX512
820  list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
821                                                  FeatureXSAVEC,
822                                                  FeatureXSAVES,
823                                                  FeatureCLFLUSHOPT,
824                                                  FeatureAVX512,
825                                                  FeatureCDI,
826                                                  FeatureDQI,
827                                                  FeatureBWI,
828                                                  FeatureVLX,
829                                                  FeaturePKU,
830                                                  FeatureCLWB];
831  list<SubtargetFeature> SKXTuning = [TuningFastGather,
832                                      TuningMacroFusion,
833                                      TuningSlow3OpsLEA,
834                                      TuningSlowDivide64,
835                                      TuningFastScalarFSQRT,
836                                      TuningFastVectorFSQRT,
837                                      TuningFastSHLDRotate,
838                                      TuningFast15ByteNOP,
839                                      TuningFastVariableCrossLaneShuffle,
840                                      TuningFastVariablePerLaneShuffle,
841                                      TuningPrefer256Bit,
842                                      TuningPOPCNTFalseDeps,
843                                      TuningInsertVZEROUPPER,
844                                      TuningAllowLight256Bit];
845  list<SubtargetFeature> SKXFeatures =
846    !listconcat(BDWFeatures, SKXAdditionalFeatures);
847
848  // Cascadelake
849  list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
850  list<SubtargetFeature> CLXTuning = SKXTuning;
851  list<SubtargetFeature> CLXFeatures =
852    !listconcat(SKXFeatures, CLXAdditionalFeatures);
853
854  // Cooperlake
855  list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
856  list<SubtargetFeature> CPXTuning = SKXTuning;
857  list<SubtargetFeature> CPXFeatures =
858    !listconcat(CLXFeatures, CPXAdditionalFeatures);
859
860  // Cannonlake
861  list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
862                                                  FeatureCDI,
863                                                  FeatureDQI,
864                                                  FeatureBWI,
865                                                  FeatureVLX,
866                                                  FeaturePKU,
867                                                  FeatureVBMI,
868                                                  FeatureIFMA,
869                                                  FeatureSHA];
870  list<SubtargetFeature> CNLTuning = [TuningFastGather,
871                                      TuningMacroFusion,
872                                      TuningSlow3OpsLEA,
873                                      TuningSlowDivide64,
874                                      TuningFastScalarFSQRT,
875                                      TuningFastVectorFSQRT,
876                                      TuningFastSHLDRotate,
877                                      TuningFast15ByteNOP,
878                                      TuningFastVariableCrossLaneShuffle,
879                                      TuningFastVariablePerLaneShuffle,
880                                      TuningPrefer256Bit,
881                                      TuningInsertVZEROUPPER,
882                                      TuningAllowLight256Bit];
883  list<SubtargetFeature> CNLFeatures =
884    !listconcat(SKLFeatures, CNLAdditionalFeatures);
885
886  // Icelake
887  list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
888                                                  FeatureVAES,
889                                                  FeatureVBMI2,
890                                                  FeatureVNNI,
891                                                  FeatureVPCLMULQDQ,
892                                                  FeatureVPOPCNTDQ,
893                                                  FeatureGFNI,
894                                                  FeatureRDPID,
895                                                  FeatureFSRM];
896  list<SubtargetFeature> ICLTuning = [TuningFastGather,
897                                      TuningMacroFusion,
898                                      TuningSlowDivide64,
899                                      TuningFastScalarFSQRT,
900                                      TuningFastVectorFSQRT,
901                                      TuningFastSHLDRotate,
902                                      TuningFast15ByteNOP,
903                                      TuningFastVariableCrossLaneShuffle,
904                                      TuningFastVariablePerLaneShuffle,
905                                      TuningPrefer256Bit,
906                                      TuningInsertVZEROUPPER,
907                                      TuningAllowLight256Bit];
908  list<SubtargetFeature> ICLFeatures =
909    !listconcat(CNLFeatures, ICLAdditionalFeatures);
910
911  // Icelake Server
912  list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,
913                                                  FeatureCLWB,
914                                                  FeatureWBNOINVD];
915  list<SubtargetFeature> ICXTuning = ICLTuning;
916  list<SubtargetFeature> ICXFeatures =
917    !listconcat(ICLFeatures, ICXAdditionalFeatures);
918
919  // Tigerlake
920  list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
921                                                  FeatureCLWB,
922                                                  FeatureMOVDIRI,
923                                                  FeatureMOVDIR64B,
924                                                  FeatureSHSTK];
925  list<SubtargetFeature> TGLTuning = ICLTuning;
926  list<SubtargetFeature> TGLFeatures =
927    !listconcat(ICLFeatures, TGLAdditionalFeatures );
928
929  // Sapphirerapids
930  list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
931                                                  FeatureAMXINT8,
932                                                  FeatureAMXBF16,
933                                                  FeatureBF16,
934                                                  FeatureSERIALIZE,
935                                                  FeatureCLDEMOTE,
936                                                  FeatureWAITPKG,
937                                                  FeaturePTWRITE,
938                                                  FeatureFP16,
939                                                  FeatureAVXVNNI,
940                                                  FeatureTSXLDTRK,
941                                                  FeatureENQCMD,
942                                                  FeatureSHSTK,
943                                                  FeatureMOVDIRI,
944                                                  FeatureMOVDIR64B,
945                                                  FeatureUINTR];
946  list<SubtargetFeature> SPRAdditionalTuning = [TuningMULCFalseDeps,
947                                                TuningPERMFalseDeps,
948                                                TuningRANGEFalseDeps,
949                                                TuningGETMANTFalseDeps,
950                                                TuningMULLQFalseDeps];
951  list<SubtargetFeature> SPRTuning = !listconcat(ICXTuning, SPRAdditionalTuning);
952  list<SubtargetFeature> SPRFeatures =
953    !listconcat(ICXFeatures, SPRAdditionalFeatures);
954
955  // Graniterapids
956  list<SubtargetFeature> GNRAdditionalFeatures = [FeatureAMXFP16,
957                                                  FeaturePREFETCHI];
958  list<SubtargetFeature> GNRFeatures =
959    !listconcat(SPRFeatures, GNRAdditionalFeatures);
960
961  // Atom
962  list<SubtargetFeature> AtomFeatures = [FeatureX87,
963                                         FeatureCX8,
964                                         FeatureCMOV,
965                                         FeatureMMX,
966                                         FeatureSSSE3,
967                                         FeatureFXSR,
968                                         FeatureNOPL,
969                                         FeatureX86_64,
970                                         FeatureCX16,
971                                         FeatureMOVBE,
972                                         FeatureLAHFSAHF64];
973  list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
974                                       TuningSlowUAMem16,
975                                       TuningLEAForSP,
976                                       TuningSlowDivide32,
977                                       TuningSlowDivide64,
978                                       TuningSlowTwoMemOps,
979                                       TuningLEAUsesAG,
980                                       TuningPadShortFunctions,
981                                       TuningInsertVZEROUPPER];
982
983  // Silvermont
984  list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
985                                                  FeatureCRC32,
986                                                  FeaturePOPCNT,
987                                                  FeaturePCLMUL,
988                                                  FeaturePRFCHW,
989                                                  FeatureRDRAND];
990  list<SubtargetFeature> SLMTuning = [TuningUseSLMArithCosts,
991                                      TuningSlowTwoMemOps,
992                                      TuningSlowLEA,
993                                      TuningSlowIncDec,
994                                      TuningSlowDivide64,
995                                      TuningSlowPMULLD,
996                                      TuningFast7ByteNOP,
997                                      TuningFastMOVBE,
998                                      TuningPOPCNTFalseDeps,
999                                      TuningInsertVZEROUPPER];
1000  list<SubtargetFeature> SLMFeatures =
1001    !listconcat(AtomFeatures, SLMAdditionalFeatures);
1002
1003  // Goldmont
1004  list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
1005                                                  FeatureSHA,
1006                                                  FeatureRDSEED,
1007                                                  FeatureXSAVE,
1008                                                  FeatureXSAVEOPT,
1009                                                  FeatureXSAVEC,
1010                                                  FeatureXSAVES,
1011                                                  FeatureCLFLUSHOPT,
1012                                                  FeatureFSGSBase];
1013  list<SubtargetFeature> GLMTuning = [TuningUseGLMDivSqrtCosts,
1014                                      TuningSlowTwoMemOps,
1015                                      TuningSlowLEA,
1016                                      TuningSlowIncDec,
1017                                      TuningFastMOVBE,
1018                                      TuningPOPCNTFalseDeps,
1019                                      TuningInsertVZEROUPPER];
1020  list<SubtargetFeature> GLMFeatures =
1021    !listconcat(SLMFeatures, GLMAdditionalFeatures);
1022
1023  // Goldmont Plus
1024  list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
1025                                                  FeatureRDPID];
1026  list<SubtargetFeature> GLPTuning = [TuningUseGLMDivSqrtCosts,
1027                                      TuningSlowTwoMemOps,
1028                                      TuningSlowLEA,
1029                                      TuningSlowIncDec,
1030                                      TuningFastMOVBE,
1031                                      TuningInsertVZEROUPPER];
1032  list<SubtargetFeature> GLPFeatures =
1033    !listconcat(GLMFeatures, GLPAdditionalFeatures);
1034
1035  // Tremont
1036  list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
1037                                                  FeatureGFNI];
1038  list<SubtargetFeature> TRMTuning = GLPTuning;
1039  list<SubtargetFeature> TRMFeatures =
1040    !listconcat(GLPFeatures, TRMAdditionalFeatures);
1041
1042  // Alderlake
1043  list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,
1044                                                  FeaturePCONFIG,
1045                                                  FeatureSHSTK,
1046                                                  FeatureWIDEKL,
1047                                                  FeatureINVPCID,
1048                                                  FeatureADX,
1049                                                  FeatureFMA,
1050                                                  FeatureVAES,
1051                                                  FeatureVPCLMULQDQ,
1052                                                  FeatureF16C,
1053                                                  FeatureBMI,
1054                                                  FeatureBMI2,
1055                                                  FeatureLZCNT,
1056                                                  FeatureAVXVNNI,
1057                                                  FeaturePKU,
1058                                                  FeatureHRESET,
1059                                                  FeatureCLDEMOTE,
1060                                                  FeatureMOVDIRI,
1061                                                  FeatureMOVDIR64B,
1062                                                  FeatureWAITPKG];
1063  list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps];
1064  list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
1065  list<SubtargetFeature> ADLFeatures =
1066    !listconcat(TRMFeatures, ADLAdditionalFeatures);
1067
1068  // Sierraforest
1069  list<SubtargetFeature> SRFAdditionalFeatures = [FeatureCMPCCXADD,
1070                                                  FeatureAVXIFMA,
1071                                                  FeatureAVXNECONVERT,
1072                                                  FeatureAVXVNNIINT8];
1073  list<SubtargetFeature> SRFFeatures =
1074    !listconcat(ADLFeatures, SRFAdditionalFeatures);
1075
1076  // Grandridge
1077  list<SubtargetFeature> GRRAdditionalFeatures = [FeatureRAOINT];
1078  list<SubtargetFeature> GRRFeatures =
1079    !listconcat(SRFFeatures, GRRAdditionalFeatures);
1080
1081  // Knights Landing
1082  list<SubtargetFeature> KNLFeatures = [FeatureX87,
1083                                        FeatureCX8,
1084                                        FeatureCMOV,
1085                                        FeatureMMX,
1086                                        FeatureFXSR,
1087                                        FeatureNOPL,
1088                                        FeatureX86_64,
1089                                        FeatureCX16,
1090                                        FeatureCRC32,
1091                                        FeaturePOPCNT,
1092                                        FeaturePCLMUL,
1093                                        FeatureXSAVE,
1094                                        FeatureXSAVEOPT,
1095                                        FeatureLAHFSAHF64,
1096                                        FeatureAES,
1097                                        FeatureRDRAND,
1098                                        FeatureF16C,
1099                                        FeatureFSGSBase,
1100                                        FeatureAVX512,
1101                                        FeatureERI,
1102                                        FeatureCDI,
1103                                        FeaturePFI,
1104                                        FeaturePREFETCHWT1,
1105                                        FeatureADX,
1106                                        FeatureRDSEED,
1107                                        FeatureMOVBE,
1108                                        FeatureLZCNT,
1109                                        FeatureBMI,
1110                                        FeatureBMI2,
1111                                        FeatureFMA,
1112                                        FeaturePRFCHW];
1113  list<SubtargetFeature> KNLTuning = [TuningSlowDivide64,
1114                                      TuningSlow3OpsLEA,
1115                                      TuningSlowIncDec,
1116                                      TuningSlowTwoMemOps,
1117                                      TuningPreferMaskRegisters,
1118                                      TuningFastGather,
1119                                      TuningFastMOVBE,
1120                                      TuningSlowPMADDWD];
1121  // TODO Add AVX5124FMAPS/AVX5124VNNIW features
1122  list<SubtargetFeature> KNMFeatures =
1123    !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
1124
1125  // Barcelona
1126  list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
1127                                              FeatureCX8,
1128                                              FeatureSSE4A,
1129                                              Feature3DNowA,
1130                                              FeatureFXSR,
1131                                              FeatureNOPL,
1132                                              FeatureCX16,
1133                                              FeaturePRFCHW,
1134                                              FeatureLZCNT,
1135                                              FeaturePOPCNT,
1136                                              FeatureLAHFSAHF64,
1137                                              FeatureCMOV,
1138                                              FeatureX86_64];
1139  list<SubtargetFeature> BarcelonaTuning = [TuningFastScalarShiftMasks,
1140                                            TuningSlowSHLD,
1141                                            TuningSBBDepBreaking,
1142                                            TuningInsertVZEROUPPER];
1143
1144  // Bobcat
1145  list<SubtargetFeature> BtVer1Features = [FeatureX87,
1146                                           FeatureCX8,
1147                                           FeatureCMOV,
1148                                           FeatureMMX,
1149                                           FeatureSSSE3,
1150                                           FeatureSSE4A,
1151                                           FeatureFXSR,
1152                                           FeatureNOPL,
1153                                           FeatureX86_64,
1154                                           FeatureCX16,
1155                                           FeaturePRFCHW,
1156                                           FeatureLZCNT,
1157                                           FeaturePOPCNT,
1158                                           FeatureLAHFSAHF64];
1159  list<SubtargetFeature> BtVer1Tuning = [TuningFast15ByteNOP,
1160                                         TuningFastScalarShiftMasks,
1161                                         TuningFastVectorShiftMasks,
1162                                         TuningSlowSHLD,
1163                                         TuningSBBDepBreaking,
1164                                         TuningInsertVZEROUPPER];
1165
1166  // Jaguar
1167  list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
1168                                                     FeatureAES,
1169                                                     FeatureCRC32,
1170                                                     FeaturePCLMUL,
1171                                                     FeatureBMI,
1172                                                     FeatureF16C,
1173                                                     FeatureMOVBE,
1174                                                     FeatureXSAVE,
1175                                                     FeatureXSAVEOPT];
1176  list<SubtargetFeature> BtVer2Tuning = [TuningFastLZCNT,
1177                                         TuningFastBEXTR,
1178                                         TuningFastHorizontalOps,
1179                                         TuningFast15ByteNOP,
1180                                         TuningFastScalarShiftMasks,
1181                                         TuningFastVectorShiftMasks,
1182                                         TuningFastMOVBE,
1183                                         TuningSBBDepBreaking,
1184                                         TuningSlowSHLD];
1185  list<SubtargetFeature> BtVer2Features =
1186    !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
1187
1188  // Bulldozer
1189  list<SubtargetFeature> BdVer1Features = [FeatureX87,
1190                                           FeatureCX8,
1191                                           FeatureCMOV,
1192                                           FeatureXOP,
1193                                           FeatureX86_64,
1194                                           FeatureCX16,
1195                                           FeatureAES,
1196                                           FeatureCRC32,
1197                                           FeaturePRFCHW,
1198                                           FeaturePCLMUL,
1199                                           FeatureMMX,
1200                                           FeatureFXSR,
1201                                           FeatureNOPL,
1202                                           FeatureLZCNT,
1203                                           FeaturePOPCNT,
1204                                           FeatureXSAVE,
1205                                           FeatureLWP,
1206                                           FeatureLAHFSAHF64];
1207  list<SubtargetFeature> BdVer1Tuning = [TuningSlowSHLD,
1208                                         TuningFast11ByteNOP,
1209                                         TuningFastScalarShiftMasks,
1210                                         TuningBranchFusion,
1211                                         TuningSBBDepBreaking,
1212                                         TuningInsertVZEROUPPER];
1213
1214  // PileDriver
1215  list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
1216                                                     FeatureBMI,
1217                                                     FeatureTBM,
1218                                                     FeatureFMA];
1219  list<SubtargetFeature> BdVer2AdditionalTuning = [TuningFastBEXTR,
1220                                                   TuningFastMOVBE];
1221  list<SubtargetFeature> BdVer2Tuning =
1222    !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
1223  list<SubtargetFeature> BdVer2Features =
1224    !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
1225
1226  // Steamroller
1227  list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
1228                                                     FeatureFSGSBase];
1229  list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;
1230  list<SubtargetFeature> BdVer3Features =
1231    !listconcat(BdVer2Features, BdVer3AdditionalFeatures);
1232
1233  // Excavator
1234  list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
1235                                                     FeatureBMI2,
1236                                                     FeatureMOVBE,
1237                                                     FeatureRDRAND,
1238                                                     FeatureMWAITX];
1239  list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;
1240  list<SubtargetFeature> BdVer4Features =
1241    !listconcat(BdVer3Features, BdVer4AdditionalFeatures);
1242
1243
1244  // AMD Zen Processors common ISAs
1245  list<SubtargetFeature> ZNFeatures = [FeatureADX,
1246                                       FeatureAES,
1247                                       FeatureAVX2,
1248                                       FeatureBMI,
1249                                       FeatureBMI2,
1250                                       FeatureCLFLUSHOPT,
1251                                       FeatureCLZERO,
1252                                       FeatureCMOV,
1253                                       FeatureX86_64,
1254                                       FeatureCX16,
1255                                       FeatureCRC32,
1256                                       FeatureF16C,
1257                                       FeatureFMA,
1258                                       FeatureFSGSBase,
1259                                       FeatureFXSR,
1260                                       FeatureNOPL,
1261                                       FeatureLAHFSAHF64,
1262                                       FeatureLZCNT,
1263                                       FeatureMMX,
1264                                       FeatureMOVBE,
1265                                       FeatureMWAITX,
1266                                       FeaturePCLMUL,
1267                                       FeaturePOPCNT,
1268                                       FeaturePRFCHW,
1269                                       FeatureRDRAND,
1270                                       FeatureRDSEED,
1271                                       FeatureSHA,
1272                                       FeatureSSE4A,
1273                                       FeatureX87,
1274                                       FeatureXSAVE,
1275                                       FeatureXSAVEC,
1276                                       FeatureXSAVEOPT,
1277                                       FeatureXSAVES];
1278  list<SubtargetFeature> ZNTuning = [TuningFastLZCNT,
1279                                     TuningFastBEXTR,
1280                                     TuningFast15ByteNOP,
1281                                     TuningBranchFusion,
1282                                     TuningFastScalarFSQRT,
1283                                     TuningFastVectorFSQRT,
1284                                     TuningFastScalarShiftMasks,
1285                                     TuningFastVariablePerLaneShuffle,
1286                                     TuningFastMOVBE,
1287                                     TuningSlowSHLD,
1288                                     TuningSBBDepBreaking,
1289                                     TuningInsertVZEROUPPER,
1290                                     TuningAllowLight256Bit];
1291  list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
1292                                                  FeatureRDPID,
1293                                                  FeatureRDPRU,
1294                                                  FeatureWBNOINVD];
1295  list<SubtargetFeature> ZN2Tuning = ZNTuning;
1296  list<SubtargetFeature> ZN2Features =
1297    !listconcat(ZNFeatures, ZN2AdditionalFeatures);
1298  list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
1299                                                  FeatureINVPCID,
1300                                                  FeaturePKU,
1301                                                  FeatureVAES,
1302                                                  FeatureVPCLMULQDQ];
1303  list<SubtargetFeature> ZN3AdditionalTuning = [TuningMacroFusion];
1304  list<SubtargetFeature> ZN3Tuning =
1305    !listconcat(ZN2Tuning, ZN3AdditionalTuning);
1306  list<SubtargetFeature> ZN3Features =
1307    !listconcat(ZN2Features, ZN3AdditionalFeatures);
1308  list<SubtargetFeature> ZN4Tuning = ZN3Tuning;
1309  list<SubtargetFeature> ZN4AdditionalFeatures = [FeatureAVX512,
1310                                                  FeatureCDI,
1311                                                  FeatureDQI,
1312                                                  FeatureBWI,
1313                                                  FeatureVLX,
1314                                                  FeatureVBMI,
1315                                                  FeatureVBMI2,
1316                                                  FeatureIFMA,
1317                                                  FeatureVNNI,
1318                                                  FeatureBITALG,
1319                                                  FeatureGFNI,
1320                                                  FeatureBF16,
1321                                                  FeatureSHSTK,
1322                                                  FeatureVPOPCNTDQ];
1323  list<SubtargetFeature> ZN4Features =
1324    !listconcat(ZN3Features, ZN4AdditionalFeatures);
1325}
1326
1327//===----------------------------------------------------------------------===//
1328// X86 processors supported.
1329//===----------------------------------------------------------------------===//
1330
1331class Proc<string Name, list<SubtargetFeature> Features,
1332           list<SubtargetFeature> TuneFeatures>
1333 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>;
1334
1335class ProcModel<string Name, SchedMachineModel Model,
1336                list<SubtargetFeature> Features,
1337                list<SubtargetFeature> TuneFeatures>
1338 : ProcessorModel<Name, Model, Features, TuneFeatures>;
1339
1340// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
1341// if i386/i486 is specifically requested.
1342// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
1343// constructor checks that any CPU used in 64-bit mode has FeatureX86_64
1344// enabled. It has no effect on code generation.
1345// NOTE: As a default tuning, "generic" aims to produce code optimized for the
1346// most common X86 processors. The tunings might be changed over time. It is
1347// recommended to use "tune-cpu"="x86-64" in function attribute for consistency.
1348def : ProcModel<"generic", SandyBridgeModel,
1349                [FeatureX87, FeatureCX8, FeatureX86_64],
1350                [TuningSlow3OpsLEA,
1351                 TuningSlowDivide64,
1352                 TuningMacroFusion,
1353                 TuningFastScalarFSQRT,
1354                 TuningFast15ByteNOP,
1355                 TuningInsertVZEROUPPER]>;
1356
1357def : Proc<"i386",            [FeatureX87],
1358                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1359def : Proc<"i486",            [FeatureX87],
1360                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1361def : Proc<"i586",            [FeatureX87, FeatureCX8],
1362                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1363def : Proc<"pentium",         [FeatureX87, FeatureCX8],
1364                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1365def : Proc<"pentium-mmx",     [FeatureX87, FeatureCX8, FeatureMMX],
1366                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1367
1368def : Proc<"i686", [FeatureX87, FeatureCX8, FeatureCMOV],
1369                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1370def : Proc<"pentiumpro", [FeatureX87, FeatureCX8, FeatureCMOV,
1371                          FeatureNOPL],
1372                         [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1373
1374def : Proc<"pentium2", [FeatureX87, FeatureCX8, FeatureMMX, FeatureCMOV,
1375                        FeatureFXSR, FeatureNOPL],
1376                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1377
1378foreach P = ["pentium3", "pentium3m"] in {
1379  def : Proc<P, [FeatureX87, FeatureCX8, FeatureMMX,
1380                 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
1381                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1382}
1383
1384// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
1385// The intent is to enable it for pentium4 which is the current default
1386// processor in a vanilla 32-bit clang compilation when no specific
1387// architecture is specified.  This generally gives a nice performance
1388// increase on silvermont, with largely neutral behavior on other
1389// contemporary large core processors.
1390// pentium-m, pentium4m, prescott and nocona are included as a preventative
1391// measure to avoid performance surprises, in case clang's default cpu
1392// changes slightly.
1393
1394def : ProcModel<"pentium-m", GenericPostRAModel,
1395                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1396                FeatureFXSR, FeatureNOPL, FeatureCMOV],
1397                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1398
1399foreach P = ["pentium4", "pentium4m"] in {
1400  def : ProcModel<P, GenericPostRAModel,
1401                  [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE2,
1402                   FeatureFXSR, FeatureNOPL, FeatureCMOV],
1403                  [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1404}
1405
1406// Intel Quark.
1407def : Proc<"lakemont", [FeatureCX8],
1408                       [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1409
1410// Intel Core Duo.
1411def : ProcModel<"yonah", SandyBridgeModel,
1412                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1413                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1414                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1415
1416// NetBurst.
1417def : ProcModel<"prescott", GenericPostRAModel,
1418                [FeatureX87, FeatureCX8, FeatureMMX, FeatureSSE3,
1419                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1420                [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1421def : ProcModel<"nocona", GenericPostRAModel, [
1422  FeatureX87,
1423  FeatureCX8,
1424  FeatureCMOV,
1425  FeatureMMX,
1426  FeatureSSE3,
1427  FeatureFXSR,
1428  FeatureNOPL,
1429  FeatureX86_64,
1430  FeatureCX16,
1431],
1432[
1433  TuningSlowUAMem16,
1434  TuningInsertVZEROUPPER
1435]>;
1436
1437// Intel Core 2 Solo/Duo.
1438def : ProcModel<"core2", SandyBridgeModel, [
1439  FeatureX87,
1440  FeatureCX8,
1441  FeatureCMOV,
1442  FeatureMMX,
1443  FeatureSSSE3,
1444  FeatureFXSR,
1445  FeatureNOPL,
1446  FeatureX86_64,
1447  FeatureCX16,
1448  FeatureLAHFSAHF64
1449],
1450[
1451  TuningMacroFusion,
1452  TuningSlowUAMem16,
1453  TuningInsertVZEROUPPER
1454]>;
1455def : ProcModel<"penryn", SandyBridgeModel, [
1456  FeatureX87,
1457  FeatureCX8,
1458  FeatureCMOV,
1459  FeatureMMX,
1460  FeatureSSE41,
1461  FeatureFXSR,
1462  FeatureNOPL,
1463  FeatureX86_64,
1464  FeatureCX16,
1465  FeatureLAHFSAHF64
1466],
1467[
1468  TuningMacroFusion,
1469  TuningSlowUAMem16,
1470  TuningInsertVZEROUPPER
1471]>;
1472
1473// Atom CPUs.
1474foreach P = ["bonnell", "atom"] in {
1475  def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
1476                  ProcessorFeatures.AtomTuning>;
1477}
1478
1479foreach P = ["silvermont", "slm"] in {
1480  def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
1481                  ProcessorFeatures.SLMTuning>;
1482}
1483
1484def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
1485                ProcessorFeatures.GLMTuning>;
1486def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
1487                ProcessorFeatures.GLPTuning>;
1488def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
1489                ProcessorFeatures.TRMTuning>;
1490def : ProcModel<"sierraforest", AlderlakePModel, ProcessorFeatures.SRFFeatures,
1491                ProcessorFeatures.TRMTuning>;
1492def : ProcModel<"grandridge", AlderlakePModel, ProcessorFeatures.GRRFeatures,
1493                ProcessorFeatures.TRMTuning>;
1494
1495// "Arrandale" along with corei3 and corei5
1496foreach P = ["nehalem", "corei7"] in {
1497  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
1498                  ProcessorFeatures.NHMTuning>;
1499}
1500
1501// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1502def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
1503                ProcessorFeatures.WSMTuning>;
1504
1505foreach P = ["sandybridge", "corei7-avx"] in {
1506  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
1507                  ProcessorFeatures.SNBTuning>;
1508}
1509
1510foreach P = ["ivybridge", "core-avx-i"] in {
1511  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
1512                  ProcessorFeatures.IVBTuning>;
1513}
1514
1515foreach P = ["haswell", "core-avx2"] in {
1516  def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
1517                  ProcessorFeatures.HSWTuning>;
1518}
1519
1520def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
1521                ProcessorFeatures.BDWTuning>;
1522
1523def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
1524                ProcessorFeatures.SKLTuning>;
1525
1526// FIXME: define KNL scheduler model
1527def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
1528                ProcessorFeatures.KNLTuning>;
1529def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
1530                ProcessorFeatures.KNLTuning>;
1531
1532foreach P = ["skylake-avx512", "skx"] in {
1533  def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
1534                  ProcessorFeatures.SKXTuning>;
1535}
1536
1537def : ProcModel<"cascadelake", SkylakeServerModel,
1538                ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
1539def : ProcModel<"cooperlake", SkylakeServerModel,
1540                ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
1541def : ProcModel<"cannonlake", SkylakeServerModel,
1542                ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
1543def : ProcModel<"icelake-client", IceLakeModel,
1544                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1545def : ProcModel<"rocketlake", IceLakeModel,
1546                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1547def : ProcModel<"icelake-server", IceLakeModel,
1548                ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
1549def : ProcModel<"tigerlake", IceLakeModel,
1550                ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
1551def : ProcModel<"sapphirerapids", SkylakeServerModel,
1552                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1553def : ProcModel<"alderlake", AlderlakePModel,
1554                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1555def : ProcModel<"raptorlake", AlderlakePModel,
1556                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1557def : ProcModel<"meteorlake", AlderlakePModel,
1558                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1559def : ProcModel<"graniterapids", SkylakeServerModel,
1560                ProcessorFeatures.GNRFeatures, ProcessorFeatures.SPRTuning>;
1561def : ProcModel<"emeraldrapids", SkylakeServerModel,
1562                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1563
1564// AMD CPUs.
1565
1566def : Proc<"k6",   [FeatureX87, FeatureCX8, FeatureMMX],
1567                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1568def : Proc<"k6-2", [FeatureX87, FeatureCX8, Feature3DNow],
1569                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1570def : Proc<"k6-3", [FeatureX87, FeatureCX8, Feature3DNow],
1571                   [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1572
1573foreach P = ["athlon", "athlon-tbird"] in {
1574  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV, Feature3DNowA,
1575                 FeatureNOPL],
1576                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1577}
1578
1579foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1580  def : Proc<P, [FeatureX87, FeatureCX8, FeatureCMOV,
1581                 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
1582                [TuningSlowSHLD, TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1583}
1584
1585foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1586  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE2, Feature3DNowA,
1587                 FeatureFXSR, FeatureNOPL, FeatureX86_64, FeatureCMOV],
1588                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1589                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1590}
1591
1592foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1593  def : Proc<P, [FeatureX87, FeatureCX8, FeatureSSE3, Feature3DNowA,
1594                 FeatureFXSR, FeatureNOPL, FeatureCX16, FeatureCMOV,
1595                 FeatureX86_64],
1596                [TuningFastScalarShiftMasks, TuningSlowSHLD, TuningSlowUAMem16,
1597                 TuningSBBDepBreaking, TuningInsertVZEROUPPER]>;
1598}
1599
1600foreach P = ["amdfam10", "barcelona"] in {
1601  def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
1602             ProcessorFeatures.BarcelonaTuning>;
1603}
1604
1605// Bobcat
1606def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
1607           ProcessorFeatures.BtVer1Tuning>;
1608// Jaguar
1609def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,
1610                ProcessorFeatures.BtVer2Tuning>;
1611
1612// Bulldozer
1613def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,
1614                ProcessorFeatures.BdVer1Tuning>;
1615// Piledriver
1616def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,
1617                ProcessorFeatures.BdVer2Tuning>;
1618// Steamroller
1619def : Proc<"bdver3", ProcessorFeatures.BdVer3Features,
1620           ProcessorFeatures.BdVer3Tuning>;
1621// Excavator
1622def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
1623           ProcessorFeatures.BdVer4Tuning>;
1624
1625def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
1626                ProcessorFeatures.ZNTuning>;
1627def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
1628                ProcessorFeatures.ZN2Tuning>;
1629def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
1630                ProcessorFeatures.ZN3Tuning>;
1631def : ProcModel<"znver4", Znver4Model, ProcessorFeatures.ZN4Features,
1632           ProcessorFeatures.ZN4Tuning>;
1633
1634def : Proc<"geode",           [FeatureX87, FeatureCX8, Feature3DNowA],
1635                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1636
1637def : Proc<"winchip-c6",      [FeatureX87, FeatureMMX],
1638                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1639def : Proc<"winchip2",        [FeatureX87, Feature3DNow],
1640                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1641def : Proc<"c3",              [FeatureX87, Feature3DNow],
1642                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1643def : Proc<"c3-2",            [FeatureX87, FeatureCX8, FeatureMMX,
1644                               FeatureSSE1, FeatureFXSR, FeatureCMOV],
1645                              [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
1646
1647// We also provide a generic 64-bit specific x86 processor model which tries to
1648// be good for modern chips without enabling instruction set encodings past the
1649// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1650// modern 64-bit x86 chip, and enables features that are generally beneficial.
1651//
1652// We currently use the Sandy Bridge model as the default scheduling model as
1653// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1654// covers a huge swath of x86 processors. If there are specific scheduling
1655// knobs which need to be tuned differently for AMD chips, we might consider
1656// forming a common base for them.
1657def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
1658[
1659  TuningSlow3OpsLEA,
1660  TuningSlowDivide64,
1661  TuningSlowIncDec,
1662  TuningMacroFusion,
1663  TuningInsertVZEROUPPER
1664]>;
1665
1666// x86-64 micro-architecture levels.
1667def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
1668                ProcessorFeatures.SNBTuning>;
1669// Close to Haswell.
1670def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
1671                ProcessorFeatures.HSWTuning>;
1672// Close to the AVX-512 level implemented by Xeon Scalable Processors.
1673def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,
1674                ProcessorFeatures.SKXTuning>;
1675
1676//===----------------------------------------------------------------------===//
1677// Calling Conventions
1678//===----------------------------------------------------------------------===//
1679
1680include "X86CallingConv.td"
1681
1682
1683//===----------------------------------------------------------------------===//
1684// Assembly Parser
1685//===----------------------------------------------------------------------===//
1686
1687def ATTAsmParserVariant : AsmParserVariant {
1688  int Variant = 0;
1689
1690  // Variant name.
1691  string Name = "att";
1692
1693  // Discard comments in assembly strings.
1694  string CommentDelimiter = "#";
1695
1696  // Recognize hard coded registers.
1697  string RegisterPrefix = "%";
1698}
1699
1700def IntelAsmParserVariant : AsmParserVariant {
1701  int Variant = 1;
1702
1703  // Variant name.
1704  string Name = "intel";
1705
1706  // Discard comments in assembly strings.
1707  string CommentDelimiter = ";";
1708
1709  // Recognize hard coded registers.
1710  string RegisterPrefix = "";
1711}
1712
1713//===----------------------------------------------------------------------===//
1714// Assembly Printers
1715//===----------------------------------------------------------------------===//
1716
1717// The X86 target supports two different syntaxes for emitting machine code.
1718// This is controlled by the -x86-asm-syntax={att|intel}
1719def ATTAsmWriter : AsmWriter {
1720  string AsmWriterClassName  = "ATTInstPrinter";
1721  int Variant = 0;
1722}
1723def IntelAsmWriter : AsmWriter {
1724  string AsmWriterClassName  = "IntelInstPrinter";
1725  int Variant = 1;
1726}
1727
1728def X86 : Target {
1729  // Information about the instructions...
1730  let InstructionSet = X86InstrInfo;
1731  let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1732  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1733  let AllowRegisterRenaming = 1;
1734}
1735
1736//===----------------------------------------------------------------------===//
1737// Pfm Counters
1738//===----------------------------------------------------------------------===//
1739
1740include "X86PfmCounters.td"
1741