xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86.td (revision 8881d206f4e68b564c2c5f50fc717086fc3e827a) 
1//===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This is a target description file for the Intel i386 architecture, referred
10// to here as the "X86" architecture.
11//
12//===----------------------------------------------------------------------===//
13
14// Get the target-independent interfaces which we are implementing...
15//
16include "llvm/Target/Target.td"
17
18//===----------------------------------------------------------------------===//
19// X86 Subtarget state
20//
21
22def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
23                                  "64-bit mode (x86_64)">;
24def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
25                                  "32-bit mode (80386)">;
26def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
27                                  "16-bit mode (i8086)">;
28
29//===----------------------------------------------------------------------===//
30// X86 Subtarget features
31//===----------------------------------------------------------------------===//
32
33def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
34                                      "Enable X87 float instructions">;
35
36def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
37                                      "Enable NOPL instruction">;
38
39def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
40                                      "Enable conditional move instructions">;
41
42def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true",
43                                        "Support CMPXCHG8B instructions">;
44
45def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
46                                       "Support POPCNT instruction">;
47
48def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
49                                      "Support fxsave/fxrestore instructions">;
50
51def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
52                                       "Support xsave instructions">;
53
54def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
55                                       "Support xsaveopt instructions",
56                                       [FeatureXSAVE]>;
57
58def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
59                                       "Support xsavec instructions",
60                                       [FeatureXSAVE]>;
61
62def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
63                                       "Support xsaves instructions",
64                                       [FeatureXSAVE]>;
65
66def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
67                                      "Enable SSE instructions">;
68def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
69                                      "Enable SSE2 instructions",
70                                      [FeatureSSE1]>;
71def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
72                                      "Enable SSE3 instructions",
73                                      [FeatureSSE2]>;
74def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
75                                      "Enable SSSE3 instructions",
76                                      [FeatureSSE3]>;
77def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
78                                      "Enable SSE 4.1 instructions",
79                                      [FeatureSSSE3]>;
80def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
81                                      "Enable SSE 4.2 instructions",
82                                      [FeatureSSE41]>;
83// The MMX subtarget feature is separate from the rest of the SSE features
84// because it's important (for odd compatibility reasons) to be able to
85// turn it off explicitly while allowing SSE+ to be on.
86def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
87                                      "Enable MMX instructions">;
88def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
89                                      "Enable 3DNow! instructions",
90                                      [FeatureMMX]>;
91def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
92                                      "Enable 3DNow! Athlon instructions",
93                                      [Feature3DNow]>;
94// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
95// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
96// without disabling 64-bit mode. Nothing should imply this feature bit. It
97// is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
98def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
99                                      "Support 64-bit instructions">;
100def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
101                                      "64-bit with cmpxchg16b",
102                                      [FeatureCMPXCHG8B]>;
103def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
104                                       "SHLD instruction is slow">;
105def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
106                                        "PMULLD instruction is slow">;
107def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
108                                          "true",
109                                          "PMADDWD is slower than PMULLD">;
110// FIXME: This should not apply to CPUs that do not have SSE.
111def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
112                                "IsUAMem16Slow", "true",
113                                "Slow unaligned 16-byte memory access">;
114def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
115                                "IsUAMem32Slow", "true",
116                                "Slow unaligned 32-byte memory access">;
117def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
118                                      "Support SSE 4a instructions",
119                                      [FeatureSSE3]>;
120
121def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
122                                      "Enable AVX instructions",
123                                      [FeatureSSE42]>;
124def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
125                                      "Enable AVX2 instructions",
126                                      [FeatureAVX]>;
127def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
128                                      "Enable three-operand fused multiple-add",
129                                      [FeatureAVX]>;
130def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
131                       "Support 16-bit floating point conversion instructions",
132                       [FeatureAVX]>;
133def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
134                                      "Enable AVX-512 instructions",
135                                      [FeatureAVX2, FeatureFMA, FeatureF16C]>;
136def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
137                      "Enable AVX-512 Exponential and Reciprocal Instructions",
138                                      [FeatureAVX512]>;
139def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
140                      "Enable AVX-512 Conflict Detection Instructions",
141                                      [FeatureAVX512]>;
142def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
143                       "true", "Enable AVX-512 Population Count Instructions",
144                                      [FeatureAVX512]>;
145def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
146                      "Enable AVX-512 PreFetch Instructions",
147                                      [FeatureAVX512]>;
148def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
149                                   "true",
150                                   "Prefetch with Intent to Write and T1 Hint">;
151def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
152                      "Enable AVX-512 Doubleword and Quadword Instructions",
153                                      [FeatureAVX512]>;
154def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
155                      "Enable AVX-512 Byte and Word Instructions",
156                                      [FeatureAVX512]>;
157def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
158                      "Enable AVX-512 Vector Length eXtensions",
159                                      [FeatureAVX512]>;
160def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
161                      "Enable AVX-512 Vector Byte Manipulation Instructions",
162                                      [FeatureBWI]>;
163def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
164                      "Enable AVX-512 further Vector Byte Manipulation Instructions",
165                                      [FeatureBWI]>;
166def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
167                      "Enable AVX-512 Integer Fused Multiple-Add",
168                                      [FeatureAVX512]>;
169def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
170                      "Enable protection keys">;
171def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
172                          "Enable AVX-512 Vector Neural Network Instructions",
173                                      [FeatureAVX512]>;
174def FeatureAVXVNNI    : SubtargetFeature<"avxvnni", "HasAVXVNNI", "true",
175                           "Support AVX_VNNI encoding",
176                                      [FeatureAVX2]>;
177def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
178                           "Support bfloat16 floating point",
179                                      [FeatureBWI]>;
180def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
181                       "Enable AVX-512 Bit Algorithms",
182                        [FeatureBWI]>;
183def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
184                                            "HasVP2INTERSECT", "true",
185                                            "Enable AVX-512 vp2intersect",
186                                            [FeatureAVX512]>;
187def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
188                         "Enable packed carry-less multiplication instructions",
189                               [FeatureSSE2]>;
190def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
191                         "Enable Galois Field Arithmetic Instructions",
192                               [FeatureSSE2]>;
193def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
194                                         "Enable vpclmulqdq instructions",
195                                         [FeatureAVX, FeaturePCLMUL]>;
196def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
197                                      "Enable four-operand fused multiple-add",
198                                      [FeatureAVX, FeatureSSE4A]>;
199def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
200                                      "Enable XOP instructions",
201                                      [FeatureFMA4]>;
202def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
203                                          "HasSSEUnalignedMem", "true",
204                      "Allow unaligned memory operands with SSE instructions">;
205def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
206                                      "Enable AES instructions",
207                                      [FeatureSSE2]>;
208def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
209                       "Promote selected AES instructions to AVX512/AVX registers",
210                        [FeatureAVX, FeatureAES]>;
211def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
212                                      "Enable TBM instructions">;
213def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
214                                      "Enable LWP instructions">;
215def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
216                                      "Support MOVBE instruction">;
217def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
218                                      "Support RDRAND instruction">;
219def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
220                                       "Support FS/GS Base instructions">;
221def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
222                                      "Support LZCNT instruction">;
223def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
224                                      "Support BMI instructions">;
225def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
226                                      "Support BMI2 instructions">;
227def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
228                                      "Support RTM instructions">;
229def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
230                                      "Support ADX instructions">;
231def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
232                                      "Enable SHA instructions",
233                                      [FeatureSSE2]>;
234def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
235                       "Support CET Shadow-Stack instructions">;
236def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
237                                      "Support PRFCHW instructions">;
238def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
239                                      "Support RDSEED instruction">;
240def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
241                           "Support LAHF and SAHF instructions in 64-bit mode">;
242def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
243                                      "Enable MONITORX/MWAITX timer functionality">;
244def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
245                                      "Enable Cache Line Zero">;
246def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
247                                      "Enable Cache Demote">;
248def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
249                                      "Support ptwrite instruction">;
250def FeatureAMXTILE     : SubtargetFeature<"amx-tile", "HasAMXTILE", "true",
251                                      "Support AMX-TILE instructions">;
252def FeatureAMXINT8     : SubtargetFeature<"amx-int8", "HasAMXINT8", "true",
253                                      "Support AMX-INT8 instructions",
254                                      [FeatureAMXTILE]>;
255def FeatureAMXBF16     : SubtargetFeature<"amx-bf16", "HasAMXBF16", "true",
256                                      "Support AMX-BF16 instructions",
257                                      [FeatureAMXTILE]>;
258def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
259                                     "Use LEA for adjusting the stack pointer">;
260def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
261                                     "HasSlowDivide32", "true",
262                                     "Use 8-bit divide for positive values less than 256">;
263def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
264                                     "HasSlowDivide64", "true",
265                                     "Use 32-bit divide for positive values less than 2^32">;
266def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
267                                     "PadShortFunctions", "true",
268                                     "Pad short functions">;
269def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
270                                      "Invalidate Process-Context Identifier">;
271def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
272                                      "Enable Software Guard Extensions">;
273def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
274                                      "Flush A Cache Line Optimized">;
275def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
276                                      "Cache Line Write Back">;
277def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
278                                      "Write Back No Invalidate">;
279def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
280                                    "Support RDPID instructions">;
281def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
282                                      "Wait and pause enhancements">;
283def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
284                                     "Has ENQCMD instructions">;
285def FeatureKL  : SubtargetFeature<"kl", "HasKL", "true",
286                                  "Support Key Locker kl Instructions",
287                                  [FeatureSSE2]>;
288def FeatureWIDEKL  : SubtargetFeature<"widekl", "HasWIDEKL", "true",
289                                      "Support Key Locker wide Instructions",
290                                      [FeatureKL]>;
291def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",
292                                      "Has hreset instruction">;
293def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
294                                        "Has serialize instruction">;
295def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",
296                                       "Support TSXLDTRK instructions">;
297def FeatureUINTR : SubtargetFeature<"uintr", "HasUINTR", "true",
298                                    "Has UINTR Instructions">;
299// On some processors, instructions that implicitly take two memory operands are
300// slow. In practice, this means that CALL, PUSH, and POP with memory operands
301// should be avoided in favor of a MOV + register CALL/PUSH/POP.
302def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
303                                     "SlowTwoMemOps", "true",
304                                     "Two memory operand instructions are slow">;
305def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
306                                   "LEA instruction needs inputs at AG stage">;
307def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
308                                   "LEA instruction with certain arguments is slow">;
309def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
310                                   "LEA instruction with 3 ops or certain registers is slow">;
311def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
312                                   "INC and DEC instructions are slower than ADD and SUB">;
313def FeatureSoftFloat
314    : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
315                       "Use software floating point features">;
316def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
317                                     "HasPOPCNTFalseDeps", "true",
318                                     "POPCNT has a false dependency on dest register">;
319def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
320                                     "HasLZCNTFalseDeps", "true",
321                                     "LZCNT/TZCNT have a false dependency on dest register">;
322def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
323                                      "platform configuration instruction">;
324// On recent X86 (port bound) processors, its preferable to combine to a single shuffle
325// using a variable mask over multiple fixed shuffles.
326def FeatureFastVariableCrossLaneShuffle
327    : SubtargetFeature<"fast-variable-crosslane-shuffle",
328                       "HasFastVariableCrossLaneShuffle",
329                       "true", "Cross-lane shuffles with variable masks are fast">;
330def FeatureFastVariablePerLaneShuffle
331    : SubtargetFeature<"fast-variable-perlane-shuffle",
332                       "HasFastVariablePerLaneShuffle",
333                       "true", "Per-lane shuffles with variable masks are fast">;
334
335// On some X86 processors, a vzeroupper instruction should be inserted after
336// using ymm/zmm registers before executing code that may use SSE instructions.
337def FeatureInsertVZEROUPPER
338    : SubtargetFeature<"vzeroupper",
339                       "InsertVZEROUPPER",
340                       "true", "Should insert vzeroupper instructions">;
341// FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
342// than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
343// vector FSQRT has higher throughput than the corresponding NR code.
344// The idea is that throughput bound code is likely to be vectorized, so for
345// vectorized code we should care about the throughput of SQRT operations.
346// But if the code is scalar that probably means that the code has some kind of
347// dependency and we should care more about reducing the latency.
348def FeatureFastScalarFSQRT
349    : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
350                       "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
351def FeatureFastVectorFSQRT
352    : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
353                       "true", "Vector SQRT is fast (disable Newton-Raphson)">;
354// If lzcnt has equivalent latency/throughput to most simple integer ops, it can
355// be used to replace test/set sequences.
356def FeatureFastLZCNT
357    : SubtargetFeature<
358          "fast-lzcnt", "HasFastLZCNT", "true",
359          "LZCNT instructions are as fast as most simple integer ops">;
360// If the target can efficiently decode NOPs upto 7-bytes in length.
361def FeatureFast7ByteNOP
362    : SubtargetFeature<
363          "fast-7bytenop", "HasFast7ByteNOP", "true",
364          "Target can quickly decode up to 7 byte NOPs">;
365// If the target can efficiently decode NOPs upto 11-bytes in length.
366def FeatureFast11ByteNOP
367    : SubtargetFeature<
368          "fast-11bytenop", "HasFast11ByteNOP", "true",
369          "Target can quickly decode up to 11 byte NOPs">;
370// If the target can efficiently decode NOPs upto 15-bytes in length.
371def FeatureFast15ByteNOP
372    : SubtargetFeature<
373          "fast-15bytenop", "HasFast15ByteNOP", "true",
374          "Target can quickly decode up to 15 byte NOPs">;
375// Sandy Bridge and newer processors can use SHLD with the same source on both
376// inputs to implement rotate to avoid the partial flag update of the normal
377// rotate instructions.
378def FeatureFastSHLDRotate
379    : SubtargetFeature<
380          "fast-shld-rotate", "HasFastSHLDRotate", "true",
381          "SHLD can be used as a faster rotate">;
382
383// Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
384// "string operations"). See "REP String Enhancement" in the Intel Software
385// Development Manual. This feature essentially means that REP MOVSB will copy
386// using the largest available size instead of copying bytes one by one, making
387// it at least as fast as REPMOVS{W,D,Q}.
388def FeatureERMSB
389    : SubtargetFeature<
390          "ermsb", "HasERMSB", "true",
391          "REP MOVS/STOS are fast">;
392
393// Icelake and newer processors have Fast Short REP MOV.
394def FeatureFSRM
395    : SubtargetFeature<
396          "fsrm", "HasFSRM", "true",
397          "REP MOVSB of short lengths is faster">;
398
399// Bulldozer and newer processors can merge CMP/TEST (but not other
400// instructions) with conditional branches.
401def FeatureBranchFusion
402    : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
403                 "CMP/TEST can be fused with conditional branches">;
404
405// Sandy Bridge and newer processors have many instructions that can be
406// fused with conditional branches and pass through the CPU as a single
407// operation.
408def FeatureMacroFusion
409    : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
410                 "Various instructions can be fused with conditional branches">;
411
412// Gather is available since Haswell (AVX2 set). So technically, we can
413// generate Gathers on all AVX2 processors. But the overhead on HSW is high.
414// Skylake Client processor has faster Gathers than HSW and performance is
415// similar to Skylake Server (AVX-512).
416def FeatureHasFastGather
417    : SubtargetFeature<"fast-gather", "HasFastGather", "true",
418                       "Indicates if gather is reasonably fast">;
419
420def FeaturePrefer128Bit
421    : SubtargetFeature<"prefer-128-bit", "Prefer128Bit", "true",
422                       "Prefer 128-bit AVX instructions">;
423
424def FeaturePrefer256Bit
425    : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
426                       "Prefer 256-bit AVX instructions">;
427
428def FeaturePreferMaskRegisters
429    : SubtargetFeature<"prefer-mask-registers", "PreferMaskRegisters", "true",
430                       "Prefer AVX512 mask registers over PTEST/MOVMSK">;
431
432// Lower indirect calls using a special construct called a `retpoline` to
433// mitigate potential Spectre v2 attacks against them.
434def FeatureRetpolineIndirectCalls
435    : SubtargetFeature<
436          "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
437          "Remove speculation of indirect calls from the generated code">;
438
439// Lower indirect branches and switches either using conditional branch trees
440// or using a special construct called a `retpoline` to mitigate potential
441// Spectre v2 attacks against them.
442def FeatureRetpolineIndirectBranches
443    : SubtargetFeature<
444          "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
445          "Remove speculation of indirect branches from the generated code">;
446
447// Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
448// `retpoline-indirect-branches` above.
449def FeatureRetpoline
450    : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
451                       "Remove speculation of indirect branches from the "
452                       "generated code, either by avoiding them entirely or "
453                       "lowering them with a speculation blocking construct",
454                       [FeatureRetpolineIndirectCalls,
455                        FeatureRetpolineIndirectBranches]>;
456
457// Rely on external thunks for the emitted retpoline calls. This allows users
458// to provide their own custom thunk definitions in highly specialized
459// environments such as a kernel that does boot-time hot patching.
460def FeatureRetpolineExternalThunk
461    : SubtargetFeature<
462          "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
463          "When lowering an indirect call or branch using a `retpoline`, rely "
464          "on the specified user provided thunk rather than emitting one "
465          "ourselves. Only has effect when combined with some other retpoline "
466          "feature", [FeatureRetpolineIndirectCalls]>;
467
468// Mitigate LVI attacks against indirect calls/branches and call returns
469def FeatureLVIControlFlowIntegrity
470    : SubtargetFeature<
471          "lvi-cfi", "UseLVIControlFlowIntegrity", "true",
472          "Prevent indirect calls/branches from using a memory operand, and "
473          "precede all indirect calls/branches from a register with an "
474          "LFENCE instruction to serialize control flow. Also decompose RET "
475          "instructions into a POP+LFENCE+JMP sequence.">;
476
477// Enable SESES to mitigate speculative execution attacks
478def FeatureSpeculativeExecutionSideEffectSuppression
479    : SubtargetFeature<
480          "seses", "UseSpeculativeExecutionSideEffectSuppression", "true",
481          "Prevent speculative execution side channel timing attacks by "
482          "inserting a speculation barrier before memory reads, memory writes, "
483          "and conditional branches. Implies LVI Control Flow integrity.",
484          [FeatureLVIControlFlowIntegrity]>;
485
486// Mitigate LVI attacks against data loads
487def FeatureLVILoadHardening
488    : SubtargetFeature<
489          "lvi-load-hardening", "UseLVILoadHardening", "true",
490          "Insert LFENCE instructions to prevent data speculatively injected "
491          "into loads from being used maliciously.">;
492
493// Direct Move instructions.
494def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
495                                       "Support movdiri instruction">;
496def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
497                                        "Support movdir64b instruction">;
498
499def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
500          "Indicates that the BEXTR instruction is implemented as a single uop "
501          "with good throughput">;
502
503// Combine vector math operations with shuffles into horizontal math
504// instructions if a CPU implements horizontal operations (introduced with
505// SSE3) with better latency/throughput than the alternative sequence.
506def FeatureFastHorizontalOps
507    : SubtargetFeature<
508        "fast-hops", "HasFastHorizontalOps", "true",
509        "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
510        "normal vector instructions with shuffles">;
511
512def FeatureFastScalarShiftMasks
513    : SubtargetFeature<
514        "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
515        "Prefer a left/right scalar logical shift pair over a shift+and pair">;
516
517def FeatureFastVectorShiftMasks
518    : SubtargetFeature<
519        "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
520        "Prefer a left/right vector logical shift pair over a shift+and pair">;
521
522def FeatureFastMOVBE
523    : SubtargetFeature<"fast-movbe", "HasFastMOVBE", "true",
524    "Prefer a movbe over a single-use load + bswap / single-use bswap + store">;
525
526def FeatureUseGLMDivSqrtCosts
527    : SubtargetFeature<"use-glm-div-sqrt-costs", "UseGLMDivSqrtCosts", "true",
528        "Use Goldmont specific floating point div/sqrt costs">;
529
530// Enable use of alias analysis during code generation.
531def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
532                                    "Use alias analysis during codegen">;
533
534// Bonnell
535def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
536// Silvermont
537def ProcIntelSLM  : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
538
539//===----------------------------------------------------------------------===//
540// Register File Description
541//===----------------------------------------------------------------------===//
542
543include "X86RegisterInfo.td"
544include "X86RegisterBanks.td"
545
546//===----------------------------------------------------------------------===//
547// Instruction Descriptions
548//===----------------------------------------------------------------------===//
549
550include "X86Schedule.td"
551include "X86InstrInfo.td"
552include "X86SchedPredicates.td"
553
554def X86InstrInfo : InstrInfo;
555
556//===----------------------------------------------------------------------===//
557// X86 Scheduler Models
558//===----------------------------------------------------------------------===//
559
560include "X86ScheduleAtom.td"
561include "X86SchedSandyBridge.td"
562include "X86SchedHaswell.td"
563include "X86SchedBroadwell.td"
564include "X86ScheduleSLM.td"
565include "X86ScheduleZnver1.td"
566include "X86ScheduleZnver2.td"
567include "X86ScheduleZnver3.td"
568include "X86ScheduleBdVer2.td"
569include "X86ScheduleBtVer2.td"
570include "X86SchedSkylakeClient.td"
571include "X86SchedSkylakeServer.td"
572
573//===----------------------------------------------------------------------===//
574// X86 Processor Feature Lists
575//===----------------------------------------------------------------------===//
576
577def ProcessorFeatures {
578  // x86-64 and x86-64-v[234]
579  list<SubtargetFeature> X86_64V1Features = [
580    FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, FeatureMMX, FeatureSSE2,
581    FeatureFXSR, FeatureNOPL, Feature64Bit
582  ];
583  list<SubtargetFeature> X86_64V2Features = !listconcat(
584      X86_64V1Features,
585      [FeatureCMPXCHG16B, FeatureLAHFSAHF, FeaturePOPCNT, FeatureSSE42]);
586  list<SubtargetFeature> X86_64V3Features = !listconcat(X86_64V2Features, [
587    FeatureAVX2, FeatureBMI, FeatureBMI2, FeatureF16C, FeatureFMA, FeatureLZCNT,
588    FeatureMOVBE, FeatureXSAVE
589  ]);
590  list<SubtargetFeature> X86_64V4Features = !listconcat(X86_64V3Features, [
591    FeatureBWI,
592    FeatureCDI,
593    FeatureDQI,
594    FeatureVLX,
595  ]);
596
597  // Nehalem
598  list<SubtargetFeature> NHMFeatures = X86_64V2Features;
599  list<SubtargetFeature> NHMTuning = [FeatureMacroFusion,
600                                      FeatureInsertVZEROUPPER];
601
602  // Westmere
603  list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
604  list<SubtargetFeature> WSMTuning = NHMTuning;
605  list<SubtargetFeature> WSMFeatures =
606    !listconcat(NHMFeatures, WSMAdditionalFeatures);
607
608  // Sandybridge
609  list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
610                                                  FeatureXSAVE,
611                                                  FeatureXSAVEOPT];
612  list<SubtargetFeature> SNBTuning = [FeatureMacroFusion,
613                                      FeatureSlow3OpsLEA,
614                                      FeatureSlowDivide64,
615                                      FeatureSlowUAMem32,
616                                      FeatureFastScalarFSQRT,
617                                      FeatureFastSHLDRotate,
618                                      FeatureFast15ByteNOP,
619                                      FeaturePOPCNTFalseDeps,
620                                      FeatureInsertVZEROUPPER];
621  list<SubtargetFeature> SNBFeatures =
622    !listconcat(WSMFeatures, SNBAdditionalFeatures);
623
624  // Ivybridge
625  list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
626                                                  FeatureF16C,
627                                                  FeatureFSGSBase];
628  list<SubtargetFeature> IVBTuning = SNBTuning;
629  list<SubtargetFeature> IVBFeatures =
630    !listconcat(SNBFeatures, IVBAdditionalFeatures);
631
632  // Haswell
633  list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
634                                                  FeatureBMI,
635                                                  FeatureBMI2,
636                                                  FeatureERMSB,
637                                                  FeatureFMA,
638                                                  FeatureINVPCID,
639                                                  FeatureLZCNT,
640                                                  FeatureMOVBE];
641  list<SubtargetFeature> HSWTuning = [FeatureMacroFusion,
642                                      FeatureSlow3OpsLEA,
643                                      FeatureSlowDivide64,
644                                      FeatureFastScalarFSQRT,
645                                      FeatureFastSHLDRotate,
646                                      FeatureFast15ByteNOP,
647                                      FeatureFastVariableCrossLaneShuffle,
648                                      FeatureFastVariablePerLaneShuffle,
649                                      FeaturePOPCNTFalseDeps,
650                                      FeatureLZCNTFalseDeps,
651                                      FeatureInsertVZEROUPPER];
652  list<SubtargetFeature> HSWFeatures =
653    !listconcat(IVBFeatures, HSWAdditionalFeatures);
654
655  // Broadwell
656  list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
657                                                  FeatureRDSEED,
658                                                  FeaturePRFCHW];
659  list<SubtargetFeature> BDWTuning = HSWTuning;
660  list<SubtargetFeature> BDWFeatures =
661    !listconcat(HSWFeatures, BDWAdditionalFeatures);
662
663  // Skylake
664  list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
665                                                  FeatureXSAVEC,
666                                                  FeatureXSAVES,
667                                                  FeatureCLFLUSHOPT];
668  list<SubtargetFeature> SKLTuning = [FeatureHasFastGather,
669                                      FeatureMacroFusion,
670                                      FeatureSlow3OpsLEA,
671                                      FeatureSlowDivide64,
672                                      FeatureFastScalarFSQRT,
673                                      FeatureFastVectorFSQRT,
674                                      FeatureFastSHLDRotate,
675                                      FeatureFast15ByteNOP,
676                                      FeatureFastVariableCrossLaneShuffle,
677                                      FeatureFastVariablePerLaneShuffle,
678                                      FeaturePOPCNTFalseDeps,
679                                      FeatureInsertVZEROUPPER];
680  list<SubtargetFeature> SKLFeatures =
681    !listconcat(BDWFeatures, SKLAdditionalFeatures);
682
683  // Skylake-AVX512
684  list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAES,
685                                                  FeatureXSAVEC,
686                                                  FeatureXSAVES,
687                                                  FeatureCLFLUSHOPT,
688                                                  FeatureAVX512,
689                                                  FeatureCDI,
690                                                  FeatureDQI,
691                                                  FeatureBWI,
692                                                  FeatureVLX,
693                                                  FeaturePKU,
694                                                  FeatureCLWB];
695  list<SubtargetFeature> SKXTuning = [FeatureHasFastGather,
696                                      FeatureMacroFusion,
697                                      FeatureSlow3OpsLEA,
698                                      FeatureSlowDivide64,
699                                      FeatureFastScalarFSQRT,
700                                      FeatureFastVectorFSQRT,
701                                      FeatureFastSHLDRotate,
702                                      FeatureFast15ByteNOP,
703                                      FeatureFastVariableCrossLaneShuffle,
704                                      FeatureFastVariablePerLaneShuffle,
705                                      FeaturePrefer256Bit,
706                                      FeaturePOPCNTFalseDeps,
707                                      FeatureInsertVZEROUPPER];
708  list<SubtargetFeature> SKXFeatures =
709    !listconcat(BDWFeatures, SKXAdditionalFeatures);
710
711  // Cascadelake
712  list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
713  list<SubtargetFeature> CLXTuning = SKXTuning;
714  list<SubtargetFeature> CLXFeatures =
715    !listconcat(SKXFeatures, CLXAdditionalFeatures);
716
717  // Cooperlake
718  list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
719  list<SubtargetFeature> CPXTuning = SKXTuning;
720  list<SubtargetFeature> CPXFeatures =
721    !listconcat(CLXFeatures, CPXAdditionalFeatures);
722
723  // Cannonlake
724  list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
725                                                  FeatureCDI,
726                                                  FeatureDQI,
727                                                  FeatureBWI,
728                                                  FeatureVLX,
729                                                  FeaturePKU,
730                                                  FeatureVBMI,
731                                                  FeatureIFMA,
732                                                  FeatureSHA];
733  list<SubtargetFeature> CNLTuning = [FeatureHasFastGather,
734                                      FeatureMacroFusion,
735                                      FeatureSlow3OpsLEA,
736                                      FeatureSlowDivide64,
737                                      FeatureFastScalarFSQRT,
738                                      FeatureFastVectorFSQRT,
739                                      FeatureFastSHLDRotate,
740                                      FeatureFast15ByteNOP,
741                                      FeatureFastVariableCrossLaneShuffle,
742                                      FeatureFastVariablePerLaneShuffle,
743                                      FeaturePrefer256Bit,
744                                      FeatureInsertVZEROUPPER];
745  list<SubtargetFeature> CNLFeatures =
746    !listconcat(SKLFeatures, CNLAdditionalFeatures);
747
748  // Icelake
749  list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
750                                                  FeatureVAES,
751                                                  FeatureVBMI2,
752                                                  FeatureVNNI,
753                                                  FeatureVPCLMULQDQ,
754                                                  FeatureVPOPCNTDQ,
755                                                  FeatureGFNI,
756                                                  FeatureRDPID,
757                                                  FeatureFSRM];
758  list<SubtargetFeature> ICLTuning = CNLTuning;
759  list<SubtargetFeature> ICLFeatures =
760    !listconcat(CNLFeatures, ICLAdditionalFeatures);
761
762  // Icelake Server
763  list<SubtargetFeature> ICXAdditionalFeatures = [FeaturePCONFIG,
764                                                  FeatureCLWB,
765                                                  FeatureWBNOINVD];
766  list<SubtargetFeature> ICXTuning = CNLTuning;
767  list<SubtargetFeature> ICXFeatures =
768    !listconcat(ICLFeatures, ICXAdditionalFeatures);
769
770  // Tigerlake
771  list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
772                                                  FeatureCLWB,
773                                                  FeatureMOVDIRI,
774                                                  FeatureMOVDIR64B,
775                                                  FeatureSHSTK];
776  list<SubtargetFeature> TGLTuning = CNLTuning;
777  list<SubtargetFeature> TGLFeatures =
778    !listconcat(ICLFeatures, TGLAdditionalFeatures );
779
780  // Sapphirerapids
781  list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
782                                                  FeatureAMXINT8,
783                                                  FeatureAMXBF16,
784                                                  FeatureBF16,
785                                                  FeatureSERIALIZE,
786                                                  FeatureCLDEMOTE,
787                                                  FeatureWAITPKG,
788                                                  FeaturePTWRITE,
789                                                  FeatureAVXVNNI,
790                                                  FeatureTSXLDTRK,
791                                                  FeatureENQCMD,
792                                                  FeatureSHSTK,
793                                                  FeatureVP2INTERSECT,
794                                                  FeatureMOVDIRI,
795                                                  FeatureMOVDIR64B,
796                                                  FeatureUINTR];
797  list<SubtargetFeature> SPRTuning = ICXTuning;
798  list<SubtargetFeature> SPRFeatures =
799    !listconcat(ICXFeatures, SPRAdditionalFeatures);
800
801  // Atom
802  list<SubtargetFeature> AtomFeatures = [FeatureX87,
803                                         FeatureCMPXCHG8B,
804                                         FeatureCMOV,
805                                         FeatureMMX,
806                                         FeatureSSSE3,
807                                         FeatureFXSR,
808                                         FeatureNOPL,
809                                         Feature64Bit,
810                                         FeatureCMPXCHG16B,
811                                         FeatureMOVBE,
812                                         FeatureLAHFSAHF];
813  list<SubtargetFeature> AtomTuning = [ProcIntelAtom,
814                                       FeatureSlowUAMem16,
815                                       FeatureLEAForSP,
816                                       FeatureSlowDivide32,
817                                       FeatureSlowDivide64,
818                                       FeatureSlowTwoMemOps,
819                                       FeatureLEAUsesAG,
820                                       FeaturePadShortFunctions,
821                                       FeatureInsertVZEROUPPER];
822
823  // Silvermont
824  list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
825                                                  FeaturePOPCNT,
826                                                  FeaturePCLMUL,
827                                                  FeaturePRFCHW,
828                                                  FeatureRDRAND];
829  list<SubtargetFeature> SLMTuning = [ProcIntelSLM,
830                                      FeatureSlowTwoMemOps,
831                                      FeatureSlowLEA,
832                                      FeatureSlowIncDec,
833                                      FeatureSlowDivide64,
834                                      FeatureSlowPMULLD,
835                                      FeatureFast7ByteNOP,
836                                      FeatureFastMOVBE,
837                                      FeaturePOPCNTFalseDeps,
838                                      FeatureInsertVZEROUPPER];
839  list<SubtargetFeature> SLMFeatures =
840    !listconcat(AtomFeatures, SLMAdditionalFeatures);
841
842  // Goldmont
843  list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
844                                                  FeatureSHA,
845                                                  FeatureRDSEED,
846                                                  FeatureXSAVE,
847                                                  FeatureXSAVEOPT,
848                                                  FeatureXSAVEC,
849                                                  FeatureXSAVES,
850                                                  FeatureCLFLUSHOPT,
851                                                  FeatureFSGSBase];
852  list<SubtargetFeature> GLMTuning = [FeatureUseGLMDivSqrtCosts,
853                                      FeatureSlowTwoMemOps,
854                                      FeatureSlowLEA,
855                                      FeatureSlowIncDec,
856                                      FeatureFastMOVBE,
857                                      FeaturePOPCNTFalseDeps,
858                                      FeatureInsertVZEROUPPER];
859  list<SubtargetFeature> GLMFeatures =
860    !listconcat(SLMFeatures, GLMAdditionalFeatures);
861
862  // Goldmont Plus
863  list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
864                                                  FeatureRDPID];
865  list<SubtargetFeature> GLPTuning = [FeatureUseGLMDivSqrtCosts,
866                                      FeatureSlowTwoMemOps,
867                                      FeatureSlowLEA,
868                                      FeatureSlowIncDec,
869                                      FeatureFastMOVBE,
870                                      FeatureInsertVZEROUPPER];
871  list<SubtargetFeature> GLPFeatures =
872    !listconcat(GLMFeatures, GLPAdditionalFeatures);
873
874  // Tremont
875  list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLWB,
876                                                  FeatureGFNI];
877  list<SubtargetFeature> TRMTuning = GLPTuning;
878  list<SubtargetFeature> TRMFeatures =
879    !listconcat(GLPFeatures, TRMAdditionalFeatures);
880
881  // Alderlake
882  list<SubtargetFeature> ADLAdditionalFeatures = [FeatureSERIALIZE,
883                                                  FeaturePCONFIG,
884                                                  FeatureSHSTK,
885                                                  FeatureWIDEKL,
886                                                  FeatureINVPCID,
887                                                  FeatureADX,
888                                                  FeatureFMA,
889                                                  FeatureVAES,
890                                                  FeatureVPCLMULQDQ,
891                                                  FeatureF16C,
892                                                  FeatureBMI,
893                                                  FeatureBMI2,
894                                                  FeatureLZCNT,
895                                                  FeatureAVXVNNI,
896                                                  FeaturePKU,
897                                                  FeatureHRESET,
898                                                  FeatureCLDEMOTE,
899                                                  FeatureMOVDIRI,
900                                                  FeatureMOVDIR64B,
901                                                  FeatureWAITPKG];
902  list<SubtargetFeature> ADLTuning = SKLTuning;
903  list<SubtargetFeature> ADLFeatures =
904    !listconcat(TRMFeatures, ADLAdditionalFeatures);
905
906  // Knights Landing
907  list<SubtargetFeature> KNLFeatures = [FeatureX87,
908                                        FeatureCMPXCHG8B,
909                                        FeatureCMOV,
910                                        FeatureMMX,
911                                        FeatureFXSR,
912                                        FeatureNOPL,
913                                        Feature64Bit,
914                                        FeatureCMPXCHG16B,
915                                        FeaturePOPCNT,
916                                        FeaturePCLMUL,
917                                        FeatureXSAVE,
918                                        FeatureXSAVEOPT,
919                                        FeatureLAHFSAHF,
920                                        FeatureAES,
921                                        FeatureRDRAND,
922                                        FeatureF16C,
923                                        FeatureFSGSBase,
924                                        FeatureAVX512,
925                                        FeatureERI,
926                                        FeatureCDI,
927                                        FeaturePFI,
928                                        FeaturePREFETCHWT1,
929                                        FeatureADX,
930                                        FeatureRDSEED,
931                                        FeatureMOVBE,
932                                        FeatureLZCNT,
933                                        FeatureBMI,
934                                        FeatureBMI2,
935                                        FeatureFMA,
936                                        FeaturePRFCHW];
937  list<SubtargetFeature> KNLTuning = [FeatureSlowDivide64,
938                                      FeatureSlow3OpsLEA,
939                                      FeatureSlowIncDec,
940                                      FeatureSlowTwoMemOps,
941                                      FeaturePreferMaskRegisters,
942                                      FeatureHasFastGather,
943                                      FeatureFastMOVBE,
944                                      FeatureSlowPMADDWD];
945  // TODO Add AVX5124FMAPS/AVX5124VNNIW features
946  list<SubtargetFeature> KNMFeatures =
947    !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
948
949  // Barcelona
950  list<SubtargetFeature> BarcelonaFeatures = [FeatureX87,
951                                              FeatureCMPXCHG8B,
952                                              FeatureSSE4A,
953                                              Feature3DNowA,
954                                              FeatureFXSR,
955                                              FeatureNOPL,
956                                              FeatureCMPXCHG16B,
957                                              FeaturePRFCHW,
958                                              FeatureLZCNT,
959                                              FeaturePOPCNT,
960                                              FeatureLAHFSAHF,
961                                              FeatureCMOV,
962                                              Feature64Bit];
963  list<SubtargetFeature> BarcelonaTuning = [FeatureFastScalarShiftMasks,
964                                            FeatureSlowSHLD,
965                                            FeatureInsertVZEROUPPER];
966
967  // Bobcat
968  list<SubtargetFeature> BtVer1Features = [FeatureX87,
969                                           FeatureCMPXCHG8B,
970                                           FeatureCMOV,
971                                           FeatureMMX,
972                                           FeatureSSSE3,
973                                           FeatureSSE4A,
974                                           FeatureFXSR,
975                                           FeatureNOPL,
976                                           Feature64Bit,
977                                           FeatureCMPXCHG16B,
978                                           FeaturePRFCHW,
979                                           FeatureLZCNT,
980                                           FeaturePOPCNT,
981                                           FeatureLAHFSAHF];
982  list<SubtargetFeature> BtVer1Tuning = [FeatureFast15ByteNOP,
983                                         FeatureFastScalarShiftMasks,
984                                         FeatureFastVectorShiftMasks,
985                                         FeatureSlowSHLD,
986                                         FeatureInsertVZEROUPPER];
987
988  // Jaguar
989  list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
990                                                     FeatureAES,
991                                                     FeaturePCLMUL,
992                                                     FeatureBMI,
993                                                     FeatureF16C,
994                                                     FeatureMOVBE,
995                                                     FeatureXSAVE,
996                                                     FeatureXSAVEOPT];
997  list<SubtargetFeature> BtVer2Tuning = [FeatureFastLZCNT,
998                                         FeatureFastBEXTR,
999                                         FeatureFastHorizontalOps,
1000                                         FeatureFast15ByteNOP,
1001                                         FeatureFastScalarShiftMasks,
1002                                         FeatureFastVectorShiftMasks,
1003                                         FeatureFastMOVBE,
1004                                         FeatureSlowSHLD];
1005  list<SubtargetFeature> BtVer2Features =
1006    !listconcat(BtVer1Features, BtVer2AdditionalFeatures);
1007
1008  // Bulldozer
1009  list<SubtargetFeature> BdVer1Features = [FeatureX87,
1010                                           FeatureCMPXCHG8B,
1011                                           FeatureCMOV,
1012                                           FeatureXOP,
1013                                           Feature64Bit,
1014                                           FeatureCMPXCHG16B,
1015                                           FeatureAES,
1016                                           FeaturePRFCHW,
1017                                           FeaturePCLMUL,
1018                                           FeatureMMX,
1019                                           FeatureFXSR,
1020                                           FeatureNOPL,
1021                                           FeatureLZCNT,
1022                                           FeaturePOPCNT,
1023                                           FeatureXSAVE,
1024                                           FeatureLWP,
1025                                           FeatureLAHFSAHF];
1026  list<SubtargetFeature> BdVer1Tuning = [FeatureSlowSHLD,
1027                                         FeatureFast11ByteNOP,
1028                                         FeatureFastScalarShiftMasks,
1029                                         FeatureBranchFusion,
1030                                         FeatureInsertVZEROUPPER];
1031
1032  // PileDriver
1033  list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
1034                                                     FeatureBMI,
1035                                                     FeatureTBM,
1036                                                     FeatureFMA,
1037                                                     FeatureFastBEXTR];
1038  list<SubtargetFeature> BdVer2AdditionalTuning = [FeatureFastMOVBE];
1039  list<SubtargetFeature> BdVer2Tuning =
1040    !listconcat(BdVer1Tuning, BdVer2AdditionalTuning);
1041  list<SubtargetFeature> BdVer2Features =
1042    !listconcat(BdVer1Features, BdVer2AdditionalFeatures);
1043
1044  // Steamroller
1045  list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
1046                                                     FeatureFSGSBase];
1047  list<SubtargetFeature> BdVer3Tuning = BdVer2Tuning;
1048  list<SubtargetFeature> BdVer3Features =
1049    !listconcat(BdVer2Features, BdVer3AdditionalFeatures);
1050
1051  // Excavator
1052  list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
1053                                                     FeatureBMI2,
1054                                                     FeatureMOVBE,
1055                                                     FeatureRDRAND,
1056                                                     FeatureMWAITX];
1057  list<SubtargetFeature> BdVer4Tuning = BdVer3Tuning;
1058  list<SubtargetFeature> BdVer4Features =
1059    !listconcat(BdVer3Features, BdVer4AdditionalFeatures);
1060
1061
1062  // AMD Zen Processors common ISAs
1063  list<SubtargetFeature> ZNFeatures = [FeatureADX,
1064                                       FeatureAES,
1065                                       FeatureAVX2,
1066                                       FeatureBMI,
1067                                       FeatureBMI2,
1068                                       FeatureCLFLUSHOPT,
1069                                       FeatureCLZERO,
1070                                       FeatureCMOV,
1071                                       Feature64Bit,
1072                                       FeatureCMPXCHG16B,
1073                                       FeatureF16C,
1074                                       FeatureFMA,
1075                                       FeatureFSGSBase,
1076                                       FeatureFXSR,
1077                                       FeatureNOPL,
1078                                       FeatureLAHFSAHF,
1079                                       FeatureLZCNT,
1080                                       FeatureMMX,
1081                                       FeatureMOVBE,
1082                                       FeatureMWAITX,
1083                                       FeaturePCLMUL,
1084                                       FeaturePOPCNT,
1085                                       FeaturePRFCHW,
1086                                       FeatureRDRAND,
1087                                       FeatureRDSEED,
1088                                       FeatureSHA,
1089                                       FeatureSSE4A,
1090                                       FeatureX87,
1091                                       FeatureXSAVE,
1092                                       FeatureXSAVEC,
1093                                       FeatureXSAVEOPT,
1094                                       FeatureXSAVES];
1095  list<SubtargetFeature> ZNTuning = [FeatureFastLZCNT,
1096                                     FeatureFastBEXTR,
1097                                     FeatureFast15ByteNOP,
1098                                     FeatureBranchFusion,
1099                                     FeatureFastScalarShiftMasks,
1100                                     FeatureFastMOVBE,
1101                                     FeatureSlowSHLD,
1102                                     FeatureInsertVZEROUPPER];
1103  list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
1104                                                  FeatureRDPID,
1105                                                  FeatureWBNOINVD];
1106  list<SubtargetFeature> ZN2Tuning = ZNTuning;
1107  list<SubtargetFeature> ZN2Features =
1108    !listconcat(ZNFeatures, ZN2AdditionalFeatures);
1109  list<SubtargetFeature> ZN3AdditionalFeatures = [FeatureFSRM,
1110                                                  FeatureINVPCID,
1111                                                  FeaturePKU,
1112                                                  FeatureVAES,
1113                                                  FeatureVPCLMULQDQ];
1114  list<SubtargetFeature> ZN3AdditionalTuning =
1115    [FeatureMacroFusion,
1116     FeatureFastVariablePerLaneShuffle];
1117  list<SubtargetFeature> ZN3Tuning =
1118    !listconcat(ZNTuning, ZN3AdditionalTuning);
1119  list<SubtargetFeature> ZN3Features =
1120    !listconcat(ZN2Features, ZN3AdditionalFeatures);
1121}
1122
1123//===----------------------------------------------------------------------===//
1124// X86 processors supported.
1125//===----------------------------------------------------------------------===//
1126
1127class Proc<string Name, list<SubtargetFeature> Features,
1128           list<SubtargetFeature> TuneFeatures>
1129 : ProcessorModel<Name, GenericModel, Features, TuneFeatures>;
1130
1131class ProcModel<string Name, SchedMachineModel Model,
1132                list<SubtargetFeature> Features,
1133                list<SubtargetFeature> TuneFeatures>
1134 : ProcessorModel<Name, Model, Features, TuneFeatures>;
1135
1136// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
1137// if i386/i486 is specifically requested.
1138// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
1139// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled.
1140// It has no effect on code generation.
1141def : ProcModel<"generic", SandyBridgeModel,
1142                [FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
1143                [FeatureSlow3OpsLEA,
1144                 FeatureSlowDivide64,
1145                 FeatureSlowIncDec,
1146                 FeatureMacroFusion,
1147                 FeatureInsertVZEROUPPER]>;
1148
1149def : Proc<"i386",            [FeatureX87],
1150                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1151def : Proc<"i486",            [FeatureX87],
1152                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1153def : Proc<"i586",            [FeatureX87, FeatureCMPXCHG8B],
1154                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1155def : Proc<"pentium",         [FeatureX87, FeatureCMPXCHG8B],
1156                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1157def : Proc<"pentium-mmx",     [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
1158                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1159
1160def : Proc<"i686", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV],
1161                   [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1162def : Proc<"pentiumpro", [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
1163                          FeatureNOPL],
1164                         [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1165
1166def : Proc<"pentium2", [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureCMOV,
1167                        FeatureFXSR, FeatureNOPL],
1168                       [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1169
1170foreach P = ["pentium3", "pentium3m"] in {
1171  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
1172                 FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV],
1173                [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1174}
1175
1176// Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
1177// The intent is to enable it for pentium4 which is the current default
1178// processor in a vanilla 32-bit clang compilation when no specific
1179// architecture is specified.  This generally gives a nice performance
1180// increase on silvermont, with largely neutral behavior on other
1181// contemporary large core processors.
1182// pentium-m, pentium4m, prescott and nocona are included as a preventative
1183// measure to avoid performance surprises, in case clang's default cpu
1184// changes slightly.
1185
1186def : ProcModel<"pentium-m", GenericPostRAModel,
1187                [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
1188                FeatureFXSR, FeatureNOPL, FeatureCMOV],
1189                [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1190
1191foreach P = ["pentium4", "pentium4m"] in {
1192  def : ProcModel<P, GenericPostRAModel,
1193                  [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE2,
1194                   FeatureFXSR, FeatureNOPL, FeatureCMOV],
1195                  [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1196}
1197
1198// Intel Quark.
1199def : Proc<"lakemont", [FeatureCMPXCHG8B],
1200                       [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1201
1202// Intel Core Duo.
1203def : ProcModel<"yonah", SandyBridgeModel,
1204                [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
1205                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1206                [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1207
1208// NetBurst.
1209def : ProcModel<"prescott", GenericPostRAModel,
1210                [FeatureX87, FeatureCMPXCHG8B, FeatureMMX, FeatureSSE3,
1211                 FeatureFXSR, FeatureNOPL, FeatureCMOV],
1212                [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1213def : ProcModel<"nocona", GenericPostRAModel, [
1214  FeatureX87,
1215  FeatureCMPXCHG8B,
1216  FeatureCMOV,
1217  FeatureMMX,
1218  FeatureSSE3,
1219  FeatureFXSR,
1220  FeatureNOPL,
1221  Feature64Bit,
1222  FeatureCMPXCHG16B,
1223],
1224[
1225  FeatureSlowUAMem16,
1226  FeatureInsertVZEROUPPER
1227]>;
1228
1229// Intel Core 2 Solo/Duo.
1230def : ProcModel<"core2", SandyBridgeModel, [
1231  FeatureX87,
1232  FeatureCMPXCHG8B,
1233  FeatureCMOV,
1234  FeatureMMX,
1235  FeatureSSSE3,
1236  FeatureFXSR,
1237  FeatureNOPL,
1238  Feature64Bit,
1239  FeatureCMPXCHG16B,
1240  FeatureLAHFSAHF
1241],
1242[
1243  FeatureMacroFusion,
1244  FeatureSlowUAMem16,
1245  FeatureInsertVZEROUPPER
1246]>;
1247def : ProcModel<"penryn", SandyBridgeModel, [
1248  FeatureX87,
1249  FeatureCMPXCHG8B,
1250  FeatureCMOV,
1251  FeatureMMX,
1252  FeatureSSE41,
1253  FeatureFXSR,
1254  FeatureNOPL,
1255  Feature64Bit,
1256  FeatureCMPXCHG16B,
1257  FeatureLAHFSAHF
1258],
1259[
1260  FeatureMacroFusion,
1261  FeatureSlowUAMem16,
1262  FeatureInsertVZEROUPPER
1263]>;
1264
1265// Atom CPUs.
1266foreach P = ["bonnell", "atom"] in {
1267  def : ProcModel<P, AtomModel, ProcessorFeatures.AtomFeatures,
1268                  ProcessorFeatures.AtomTuning>;
1269}
1270
1271foreach P = ["silvermont", "slm"] in {
1272  def : ProcModel<P, SLMModel, ProcessorFeatures.SLMFeatures,
1273                  ProcessorFeatures.SLMTuning>;
1274}
1275
1276def : ProcModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures,
1277                ProcessorFeatures.GLMTuning>;
1278def : ProcModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures,
1279                ProcessorFeatures.GLPTuning>;
1280def : ProcModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures,
1281                ProcessorFeatures.TRMTuning>;
1282
1283// "Arrandale" along with corei3 and corei5
1284foreach P = ["nehalem", "corei7"] in {
1285  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures,
1286                  ProcessorFeatures.NHMTuning>;
1287}
1288
1289// Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1290def : ProcModel<"westmere", SandyBridgeModel, ProcessorFeatures.WSMFeatures,
1291                ProcessorFeatures.WSMTuning>;
1292
1293foreach P = ["sandybridge", "corei7-avx"] in {
1294  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures,
1295                  ProcessorFeatures.SNBTuning>;
1296}
1297
1298foreach P = ["ivybridge", "core-avx-i"] in {
1299  def : ProcModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures,
1300                  ProcessorFeatures.IVBTuning>;
1301}
1302
1303foreach P = ["haswell", "core-avx2"] in {
1304  def : ProcModel<P, HaswellModel, ProcessorFeatures.HSWFeatures,
1305                  ProcessorFeatures.HSWTuning>;
1306}
1307
1308def : ProcModel<"broadwell", BroadwellModel, ProcessorFeatures.BDWFeatures,
1309                ProcessorFeatures.BDWTuning>;
1310
1311def : ProcModel<"skylake", SkylakeClientModel, ProcessorFeatures.SKLFeatures,
1312                ProcessorFeatures.SKLTuning>;
1313
1314// FIXME: define KNL scheduler model
1315def : ProcModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures,
1316                ProcessorFeatures.KNLTuning>;
1317def : ProcModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures,
1318                ProcessorFeatures.KNLTuning>;
1319
1320foreach P = ["skylake-avx512", "skx"] in {
1321  def : ProcModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures,
1322                  ProcessorFeatures.SKXTuning>;
1323}
1324
1325def : ProcModel<"cascadelake", SkylakeServerModel,
1326                ProcessorFeatures.CLXFeatures, ProcessorFeatures.CLXTuning>;
1327def : ProcModel<"cooperlake", SkylakeServerModel,
1328                ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
1329def : ProcModel<"cannonlake", SkylakeServerModel,
1330                ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
1331def : ProcModel<"icelake-client", SkylakeServerModel,
1332                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1333def : ProcModel<"rocketlake", SkylakeServerModel,
1334                ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
1335def : ProcModel<"icelake-server", SkylakeServerModel,
1336                ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
1337def : ProcModel<"tigerlake", SkylakeServerModel,
1338                ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
1339def : ProcModel<"sapphirerapids", SkylakeServerModel,
1340                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
1341def : ProcModel<"alderlake", SkylakeClientModel,
1342                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
1343
1344// AMD CPUs.
1345
1346def : Proc<"k6",   [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
1347                   [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1348def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
1349                   [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1350def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
1351                   [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1352
1353foreach P = ["athlon", "athlon-tbird"] in {
1354  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV, Feature3DNowA,
1355                 FeatureNOPL],
1356                [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1357}
1358
1359foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1360  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureCMOV,
1361                 FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL],
1362                [FeatureSlowSHLD, FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1363}
1364
1365foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1366  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE2, Feature3DNowA,
1367                 FeatureFXSR, FeatureNOPL, Feature64Bit, FeatureCMOV],
1368                [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
1369                 FeatureInsertVZEROUPPER]>;
1370}
1371
1372foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1373  def : Proc<P, [FeatureX87, FeatureCMPXCHG8B, FeatureSSE3, Feature3DNowA,
1374                 FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B, FeatureCMOV,
1375                 Feature64Bit],
1376                [FeatureFastScalarShiftMasks, FeatureSlowSHLD, FeatureSlowUAMem16,
1377                 FeatureInsertVZEROUPPER]>;
1378}
1379
1380foreach P = ["amdfam10", "barcelona"] in {
1381  def : Proc<P, ProcessorFeatures.BarcelonaFeatures,
1382             ProcessorFeatures.BarcelonaTuning>;
1383}
1384
1385// Bobcat
1386def : Proc<"btver1", ProcessorFeatures.BtVer1Features,
1387           ProcessorFeatures.BtVer1Tuning>;
1388// Jaguar
1389def : ProcModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features,
1390                ProcessorFeatures.BtVer2Tuning>;
1391
1392// Bulldozer
1393def : ProcModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features,
1394                ProcessorFeatures.BdVer1Tuning>;
1395// Piledriver
1396def : ProcModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features,
1397                ProcessorFeatures.BdVer2Tuning>;
1398// Steamroller
1399def : Proc<"bdver3", ProcessorFeatures.BdVer3Features,
1400           ProcessorFeatures.BdVer3Tuning>;
1401// Excavator
1402def : Proc<"bdver4", ProcessorFeatures.BdVer4Features,
1403           ProcessorFeatures.BdVer4Tuning>;
1404
1405def : ProcModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures,
1406                ProcessorFeatures.ZNTuning>;
1407def : ProcModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features,
1408                ProcessorFeatures.ZN2Tuning>;
1409def : ProcModel<"znver3", Znver3Model, ProcessorFeatures.ZN3Features,
1410                ProcessorFeatures.ZN3Tuning>;
1411
1412def : Proc<"geode",           [FeatureX87, FeatureCMPXCHG8B, Feature3DNowA],
1413                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1414
1415def : Proc<"winchip-c6",      [FeatureX87, FeatureMMX],
1416                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1417def : Proc<"winchip2",        [FeatureX87, Feature3DNow],
1418                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1419def : Proc<"c3",              [FeatureX87, Feature3DNow],
1420                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1421def : Proc<"c3-2",            [FeatureX87, FeatureCMPXCHG8B, FeatureMMX,
1422                               FeatureSSE1, FeatureFXSR, FeatureCMOV],
1423                              [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
1424
1425// We also provide a generic 64-bit specific x86 processor model which tries to
1426// be good for modern chips without enabling instruction set encodings past the
1427// basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1428// modern 64-bit x86 chip, and enables features that are generally beneficial.
1429//
1430// We currently use the Sandy Bridge model as the default scheduling model as
1431// we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1432// covers a huge swath of x86 processors. If there are specific scheduling
1433// knobs which need to be tuned differently for AMD chips, we might consider
1434// forming a common base for them.
1435def : ProcModel<"x86-64", SandyBridgeModel, ProcessorFeatures.X86_64V1Features,
1436[
1437  FeatureSlow3OpsLEA,
1438  FeatureSlowDivide64,
1439  FeatureSlowIncDec,
1440  FeatureMacroFusion,
1441  FeatureInsertVZEROUPPER
1442]>;
1443
1444// x86-64 micro-architecture levels.
1445def : ProcModel<"x86-64-v2", SandyBridgeModel, ProcessorFeatures.X86_64V2Features,
1446                ProcessorFeatures.SNBTuning>;
1447// Close to Haswell.
1448def : ProcModel<"x86-64-v3", HaswellModel, ProcessorFeatures.X86_64V3Features,
1449                ProcessorFeatures.HSWTuning>;
1450// Close to the AVX-512 level implemented by Xeon Scalable Processors.
1451def : ProcModel<"x86-64-v4", SkylakeServerModel, ProcessorFeatures.X86_64V4Features,
1452                ProcessorFeatures.SKXTuning>;
1453
1454//===----------------------------------------------------------------------===//
1455// Calling Conventions
1456//===----------------------------------------------------------------------===//
1457
1458include "X86CallingConv.td"
1459
1460
1461//===----------------------------------------------------------------------===//
1462// Assembly Parser
1463//===----------------------------------------------------------------------===//
1464
1465def ATTAsmParserVariant : AsmParserVariant {
1466  int Variant = 0;
1467
1468  // Variant name.
1469  string Name = "att";
1470
1471  // Discard comments in assembly strings.
1472  string CommentDelimiter = "#";
1473
1474  // Recognize hard coded registers.
1475  string RegisterPrefix = "%";
1476}
1477
1478def IntelAsmParserVariant : AsmParserVariant {
1479  int Variant = 1;
1480
1481  // Variant name.
1482  string Name = "intel";
1483
1484  // Discard comments in assembly strings.
1485  string CommentDelimiter = ";";
1486
1487  // Recognize hard coded registers.
1488  string RegisterPrefix = "";
1489}
1490
1491//===----------------------------------------------------------------------===//
1492// Assembly Printers
1493//===----------------------------------------------------------------------===//
1494
1495// The X86 target supports two different syntaxes for emitting machine code.
1496// This is controlled by the -x86-asm-syntax={att|intel}
1497def ATTAsmWriter : AsmWriter {
1498  string AsmWriterClassName  = "ATTInstPrinter";
1499  int Variant = 0;
1500}
1501def IntelAsmWriter : AsmWriter {
1502  string AsmWriterClassName  = "IntelInstPrinter";
1503  int Variant = 1;
1504}
1505
1506def X86 : Target {
1507  // Information about the instructions...
1508  let InstructionSet = X86InstrInfo;
1509  let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1510  let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1511  let AllowRegisterRenaming = 1;
1512}
1513
1514//===----------------------------------------------------------------------===//
1515// Pfm Counters
1516//===----------------------------------------------------------------------===//
1517
1518include "X86PfmCounters.td"
1519