xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h (revision e53a21abdf2953714e44e3c54b4bb78557cb096c)
1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provides X86 specific target descriptions.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H
15 
16 #include "llvm/ADT/SmallVector.h"
17 #include <memory>
18 #include <string>
19 
20 namespace llvm {
21 class formatted_raw_ostream;
22 class MCAsmBackend;
23 class MCCodeEmitter;
24 class MCContext;
25 class MCInst;
26 class MCInstPrinter;
27 class MCInstrInfo;
28 class MCObjectStreamer;
29 class MCObjectTargetWriter;
30 class MCObjectWriter;
31 class MCRegister;
32 class MCRegisterInfo;
33 class MCStreamer;
34 class MCSubtargetInfo;
35 class MCTargetOptions;
36 class MCTargetStreamer;
37 class Target;
38 class Triple;
39 class StringRef;
40 
41 /// Flavour of dwarf regnumbers
42 ///
43 namespace DWARFFlavour {
44   enum {
45     X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2
46   };
47 }
48 
49 ///  Native X86 register numbers
50 ///
51 namespace N86 {
52   enum {
53     EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7
54   };
55 }
56 
57 namespace X86_MC {
58 std::string ParseX86Triple(const Triple &TT);
59 
60 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH);
61 
62 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI);
63 
64 
65 /// Returns true if this instruction has a LOCK prefix.
66 bool hasLockPrefix(const MCInst &MI);
67 
68 /// \param Op operand # of the memory operand.
69 ///
70 /// \returns true if the specified instruction has a 16-bit memory operand.
71 bool is16BitMemOperand(const MCInst &MI, unsigned Op,
72                        const MCSubtargetInfo &STI);
73 
74 /// \param Op operand # of the memory operand.
75 ///
76 /// \returns true if the specified instruction has a 32-bit memory operand.
77 bool is32BitMemOperand(const MCInst &MI, unsigned Op);
78 
79 /// \param Op operand # of the memory operand.
80 ///
81 /// \returns true if the specified instruction has a 64-bit memory operand.
82 #ifndef NDEBUG
83 bool is64BitMemOperand(const MCInst &MI, unsigned Op);
84 #endif
85 
86 /// Returns true if this instruction needs an Address-Size override prefix.
87 bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI,
88                               int MemoryOperand, uint64_t TSFlags);
89 
90 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc.
91 /// do not need to go through TargetRegistry.
92 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU,
93                                           StringRef FS);
94 
95 void emitInstruction(MCObjectStreamer &, const MCInst &Inst,
96                      const MCSubtargetInfo &STI);
97 
98 void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl<char> &CB,
99                 const MCSubtargetInfo &STI);
100 }
101 
102 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
103                                       MCContext &Ctx);
104 
105 MCAsmBackend *createX86_32AsmBackend(const Target &T,
106                                      const MCSubtargetInfo &STI,
107                                      const MCRegisterInfo &MRI,
108                                      const MCTargetOptions &Options);
109 MCAsmBackend *createX86_64AsmBackend(const Target &T,
110                                      const MCSubtargetInfo &STI,
111                                      const MCRegisterInfo &MRI,
112                                      const MCTargetOptions &Options);
113 
114 /// Implements X86-only directives for assembly emission.
115 MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S,
116                                              formatted_raw_ostream &OS,
117                                              MCInstPrinter *InstPrinter);
118 
119 /// Implements X86-only directives for object files.
120 MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &S,
121                                                 const MCSubtargetInfo &STI);
122 
123 /// Construct an X86 Windows COFF machine code streamer which will generate
124 /// PE/COFF format object files.
125 ///
126 /// Takes ownership of \p AB and \p CE.
127 MCStreamer *createX86WinCOFFStreamer(MCContext &C,
128                                      std::unique_ptr<MCAsmBackend> &&AB,
129                                      std::unique_ptr<MCObjectWriter> &&OW,
130                                      std::unique_ptr<MCCodeEmitter> &&CE);
131 
132 MCStreamer *createX86ELFStreamer(const Triple &T, MCContext &Context,
133                                  std::unique_ptr<MCAsmBackend> &&MAB,
134                                  std::unique_ptr<MCObjectWriter> &&MOW,
135                                  std::unique_ptr<MCCodeEmitter> &&MCE);
136 
137 /// Construct an X86 Mach-O object writer.
138 std::unique_ptr<MCObjectTargetWriter>
139 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype);
140 
141 /// Construct an X86 ELF object writer.
142 std::unique_ptr<MCObjectTargetWriter>
143 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine);
144 /// Construct an X86 Win COFF object writer.
145 std::unique_ptr<MCObjectTargetWriter>
146 createX86WinCOFFObjectWriter(bool Is64Bit);
147 
148 /// \param Reg speicifed register.
149 /// \param Size the bit size of returned register.
150 /// \param High requires the high register.
151 ///
152 /// \returns the sub or super register of a specific X86 register.
153 MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size,
154                                   bool High = false);
155 } // End llvm namespace
156 
157 
158 // Defines symbolic names for X86 registers.  This defines a mapping from
159 // register name to register number.
160 //
161 #define GET_REGINFO_ENUM
162 #include "X86GenRegisterInfo.inc"
163 
164 // Defines symbolic names for the X86 instructions.
165 //
166 #define GET_INSTRINFO_ENUM
167 #define GET_INSTRINFO_MC_HELPER_DECLS
168 #include "X86GenInstrInfo.inc"
169 
170 #define GET_SUBTARGETINFO_ENUM
171 #include "X86GenSubtargetInfo.inc"
172 
173 #define GET_X86_MNEMONIC_TABLES_H
174 #include "X86GenMnemonicTables.inc"
175 
176 #endif
177