1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 15 16 #include <memory> 17 #include <string> 18 19 namespace llvm { 20 class formatted_raw_ostream; 21 class MCAsmBackend; 22 class MCCodeEmitter; 23 class MCContext; 24 class MCInst; 25 class MCInstPrinter; 26 class MCInstrInfo; 27 class MCObjectTargetWriter; 28 class MCObjectWriter; 29 class MCRegister; 30 class MCRegisterInfo; 31 class MCStreamer; 32 class MCSubtargetInfo; 33 class MCTargetOptions; 34 class MCTargetStreamer; 35 class Target; 36 class Triple; 37 class StringRef; 38 39 /// Flavour of dwarf regnumbers 40 /// 41 namespace DWARFFlavour { 42 enum { 43 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 44 }; 45 } 46 47 /// Native X86 register numbers 48 /// 49 namespace N86 { 50 enum { 51 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 52 }; 53 } 54 55 namespace X86_MC { 56 std::string ParseX86Triple(const Triple &TT); 57 58 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); 59 60 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); 61 62 63 /// Returns true if this instruction has a LOCK prefix. 64 bool hasLockPrefix(const MCInst &MI); 65 66 /// \param Op operand # of the memory operand. 67 /// 68 /// \returns true if the specified instruction has a 16-bit memory operand. 69 bool is16BitMemOperand(const MCInst &MI, unsigned Op, 70 const MCSubtargetInfo &STI); 71 72 /// \param Op operand # of the memory operand. 73 /// 74 /// \returns true if the specified instruction has a 32-bit memory operand. 75 bool is32BitMemOperand(const MCInst &MI, unsigned Op); 76 77 /// \param Op operand # of the memory operand. 78 /// 79 /// \returns true if the specified instruction has a 64-bit memory operand. 80 #ifndef NDEBUG 81 bool is64BitMemOperand(const MCInst &MI, unsigned Op); 82 #endif 83 84 /// Returns true if this instruction needs an Address-Size override prefix. 85 bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, 86 int MemoryOperand, uint64_t TSFlags); 87 88 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. 89 /// do not need to go through TargetRegistry. 90 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, 91 StringRef FS); 92 } 93 94 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 95 MCContext &Ctx); 96 97 MCAsmBackend *createX86_32AsmBackend(const Target &T, 98 const MCSubtargetInfo &STI, 99 const MCRegisterInfo &MRI, 100 const MCTargetOptions &Options); 101 MCAsmBackend *createX86_64AsmBackend(const Target &T, 102 const MCSubtargetInfo &STI, 103 const MCRegisterInfo &MRI, 104 const MCTargetOptions &Options); 105 106 /// Implements X86-only directives for assembly emission. 107 MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S, 108 formatted_raw_ostream &OS, 109 MCInstPrinter *InstPrinter, 110 bool IsVerboseAsm); 111 112 /// Implements X86-only directives for object files. 113 MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &S, 114 const MCSubtargetInfo &STI); 115 116 /// Construct an X86 Windows COFF machine code streamer which will generate 117 /// PE/COFF format object files. 118 /// 119 /// Takes ownership of \p AB and \p CE. 120 MCStreamer *createX86WinCOFFStreamer(MCContext &C, 121 std::unique_ptr<MCAsmBackend> &&AB, 122 std::unique_ptr<MCObjectWriter> &&OW, 123 std::unique_ptr<MCCodeEmitter> &&CE, 124 bool RelaxAll, 125 bool IncrementalLinkerCompatible); 126 127 /// Construct an X86 Mach-O object writer. 128 std::unique_ptr<MCObjectTargetWriter> 129 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); 130 131 /// Construct an X86 ELF object writer. 132 std::unique_ptr<MCObjectTargetWriter> 133 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine); 134 /// Construct an X86 Win COFF object writer. 135 std::unique_ptr<MCObjectTargetWriter> 136 createX86WinCOFFObjectWriter(bool Is64Bit); 137 138 /// Returns the sub or super register of a specific X86 register. 139 /// e.g. getX86SubSuperRegister(X86::EAX, 16) returns X86::AX. 140 /// Aborts on error. 141 MCRegister getX86SubSuperRegister(MCRegister, unsigned, bool High=false); 142 143 /// Returns the sub or super register of a specific X86 register. 144 /// Like getX86SubSuperRegister() but returns 0 on error. 145 MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, 146 bool High = false); 147 148 } // End llvm namespace 149 150 151 // Defines symbolic names for X86 registers. This defines a mapping from 152 // register name to register number. 153 // 154 #define GET_REGINFO_ENUM 155 #include "X86GenRegisterInfo.inc" 156 157 // Defines symbolic names for the X86 instructions. 158 // 159 #define GET_INSTRINFO_ENUM 160 #define GET_INSTRINFO_MC_HELPER_DECLS 161 #include "X86GenInstrInfo.inc" 162 163 #define GET_SUBTARGETINFO_ENUM 164 #include "X86GenSubtargetInfo.inc" 165 166 #define GET_X86_MNEMONIC_TABLES_H 167 #include "X86GenMnemonicTables.inc" 168 169 #endif 170