1 //===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86MCTargetDesc.h" 14 #include "TargetInfo/X86TargetInfo.h" 15 #include "X86ATTInstPrinter.h" 16 #include "X86BaseInfo.h" 17 #include "X86IntelInstPrinter.h" 18 #include "X86MCAsmInfo.h" 19 #include "llvm/ADT/APInt.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/DebugInfo/CodeView/CodeView.h" 22 #include "llvm/MC/MCDwarf.h" 23 #include "llvm/MC/MCInstrAnalysis.h" 24 #include "llvm/MC/MCInstrInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/MC/MCStreamer.h" 27 #include "llvm/MC/MCSubtargetInfo.h" 28 #include "llvm/MC/MachineLocation.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/Host.h" 31 #include "llvm/Support/TargetRegistry.h" 32 33 using namespace llvm; 34 35 #define GET_REGINFO_MC_DESC 36 #include "X86GenRegisterInfo.inc" 37 38 #define GET_INSTRINFO_MC_DESC 39 #define GET_INSTRINFO_MC_HELPERS 40 #include "X86GenInstrInfo.inc" 41 42 #define GET_SUBTARGETINFO_MC_DESC 43 #include "X86GenSubtargetInfo.inc" 44 45 std::string X86_MC::ParseX86Triple(const Triple &TT) { 46 std::string FS; 47 if (TT.getArch() == Triple::x86_64) 48 FS = "+64bit-mode,-32bit-mode,-16bit-mode"; 49 else if (TT.getEnvironment() != Triple::CODE16) 50 FS = "-64bit-mode,+32bit-mode,-16bit-mode"; 51 else 52 FS = "-64bit-mode,-32bit-mode,+16bit-mode"; 53 54 return FS; 55 } 56 57 unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) { 58 if (TT.getArch() == Triple::x86_64) 59 return DWARFFlavour::X86_64; 60 61 if (TT.isOSDarwin()) 62 return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic; 63 if (TT.isOSCygMing()) 64 // Unsupported by now, just quick fallback 65 return DWARFFlavour::X86_32_Generic; 66 return DWARFFlavour::X86_32_Generic; 67 } 68 69 bool X86_MC::hasLockPrefix(const MCInst &MI) { 70 return MI.getFlags() & X86::IP_HAS_LOCK; 71 } 72 73 void X86_MC::initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI) { 74 // FIXME: TableGen these. 75 for (unsigned Reg = X86::NoRegister + 1; Reg < X86::NUM_TARGET_REGS; ++Reg) { 76 unsigned SEH = MRI->getEncodingValue(Reg); 77 MRI->mapLLVMRegToSEHReg(Reg, SEH); 78 } 79 80 // Mapping from CodeView to MC register id. 81 static const struct { 82 codeview::RegisterId CVReg; 83 MCPhysReg Reg; 84 } RegMap[] = { 85 {codeview::RegisterId::AL, X86::AL}, 86 {codeview::RegisterId::CL, X86::CL}, 87 {codeview::RegisterId::DL, X86::DL}, 88 {codeview::RegisterId::BL, X86::BL}, 89 {codeview::RegisterId::AH, X86::AH}, 90 {codeview::RegisterId::CH, X86::CH}, 91 {codeview::RegisterId::DH, X86::DH}, 92 {codeview::RegisterId::BH, X86::BH}, 93 {codeview::RegisterId::AX, X86::AX}, 94 {codeview::RegisterId::CX, X86::CX}, 95 {codeview::RegisterId::DX, X86::DX}, 96 {codeview::RegisterId::BX, X86::BX}, 97 {codeview::RegisterId::SP, X86::SP}, 98 {codeview::RegisterId::BP, X86::BP}, 99 {codeview::RegisterId::SI, X86::SI}, 100 {codeview::RegisterId::DI, X86::DI}, 101 {codeview::RegisterId::EAX, X86::EAX}, 102 {codeview::RegisterId::ECX, X86::ECX}, 103 {codeview::RegisterId::EDX, X86::EDX}, 104 {codeview::RegisterId::EBX, X86::EBX}, 105 {codeview::RegisterId::ESP, X86::ESP}, 106 {codeview::RegisterId::EBP, X86::EBP}, 107 {codeview::RegisterId::ESI, X86::ESI}, 108 {codeview::RegisterId::EDI, X86::EDI}, 109 110 {codeview::RegisterId::EFLAGS, X86::EFLAGS}, 111 112 {codeview::RegisterId::ST0, X86::FP0}, 113 {codeview::RegisterId::ST1, X86::FP1}, 114 {codeview::RegisterId::ST2, X86::FP2}, 115 {codeview::RegisterId::ST3, X86::FP3}, 116 {codeview::RegisterId::ST4, X86::FP4}, 117 {codeview::RegisterId::ST5, X86::FP5}, 118 {codeview::RegisterId::ST6, X86::FP6}, 119 {codeview::RegisterId::ST7, X86::FP7}, 120 121 {codeview::RegisterId::MM0, X86::MM0}, 122 {codeview::RegisterId::MM1, X86::MM1}, 123 {codeview::RegisterId::MM2, X86::MM2}, 124 {codeview::RegisterId::MM3, X86::MM3}, 125 {codeview::RegisterId::MM4, X86::MM4}, 126 {codeview::RegisterId::MM5, X86::MM5}, 127 {codeview::RegisterId::MM6, X86::MM6}, 128 {codeview::RegisterId::MM7, X86::MM7}, 129 130 {codeview::RegisterId::XMM0, X86::XMM0}, 131 {codeview::RegisterId::XMM1, X86::XMM1}, 132 {codeview::RegisterId::XMM2, X86::XMM2}, 133 {codeview::RegisterId::XMM3, X86::XMM3}, 134 {codeview::RegisterId::XMM4, X86::XMM4}, 135 {codeview::RegisterId::XMM5, X86::XMM5}, 136 {codeview::RegisterId::XMM6, X86::XMM6}, 137 {codeview::RegisterId::XMM7, X86::XMM7}, 138 139 {codeview::RegisterId::XMM8, X86::XMM8}, 140 {codeview::RegisterId::XMM9, X86::XMM9}, 141 {codeview::RegisterId::XMM10, X86::XMM10}, 142 {codeview::RegisterId::XMM11, X86::XMM11}, 143 {codeview::RegisterId::XMM12, X86::XMM12}, 144 {codeview::RegisterId::XMM13, X86::XMM13}, 145 {codeview::RegisterId::XMM14, X86::XMM14}, 146 {codeview::RegisterId::XMM15, X86::XMM15}, 147 148 {codeview::RegisterId::SIL, X86::SIL}, 149 {codeview::RegisterId::DIL, X86::DIL}, 150 {codeview::RegisterId::BPL, X86::BPL}, 151 {codeview::RegisterId::SPL, X86::SPL}, 152 {codeview::RegisterId::RAX, X86::RAX}, 153 {codeview::RegisterId::RBX, X86::RBX}, 154 {codeview::RegisterId::RCX, X86::RCX}, 155 {codeview::RegisterId::RDX, X86::RDX}, 156 {codeview::RegisterId::RSI, X86::RSI}, 157 {codeview::RegisterId::RDI, X86::RDI}, 158 {codeview::RegisterId::RBP, X86::RBP}, 159 {codeview::RegisterId::RSP, X86::RSP}, 160 {codeview::RegisterId::R8, X86::R8}, 161 {codeview::RegisterId::R9, X86::R9}, 162 {codeview::RegisterId::R10, X86::R10}, 163 {codeview::RegisterId::R11, X86::R11}, 164 {codeview::RegisterId::R12, X86::R12}, 165 {codeview::RegisterId::R13, X86::R13}, 166 {codeview::RegisterId::R14, X86::R14}, 167 {codeview::RegisterId::R15, X86::R15}, 168 {codeview::RegisterId::R8B, X86::R8B}, 169 {codeview::RegisterId::R9B, X86::R9B}, 170 {codeview::RegisterId::R10B, X86::R10B}, 171 {codeview::RegisterId::R11B, X86::R11B}, 172 {codeview::RegisterId::R12B, X86::R12B}, 173 {codeview::RegisterId::R13B, X86::R13B}, 174 {codeview::RegisterId::R14B, X86::R14B}, 175 {codeview::RegisterId::R15B, X86::R15B}, 176 {codeview::RegisterId::R8W, X86::R8W}, 177 {codeview::RegisterId::R9W, X86::R9W}, 178 {codeview::RegisterId::R10W, X86::R10W}, 179 {codeview::RegisterId::R11W, X86::R11W}, 180 {codeview::RegisterId::R12W, X86::R12W}, 181 {codeview::RegisterId::R13W, X86::R13W}, 182 {codeview::RegisterId::R14W, X86::R14W}, 183 {codeview::RegisterId::R15W, X86::R15W}, 184 {codeview::RegisterId::R8D, X86::R8D}, 185 {codeview::RegisterId::R9D, X86::R9D}, 186 {codeview::RegisterId::R10D, X86::R10D}, 187 {codeview::RegisterId::R11D, X86::R11D}, 188 {codeview::RegisterId::R12D, X86::R12D}, 189 {codeview::RegisterId::R13D, X86::R13D}, 190 {codeview::RegisterId::R14D, X86::R14D}, 191 {codeview::RegisterId::R15D, X86::R15D}, 192 {codeview::RegisterId::AMD64_YMM0, X86::YMM0}, 193 {codeview::RegisterId::AMD64_YMM1, X86::YMM1}, 194 {codeview::RegisterId::AMD64_YMM2, X86::YMM2}, 195 {codeview::RegisterId::AMD64_YMM3, X86::YMM3}, 196 {codeview::RegisterId::AMD64_YMM4, X86::YMM4}, 197 {codeview::RegisterId::AMD64_YMM5, X86::YMM5}, 198 {codeview::RegisterId::AMD64_YMM6, X86::YMM6}, 199 {codeview::RegisterId::AMD64_YMM7, X86::YMM7}, 200 {codeview::RegisterId::AMD64_YMM8, X86::YMM8}, 201 {codeview::RegisterId::AMD64_YMM9, X86::YMM9}, 202 {codeview::RegisterId::AMD64_YMM10, X86::YMM10}, 203 {codeview::RegisterId::AMD64_YMM11, X86::YMM11}, 204 {codeview::RegisterId::AMD64_YMM12, X86::YMM12}, 205 {codeview::RegisterId::AMD64_YMM13, X86::YMM13}, 206 {codeview::RegisterId::AMD64_YMM14, X86::YMM14}, 207 {codeview::RegisterId::AMD64_YMM15, X86::YMM15}, 208 {codeview::RegisterId::AMD64_YMM16, X86::YMM16}, 209 {codeview::RegisterId::AMD64_YMM17, X86::YMM17}, 210 {codeview::RegisterId::AMD64_YMM18, X86::YMM18}, 211 {codeview::RegisterId::AMD64_YMM19, X86::YMM19}, 212 {codeview::RegisterId::AMD64_YMM20, X86::YMM20}, 213 {codeview::RegisterId::AMD64_YMM21, X86::YMM21}, 214 {codeview::RegisterId::AMD64_YMM22, X86::YMM22}, 215 {codeview::RegisterId::AMD64_YMM23, X86::YMM23}, 216 {codeview::RegisterId::AMD64_YMM24, X86::YMM24}, 217 {codeview::RegisterId::AMD64_YMM25, X86::YMM25}, 218 {codeview::RegisterId::AMD64_YMM26, X86::YMM26}, 219 {codeview::RegisterId::AMD64_YMM27, X86::YMM27}, 220 {codeview::RegisterId::AMD64_YMM28, X86::YMM28}, 221 {codeview::RegisterId::AMD64_YMM29, X86::YMM29}, 222 {codeview::RegisterId::AMD64_YMM30, X86::YMM30}, 223 {codeview::RegisterId::AMD64_YMM31, X86::YMM31}, 224 {codeview::RegisterId::AMD64_ZMM0, X86::ZMM0}, 225 {codeview::RegisterId::AMD64_ZMM1, X86::ZMM1}, 226 {codeview::RegisterId::AMD64_ZMM2, X86::ZMM2}, 227 {codeview::RegisterId::AMD64_ZMM3, X86::ZMM3}, 228 {codeview::RegisterId::AMD64_ZMM4, X86::ZMM4}, 229 {codeview::RegisterId::AMD64_ZMM5, X86::ZMM5}, 230 {codeview::RegisterId::AMD64_ZMM6, X86::ZMM6}, 231 {codeview::RegisterId::AMD64_ZMM7, X86::ZMM7}, 232 {codeview::RegisterId::AMD64_ZMM8, X86::ZMM8}, 233 {codeview::RegisterId::AMD64_ZMM9, X86::ZMM9}, 234 {codeview::RegisterId::AMD64_ZMM10, X86::ZMM10}, 235 {codeview::RegisterId::AMD64_ZMM11, X86::ZMM11}, 236 {codeview::RegisterId::AMD64_ZMM12, X86::ZMM12}, 237 {codeview::RegisterId::AMD64_ZMM13, X86::ZMM13}, 238 {codeview::RegisterId::AMD64_ZMM14, X86::ZMM14}, 239 {codeview::RegisterId::AMD64_ZMM15, X86::ZMM15}, 240 {codeview::RegisterId::AMD64_ZMM16, X86::ZMM16}, 241 {codeview::RegisterId::AMD64_ZMM17, X86::ZMM17}, 242 {codeview::RegisterId::AMD64_ZMM18, X86::ZMM18}, 243 {codeview::RegisterId::AMD64_ZMM19, X86::ZMM19}, 244 {codeview::RegisterId::AMD64_ZMM20, X86::ZMM20}, 245 {codeview::RegisterId::AMD64_ZMM21, X86::ZMM21}, 246 {codeview::RegisterId::AMD64_ZMM22, X86::ZMM22}, 247 {codeview::RegisterId::AMD64_ZMM23, X86::ZMM23}, 248 {codeview::RegisterId::AMD64_ZMM24, X86::ZMM24}, 249 {codeview::RegisterId::AMD64_ZMM25, X86::ZMM25}, 250 {codeview::RegisterId::AMD64_ZMM26, X86::ZMM26}, 251 {codeview::RegisterId::AMD64_ZMM27, X86::ZMM27}, 252 {codeview::RegisterId::AMD64_ZMM28, X86::ZMM28}, 253 {codeview::RegisterId::AMD64_ZMM29, X86::ZMM29}, 254 {codeview::RegisterId::AMD64_ZMM30, X86::ZMM30}, 255 {codeview::RegisterId::AMD64_ZMM31, X86::ZMM31}, 256 {codeview::RegisterId::AMD64_K0, X86::K0}, 257 {codeview::RegisterId::AMD64_K1, X86::K1}, 258 {codeview::RegisterId::AMD64_K2, X86::K2}, 259 {codeview::RegisterId::AMD64_K3, X86::K3}, 260 {codeview::RegisterId::AMD64_K4, X86::K4}, 261 {codeview::RegisterId::AMD64_K5, X86::K5}, 262 {codeview::RegisterId::AMD64_K6, X86::K6}, 263 {codeview::RegisterId::AMD64_K7, X86::K7}, 264 {codeview::RegisterId::AMD64_XMM16, X86::XMM16}, 265 {codeview::RegisterId::AMD64_XMM17, X86::XMM17}, 266 {codeview::RegisterId::AMD64_XMM18, X86::XMM18}, 267 {codeview::RegisterId::AMD64_XMM19, X86::XMM19}, 268 {codeview::RegisterId::AMD64_XMM20, X86::XMM20}, 269 {codeview::RegisterId::AMD64_XMM21, X86::XMM21}, 270 {codeview::RegisterId::AMD64_XMM22, X86::XMM22}, 271 {codeview::RegisterId::AMD64_XMM23, X86::XMM23}, 272 {codeview::RegisterId::AMD64_XMM24, X86::XMM24}, 273 {codeview::RegisterId::AMD64_XMM25, X86::XMM25}, 274 {codeview::RegisterId::AMD64_XMM26, X86::XMM26}, 275 {codeview::RegisterId::AMD64_XMM27, X86::XMM27}, 276 {codeview::RegisterId::AMD64_XMM28, X86::XMM28}, 277 {codeview::RegisterId::AMD64_XMM29, X86::XMM29}, 278 {codeview::RegisterId::AMD64_XMM30, X86::XMM30}, 279 {codeview::RegisterId::AMD64_XMM31, X86::XMM31}, 280 281 }; 282 for (unsigned I = 0; I < array_lengthof(RegMap); ++I) 283 MRI->mapLLVMRegToCVReg(RegMap[I].Reg, static_cast<int>(RegMap[I].CVReg)); 284 } 285 286 MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT, 287 StringRef CPU, StringRef FS) { 288 std::string ArchFS = X86_MC::ParseX86Triple(TT); 289 assert(!ArchFS.empty() && "Failed to parse X86 triple"); 290 if (!FS.empty()) 291 ArchFS = (Twine(ArchFS) + "," + FS).str(); 292 293 std::string CPUName = std::string(CPU); 294 if (CPUName.empty()) 295 CPUName = "generic"; 296 297 return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS); 298 } 299 300 static MCInstrInfo *createX86MCInstrInfo() { 301 MCInstrInfo *X = new MCInstrInfo(); 302 InitX86MCInstrInfo(X); 303 return X; 304 } 305 306 static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) { 307 unsigned RA = (TT.getArch() == Triple::x86_64) 308 ? X86::RIP // Should have dwarf #16. 309 : X86::EIP; // Should have dwarf #8. 310 311 MCRegisterInfo *X = new MCRegisterInfo(); 312 InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false), 313 X86_MC::getDwarfRegFlavour(TT, true), RA); 314 X86_MC::initLLVMToSEHAndCVRegMapping(X); 315 return X; 316 } 317 318 static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, 319 const Triple &TheTriple, 320 const MCTargetOptions &Options) { 321 bool is64Bit = TheTriple.getArch() == Triple::x86_64; 322 323 MCAsmInfo *MAI; 324 if (TheTriple.isOSBinFormatMachO()) { 325 if (is64Bit) 326 MAI = new X86_64MCAsmInfoDarwin(TheTriple); 327 else 328 MAI = new X86MCAsmInfoDarwin(TheTriple); 329 } else if (TheTriple.isOSBinFormatELF()) { 330 // Force the use of an ELF container. 331 MAI = new X86ELFMCAsmInfo(TheTriple); 332 } else if (TheTriple.isWindowsMSVCEnvironment() || 333 TheTriple.isWindowsCoreCLREnvironment()) { 334 if (Options.getAssemblyLanguage().equals_lower("masm")) 335 MAI = new X86MCAsmInfoMicrosoftMASM(TheTriple); 336 else 337 MAI = new X86MCAsmInfoMicrosoft(TheTriple); 338 } else if (TheTriple.isOSCygMing() || 339 TheTriple.isWindowsItaniumEnvironment()) { 340 MAI = new X86MCAsmInfoGNUCOFF(TheTriple); 341 } else { 342 // The default is ELF. 343 MAI = new X86ELFMCAsmInfo(TheTriple); 344 } 345 346 // Initialize initial frame state. 347 // Calculate amount of bytes used for return address storing 348 int stackGrowth = is64Bit ? -8 : -4; 349 350 // Initial state of the frame pointer is esp+stackGrowth. 351 unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP; 352 MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( 353 nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth); 354 MAI->addInitialFrameState(Inst); 355 356 // Add return address to move list 357 unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP; 358 MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( 359 nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth); 360 MAI->addInitialFrameState(Inst2); 361 362 return MAI; 363 } 364 365 static MCInstPrinter *createX86MCInstPrinter(const Triple &T, 366 unsigned SyntaxVariant, 367 const MCAsmInfo &MAI, 368 const MCInstrInfo &MII, 369 const MCRegisterInfo &MRI) { 370 if (SyntaxVariant == 0) 371 return new X86ATTInstPrinter(MAI, MII, MRI); 372 if (SyntaxVariant == 1) 373 return new X86IntelInstPrinter(MAI, MII, MRI); 374 return nullptr; 375 } 376 377 static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple, 378 MCContext &Ctx) { 379 // Default to the stock relocation info. 380 return llvm::createMCRelocationInfo(TheTriple, Ctx); 381 } 382 383 namespace llvm { 384 namespace X86_MC { 385 386 class X86MCInstrAnalysis : public MCInstrAnalysis { 387 X86MCInstrAnalysis(const X86MCInstrAnalysis &) = delete; 388 X86MCInstrAnalysis &operator=(const X86MCInstrAnalysis &) = delete; 389 virtual ~X86MCInstrAnalysis() = default; 390 391 public: 392 X86MCInstrAnalysis(const MCInstrInfo *MCII) : MCInstrAnalysis(MCII) {} 393 394 #define GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS 395 #include "X86GenSubtargetInfo.inc" 396 397 bool clearsSuperRegisters(const MCRegisterInfo &MRI, const MCInst &Inst, 398 APInt &Mask) const override; 399 std::vector<std::pair<uint64_t, uint64_t>> 400 findPltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 401 uint64_t GotSectionVA, 402 const Triple &TargetTriple) const override; 403 404 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, uint64_t Size, 405 uint64_t &Target) const override; 406 Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst, 407 uint64_t Addr, 408 uint64_t Size) const override; 409 }; 410 411 #define GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS 412 #include "X86GenSubtargetInfo.inc" 413 414 bool X86MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI, 415 const MCInst &Inst, 416 APInt &Mask) const { 417 const MCInstrDesc &Desc = Info->get(Inst.getOpcode()); 418 unsigned NumDefs = Desc.getNumDefs(); 419 unsigned NumImplicitDefs = Desc.getNumImplicitDefs(); 420 assert(Mask.getBitWidth() == NumDefs + NumImplicitDefs && 421 "Unexpected number of bits in the mask!"); 422 423 bool HasVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::VEX; 424 bool HasEVEX = (Desc.TSFlags & X86II::EncodingMask) == X86II::EVEX; 425 bool HasXOP = (Desc.TSFlags & X86II::EncodingMask) == X86II::XOP; 426 427 const MCRegisterClass &GR32RC = MRI.getRegClass(X86::GR32RegClassID); 428 const MCRegisterClass &VR128XRC = MRI.getRegClass(X86::VR128XRegClassID); 429 const MCRegisterClass &VR256XRC = MRI.getRegClass(X86::VR256XRegClassID); 430 431 auto ClearsSuperReg = [=](unsigned RegID) { 432 // On X86-64, a general purpose integer register is viewed as a 64-bit 433 // register internal to the processor. 434 // An update to the lower 32 bits of a 64 bit integer register is 435 // architecturally defined to zero extend the upper 32 bits. 436 if (GR32RC.contains(RegID)) 437 return true; 438 439 // Early exit if this instruction has no vex/evex/xop prefix. 440 if (!HasEVEX && !HasVEX && !HasXOP) 441 return false; 442 443 // All VEX and EVEX encoded instructions are defined to zero the high bits 444 // of the destination register up to VLMAX (i.e. the maximum vector register 445 // width pertaining to the instruction). 446 // We assume the same behavior for XOP instructions too. 447 return VR128XRC.contains(RegID) || VR256XRC.contains(RegID); 448 }; 449 450 Mask.clearAllBits(); 451 for (unsigned I = 0, E = NumDefs; I < E; ++I) { 452 const MCOperand &Op = Inst.getOperand(I); 453 if (ClearsSuperReg(Op.getReg())) 454 Mask.setBit(I); 455 } 456 457 for (unsigned I = 0, E = NumImplicitDefs; I < E; ++I) { 458 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; 459 if (ClearsSuperReg(Reg)) 460 Mask.setBit(NumDefs + I); 461 } 462 463 return Mask.getBoolValue(); 464 } 465 466 static std::vector<std::pair<uint64_t, uint64_t>> 467 findX86PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 468 uint64_t GotPltSectionVA) { 469 // Do a lightweight parsing of PLT entries. 470 std::vector<std::pair<uint64_t, uint64_t>> Result; 471 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 472 // Recognize a jmp. 473 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0xa3) { 474 // The jmp instruction at the beginning of each PLT entry jumps to the 475 // address of the base of the .got.plt section plus the immediate. 476 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 477 Result.push_back( 478 std::make_pair(PltSectionVA + Byte, GotPltSectionVA + Imm)); 479 Byte += 6; 480 } else if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 481 // The jmp instruction at the beginning of each PLT entry jumps to the 482 // immediate. 483 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 484 Result.push_back(std::make_pair(PltSectionVA + Byte, Imm)); 485 Byte += 6; 486 } else 487 Byte++; 488 } 489 return Result; 490 } 491 492 static std::vector<std::pair<uint64_t, uint64_t>> 493 findX86_64PltEntries(uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents) { 494 // Do a lightweight parsing of PLT entries. 495 std::vector<std::pair<uint64_t, uint64_t>> Result; 496 for (uint64_t Byte = 0, End = PltContents.size(); Byte + 6 < End; ) { 497 // Recognize a jmp. 498 if (PltContents[Byte] == 0xff && PltContents[Byte + 1] == 0x25) { 499 // The jmp instruction at the beginning of each PLT entry jumps to the 500 // address of the next instruction plus the immediate. 501 uint32_t Imm = support::endian::read32le(PltContents.data() + Byte + 2); 502 Result.push_back( 503 std::make_pair(PltSectionVA + Byte, PltSectionVA + Byte + 6 + Imm)); 504 Byte += 6; 505 } else 506 Byte++; 507 } 508 return Result; 509 } 510 511 std::vector<std::pair<uint64_t, uint64_t>> X86MCInstrAnalysis::findPltEntries( 512 uint64_t PltSectionVA, ArrayRef<uint8_t> PltContents, 513 uint64_t GotPltSectionVA, const Triple &TargetTriple) const { 514 switch (TargetTriple.getArch()) { 515 case Triple::x86: 516 return findX86PltEntries(PltSectionVA, PltContents, GotPltSectionVA); 517 case Triple::x86_64: 518 return findX86_64PltEntries(PltSectionVA, PltContents); 519 default: 520 return {}; 521 } 522 } 523 524 bool X86MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr, 525 uint64_t Size, uint64_t &Target) const { 526 if (Inst.getNumOperands() == 0 || 527 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL) 528 return false; 529 Target = Addr + Size + Inst.getOperand(0).getImm(); 530 return true; 531 } 532 533 Optional<uint64_t> X86MCInstrAnalysis::evaluateMemoryOperandAddress( 534 const MCInst &Inst, uint64_t Addr, uint64_t Size) const { 535 const MCInstrDesc &MCID = Info->get(Inst.getOpcode()); 536 int MemOpStart = X86II::getMemoryOperandNo(MCID.TSFlags); 537 if (MemOpStart == -1) 538 return None; 539 MemOpStart += X86II::getOperandBias(MCID); 540 541 const MCOperand &SegReg = Inst.getOperand(MemOpStart + X86::AddrSegmentReg); 542 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); 543 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); 544 const MCOperand &ScaleAmt = Inst.getOperand(MemOpStart + X86::AddrScaleAmt); 545 const MCOperand &Disp = Inst.getOperand(MemOpStart + X86::AddrDisp); 546 if (SegReg.getReg() != 0 || IndexReg.getReg() != 0 || ScaleAmt.getImm() != 1 || 547 !Disp.isImm()) 548 return None; 549 550 // RIP-relative addressing. 551 if (BaseReg.getReg() == X86::RIP) 552 return Addr + Size + Disp.getImm(); 553 554 return None; 555 } 556 557 } // end of namespace X86_MC 558 559 } // end of namespace llvm 560 561 static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { 562 return new X86_MC::X86MCInstrAnalysis(Info); 563 } 564 565 // Force static initialization. 566 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86TargetMC() { 567 for (Target *T : {&getTheX86_32Target(), &getTheX86_64Target()}) { 568 // Register the MC asm info. 569 RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); 570 571 // Register the MC instruction info. 572 TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo); 573 574 // Register the MC register info. 575 TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo); 576 577 // Register the MC subtarget info. 578 TargetRegistry::RegisterMCSubtargetInfo(*T, 579 X86_MC::createX86MCSubtargetInfo); 580 581 // Register the MC instruction analyzer. 582 TargetRegistry::RegisterMCInstrAnalysis(*T, createX86MCInstrAnalysis); 583 584 // Register the code emitter. 585 TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter); 586 587 // Register the obj target streamer. 588 TargetRegistry::RegisterObjectTargetStreamer(*T, 589 createX86ObjectTargetStreamer); 590 591 // Register the asm target streamer. 592 TargetRegistry::RegisterAsmTargetStreamer(*T, createX86AsmTargetStreamer); 593 594 TargetRegistry::RegisterCOFFStreamer(*T, createX86WinCOFFStreamer); 595 596 // Register the MCInstPrinter. 597 TargetRegistry::RegisterMCInstPrinter(*T, createX86MCInstPrinter); 598 599 // Register the MC relocation info. 600 TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo); 601 } 602 603 // Register the asm backend. 604 TargetRegistry::RegisterMCAsmBackend(getTheX86_32Target(), 605 createX86_32AsmBackend); 606 TargetRegistry::RegisterMCAsmBackend(getTheX86_64Target(), 607 createX86_64AsmBackend); 608 } 609 610 MCRegister llvm::getX86SubSuperRegisterOrZero(MCRegister Reg, unsigned Size, 611 bool High) { 612 switch (Size) { 613 default: return X86::NoRegister; 614 case 8: 615 if (High) { 616 switch (Reg.id()) { 617 default: return getX86SubSuperRegisterOrZero(Reg, 64); 618 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 619 return X86::SI; 620 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 621 return X86::DI; 622 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 623 return X86::BP; 624 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 625 return X86::SP; 626 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 627 return X86::AH; 628 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 629 return X86::DH; 630 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 631 return X86::CH; 632 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 633 return X86::BH; 634 } 635 } else { 636 switch (Reg.id()) { 637 default: return X86::NoRegister; 638 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 639 return X86::AL; 640 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 641 return X86::DL; 642 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 643 return X86::CL; 644 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 645 return X86::BL; 646 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 647 return X86::SIL; 648 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 649 return X86::DIL; 650 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 651 return X86::BPL; 652 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 653 return X86::SPL; 654 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 655 return X86::R8B; 656 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 657 return X86::R9B; 658 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 659 return X86::R10B; 660 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 661 return X86::R11B; 662 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 663 return X86::R12B; 664 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 665 return X86::R13B; 666 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 667 return X86::R14B; 668 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 669 return X86::R15B; 670 } 671 } 672 case 16: 673 switch (Reg.id()) { 674 default: return X86::NoRegister; 675 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 676 return X86::AX; 677 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 678 return X86::DX; 679 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 680 return X86::CX; 681 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 682 return X86::BX; 683 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 684 return X86::SI; 685 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 686 return X86::DI; 687 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 688 return X86::BP; 689 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 690 return X86::SP; 691 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 692 return X86::R8W; 693 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 694 return X86::R9W; 695 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 696 return X86::R10W; 697 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 698 return X86::R11W; 699 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 700 return X86::R12W; 701 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 702 return X86::R13W; 703 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 704 return X86::R14W; 705 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 706 return X86::R15W; 707 } 708 case 32: 709 switch (Reg.id()) { 710 default: return X86::NoRegister; 711 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 712 return X86::EAX; 713 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 714 return X86::EDX; 715 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 716 return X86::ECX; 717 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 718 return X86::EBX; 719 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 720 return X86::ESI; 721 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 722 return X86::EDI; 723 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 724 return X86::EBP; 725 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 726 return X86::ESP; 727 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 728 return X86::R8D; 729 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 730 return X86::R9D; 731 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 732 return X86::R10D; 733 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 734 return X86::R11D; 735 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 736 return X86::R12D; 737 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 738 return X86::R13D; 739 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 740 return X86::R14D; 741 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 742 return X86::R15D; 743 } 744 case 64: 745 switch (Reg.id()) { 746 default: return 0; 747 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 748 return X86::RAX; 749 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 750 return X86::RDX; 751 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 752 return X86::RCX; 753 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 754 return X86::RBX; 755 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 756 return X86::RSI; 757 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 758 return X86::RDI; 759 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 760 return X86::RBP; 761 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 762 return X86::RSP; 763 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 764 return X86::R8; 765 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 766 return X86::R9; 767 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 768 return X86::R10; 769 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 770 return X86::R11; 771 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 772 return X86::R12; 773 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 774 return X86::R13; 775 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 776 return X86::R14; 777 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 778 return X86::R15; 779 } 780 } 781 } 782 783 MCRegister llvm::getX86SubSuperRegister(MCRegister Reg, unsigned Size, bool High) { 784 MCRegister Res = getX86SubSuperRegisterOrZero(Reg, Size, High); 785 assert(Res != X86::NoRegister && "Unexpected register or VT"); 786 return Res; 787 } 788 789 790