1 //===-- X86MCCodeEmitter.cpp - Convert X86 code to machine code -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the X86MCCodeEmitter class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MCTargetDesc/X86BaseInfo.h" 14 #include "MCTargetDesc/X86FixupKinds.h" 15 #include "MCTargetDesc/X86MCTargetDesc.h" 16 #include "llvm/ADT/SmallVector.h" 17 #include "llvm/MC/MCCodeEmitter.h" 18 #include "llvm/MC/MCContext.h" 19 #include "llvm/MC/MCExpr.h" 20 #include "llvm/MC/MCFixup.h" 21 #include "llvm/MC/MCInst.h" 22 #include "llvm/MC/MCInstrDesc.h" 23 #include "llvm/MC/MCInstrInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbol.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <cassert> 30 #include <cstdint> 31 #include <cstdlib> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "mccodeemitter" 36 37 namespace { 38 39 class X86MCCodeEmitter : public MCCodeEmitter { 40 const MCInstrInfo &MCII; 41 MCContext &Ctx; 42 43 public: 44 X86MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) 45 : MCII(mcii), Ctx(ctx) {} 46 X86MCCodeEmitter(const X86MCCodeEmitter &) = delete; 47 X86MCCodeEmitter &operator=(const X86MCCodeEmitter &) = delete; 48 ~X86MCCodeEmitter() override = default; 49 50 void emitPrefix(const MCInst &MI, raw_ostream &OS, 51 const MCSubtargetInfo &STI) const override; 52 53 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 54 SmallVectorImpl<MCFixup> &Fixups, 55 const MCSubtargetInfo &STI) const override; 56 57 private: 58 unsigned getX86RegNum(const MCOperand &MO) const { 59 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; 60 } 61 62 unsigned getX86RegEncoding(const MCInst &MI, unsigned OpNum) const { 63 return Ctx.getRegisterInfo()->getEncodingValue( 64 MI.getOperand(OpNum).getReg()); 65 } 66 67 /// \param MI a single low-level machine instruction. 68 /// \param OpNum the operand #. 69 /// \returns true if the OpNumth operand of MI require a bit to be set in 70 /// REX prefix. 71 bool isREXExtendedReg(const MCInst &MI, unsigned OpNum) const { 72 return (getX86RegEncoding(MI, OpNum) >> 3) & 1; 73 } 74 75 void emitByte(uint8_t C, unsigned &CurByte, raw_ostream &OS) const { 76 OS << (char)C; 77 ++CurByte; 78 } 79 80 void emitConstant(uint64_t Val, unsigned Size, unsigned &CurByte, 81 raw_ostream &OS) const { 82 // Output the constant in little endian byte order. 83 for (unsigned i = 0; i != Size; ++i) { 84 emitByte(Val & 255, CurByte, OS); 85 Val >>= 8; 86 } 87 } 88 89 void emitImmediate(const MCOperand &Disp, SMLoc Loc, unsigned ImmSize, 90 MCFixupKind FixupKind, unsigned &CurByte, raw_ostream &OS, 91 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset = 0) const; 92 93 static uint8_t modRMByte(unsigned Mod, unsigned RegOpcode, unsigned RM) { 94 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!"); 95 return RM | (RegOpcode << 3) | (Mod << 6); 96 } 97 98 void emitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld, 99 unsigned &CurByte, raw_ostream &OS) const { 100 emitByte(modRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)), CurByte, OS); 101 } 102 103 void emitSIBByte(unsigned SS, unsigned Index, unsigned Base, 104 unsigned &CurByte, raw_ostream &OS) const { 105 // SIB byte is in the same format as the modRMByte. 106 emitByte(modRMByte(SS, Index, Base), CurByte, OS); 107 } 108 109 void emitMemModRMByte(const MCInst &MI, unsigned Op, unsigned RegOpcodeField, 110 uint64_t TSFlags, bool Rex, unsigned &CurByte, 111 raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, 112 const MCSubtargetInfo &STI) const; 113 114 void emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, unsigned &CurByte, 115 bool &Rex, const MCInst &MI, const MCInstrDesc &Desc, 116 const MCSubtargetInfo &STI, raw_ostream &OS) const; 117 118 void emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 119 const MCInst &MI, const MCInstrDesc &Desc, 120 raw_ostream &OS) const; 121 122 void emitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand, 123 const MCInst &MI, raw_ostream &OS) const; 124 125 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 126 const MCInst &MI, const MCInstrDesc &Desc, 127 const MCSubtargetInfo &STI, raw_ostream &OS) const; 128 129 uint8_t determineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand, 130 const MCInstrDesc &Desc) const; 131 }; 132 133 } // end anonymous namespace 134 135 /// \returns true if this signed displacement fits in a 8-bit sign-extended 136 /// field. 137 static bool isDisp8(int Value) { return Value == (int8_t)Value; } 138 139 /// \returns true if this signed displacement fits in a 8-bit compressed 140 /// dispacement field. 141 static bool isCDisp8(uint64_t TSFlags, int Value, int &CValue) { 142 assert(((TSFlags & X86II::EncodingMask) == X86II::EVEX) && 143 "Compressed 8-bit displacement is only valid for EVEX inst."); 144 145 unsigned CD8_Scale = 146 (TSFlags & X86II::CD8_Scale_Mask) >> X86II::CD8_Scale_Shift; 147 if (CD8_Scale == 0) { 148 CValue = Value; 149 return isDisp8(Value); 150 } 151 152 unsigned Mask = CD8_Scale - 1; 153 assert((CD8_Scale & Mask) == 0 && "Invalid memory object size."); 154 if (Value & Mask) // Unaligned offset 155 return false; 156 Value /= (int)CD8_Scale; 157 bool Ret = (Value == (int8_t)Value); 158 159 if (Ret) 160 CValue = Value; 161 return Ret; 162 } 163 164 /// \returns the appropriate fixup kind to use for an immediate in an 165 /// instruction with the specified TSFlags. 166 static MCFixupKind getImmFixupKind(uint64_t TSFlags) { 167 unsigned Size = X86II::getSizeOfImm(TSFlags); 168 bool isPCRel = X86II::isImmPCRel(TSFlags); 169 170 if (X86II::isImmSigned(TSFlags)) { 171 switch (Size) { 172 default: 173 llvm_unreachable("Unsupported signed fixup size!"); 174 case 4: 175 return MCFixupKind(X86::reloc_signed_4byte); 176 } 177 } 178 return MCFixup::getKindForSize(Size, isPCRel); 179 } 180 181 /// \param Op operand # of the memory operand. 182 /// 183 /// \returns true if the specified instruction has a 16-bit memory operand. 184 static bool is16BitMemOperand(const MCInst &MI, unsigned Op, 185 const MCSubtargetInfo &STI) { 186 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 187 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 188 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); 189 190 if (STI.hasFeature(X86::Mode16Bit) && BaseReg.getReg() == 0 && Disp.isImm() && 191 Disp.getImm() < 0x10000) 192 return true; 193 if ((BaseReg.getReg() != 0 && 194 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || 195 (IndexReg.getReg() != 0 && 196 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) 197 return true; 198 return false; 199 } 200 201 /// \param Op operand # of the memory operand. 202 /// 203 /// \returns true if the specified instruction has a 32-bit memory operand. 204 static bool is32BitMemOperand(const MCInst &MI, unsigned Op) { 205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 207 208 if ((BaseReg.getReg() != 0 && 209 X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg.getReg())) || 210 (IndexReg.getReg() != 0 && 211 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg.getReg()))) 212 return true; 213 if (BaseReg.getReg() == X86::EIP) { 214 assert(IndexReg.getReg() == 0 && "Invalid eip-based address."); 215 return true; 216 } 217 if (IndexReg.getReg() == X86::EIZ) 218 return true; 219 return false; 220 } 221 222 /// \param Op operand # of the memory operand. 223 /// 224 /// \returns true if the specified instruction has a 64-bit memory operand. 225 #ifndef NDEBUG 226 static bool is64BitMemOperand(const MCInst &MI, unsigned Op) { 227 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); 228 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 229 230 if ((BaseReg.getReg() != 0 && 231 X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg.getReg())) || 232 (IndexReg.getReg() != 0 && 233 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg.getReg()))) 234 return true; 235 return false; 236 } 237 #endif 238 239 enum GlobalOffsetTableExprKind { GOT_None, GOT_Normal, GOT_SymDiff }; 240 241 /// Check if this expression starts with _GLOBAL_OFFSET_TABLE_ and if it is 242 /// of the form _GLOBAL_OFFSET_TABLE_-symbol. This is needed to support PIC on 243 /// ELF i386 as _GLOBAL_OFFSET_TABLE_ is magical. We check only simple case that 244 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start of a 245 /// binary expression. 246 static GlobalOffsetTableExprKind 247 startsWithGlobalOffsetTable(const MCExpr *Expr) { 248 const MCExpr *RHS = nullptr; 249 if (Expr->getKind() == MCExpr::Binary) { 250 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr); 251 Expr = BE->getLHS(); 252 RHS = BE->getRHS(); 253 } 254 255 if (Expr->getKind() != MCExpr::SymbolRef) 256 return GOT_None; 257 258 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 259 const MCSymbol &S = Ref->getSymbol(); 260 if (S.getName() != "_GLOBAL_OFFSET_TABLE_") 261 return GOT_None; 262 if (RHS && RHS->getKind() == MCExpr::SymbolRef) 263 return GOT_SymDiff; 264 return GOT_Normal; 265 } 266 267 static bool hasSecRelSymbolRef(const MCExpr *Expr) { 268 if (Expr->getKind() == MCExpr::SymbolRef) { 269 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); 270 return Ref->getKind() == MCSymbolRefExpr::VK_SECREL; 271 } 272 return false; 273 } 274 275 static bool isPCRel32Branch(const MCInst &MI, const MCInstrInfo &MCII) { 276 unsigned Opcode = MI.getOpcode(); 277 const MCInstrDesc &Desc = MCII.get(Opcode); 278 if ((Opcode != X86::CALL64pcrel32 && Opcode != X86::JMP_4) || 279 getImmFixupKind(Desc.TSFlags) != FK_PCRel_4) 280 return false; 281 282 unsigned CurOp = X86II::getOperandBias(Desc); 283 const MCOperand &Op = MI.getOperand(CurOp); 284 if (!Op.isExpr()) 285 return false; 286 287 const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(Op.getExpr()); 288 return Ref && Ref->getKind() == MCSymbolRefExpr::VK_None; 289 } 290 291 void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc, 292 unsigned Size, MCFixupKind FixupKind, 293 unsigned &CurByte, raw_ostream &OS, 294 SmallVectorImpl<MCFixup> &Fixups, 295 int ImmOffset) const { 296 const MCExpr *Expr = nullptr; 297 if (DispOp.isImm()) { 298 // If this is a simple integer displacement that doesn't require a 299 // relocation, emit it now. 300 if (FixupKind != FK_PCRel_1 && FixupKind != FK_PCRel_2 && 301 FixupKind != FK_PCRel_4) { 302 emitConstant(DispOp.getImm() + ImmOffset, Size, CurByte, OS); 303 return; 304 } 305 Expr = MCConstantExpr::create(DispOp.getImm(), Ctx); 306 } else { 307 Expr = DispOp.getExpr(); 308 } 309 310 // If we have an immoffset, add it to the expression. 311 if ((FixupKind == FK_Data_4 || FixupKind == FK_Data_8 || 312 FixupKind == MCFixupKind(X86::reloc_signed_4byte))) { 313 GlobalOffsetTableExprKind Kind = startsWithGlobalOffsetTable(Expr); 314 if (Kind != GOT_None) { 315 assert(ImmOffset == 0); 316 317 if (Size == 8) { 318 FixupKind = MCFixupKind(X86::reloc_global_offset_table8); 319 } else { 320 assert(Size == 4); 321 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 322 } 323 324 if (Kind == GOT_Normal) 325 ImmOffset = CurByte; 326 } else if (Expr->getKind() == MCExpr::SymbolRef) { 327 if (hasSecRelSymbolRef(Expr)) { 328 FixupKind = MCFixupKind(FK_SecRel_4); 329 } 330 } else if (Expr->getKind() == MCExpr::Binary) { 331 const MCBinaryExpr *Bin = static_cast<const MCBinaryExpr *>(Expr); 332 if (hasSecRelSymbolRef(Bin->getLHS()) || 333 hasSecRelSymbolRef(Bin->getRHS())) { 334 FixupKind = MCFixupKind(FK_SecRel_4); 335 } 336 } 337 } 338 339 // If the fixup is pc-relative, we need to bias the value to be relative to 340 // the start of the field, not the end of the field. 341 if (FixupKind == FK_PCRel_4 || 342 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) || 343 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load) || 344 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) || 345 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) || 346 FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) { 347 ImmOffset -= 4; 348 // If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_: 349 // leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15 350 // this needs to be a GOTPC32 relocation. 351 if (startsWithGlobalOffsetTable(Expr) != GOT_None) 352 FixupKind = MCFixupKind(X86::reloc_global_offset_table); 353 } 354 if (FixupKind == FK_PCRel_2) 355 ImmOffset -= 2; 356 if (FixupKind == FK_PCRel_1) 357 ImmOffset -= 1; 358 359 if (ImmOffset) 360 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(ImmOffset, Ctx), 361 Ctx); 362 363 // Emit a symbolic constant as a fixup and 4 zeros. 364 Fixups.push_back(MCFixup::create(CurByte, Expr, FixupKind, Loc)); 365 emitConstant(0, Size, CurByte, OS); 366 } 367 368 void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op, 369 unsigned RegOpcodeField, 370 uint64_t TSFlags, bool Rex, 371 unsigned &CurByte, raw_ostream &OS, 372 SmallVectorImpl<MCFixup> &Fixups, 373 const MCSubtargetInfo &STI) const { 374 const MCOperand &Disp = MI.getOperand(Op + X86::AddrDisp); 375 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); 376 const MCOperand &Scale = MI.getOperand(Op + X86::AddrScaleAmt); 377 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); 378 unsigned BaseReg = Base.getReg(); 379 bool HasEVEX = (TSFlags & X86II::EncodingMask) == X86II::EVEX; 380 381 // Handle %rip relative addressing. 382 if (BaseReg == X86::RIP || 383 BaseReg == X86::EIP) { // [disp32+rIP] in X86-64 mode 384 assert(STI.hasFeature(X86::Mode64Bit) && 385 "Rip-relative addressing requires 64-bit mode"); 386 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address"); 387 emitByte(modRMByte(0, RegOpcodeField, 5), CurByte, OS); 388 389 unsigned Opcode = MI.getOpcode(); 390 // movq loads are handled with a special relocation form which allows the 391 // linker to eliminate some loads for GOT references which end up in the 392 // same linkage unit. 393 unsigned FixupKind = [=]() { 394 switch (Opcode) { 395 default: 396 return X86::reloc_riprel_4byte; 397 case X86::MOV64rm: 398 assert(Rex); 399 return X86::reloc_riprel_4byte_movq_load; 400 case X86::CALL64m: 401 case X86::JMP64m: 402 case X86::TAILJMPm64: 403 case X86::TEST64mr: 404 case X86::ADC64rm: 405 case X86::ADD64rm: 406 case X86::AND64rm: 407 case X86::CMP64rm: 408 case X86::OR64rm: 409 case X86::SBB64rm: 410 case X86::SUB64rm: 411 case X86::XOR64rm: 412 return Rex ? X86::reloc_riprel_4byte_relax_rex 413 : X86::reloc_riprel_4byte_relax; 414 } 415 }(); 416 417 // rip-relative addressing is actually relative to the *next* instruction. 418 // Since an immediate can follow the mod/rm byte for an instruction, this 419 // means that we need to bias the displacement field of the instruction with 420 // the size of the immediate field. If we have this case, add it into the 421 // expression to emit. 422 // Note: rip-relative addressing using immediate displacement values should 423 // not be adjusted, assuming it was the user's intent. 424 int ImmSize = !Disp.isImm() && X86II::hasImm(TSFlags) 425 ? X86II::getSizeOfImm(TSFlags) 426 : 0; 427 428 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, 429 Fixups, -ImmSize); 430 return; 431 } 432 433 unsigned BaseRegNo = BaseReg ? getX86RegNum(Base) : -1U; 434 435 // 16-bit addressing forms of the ModR/M byte have a different encoding for 436 // the R/M field and are far more limited in which registers can be used. 437 if (is16BitMemOperand(MI, Op, STI)) { 438 if (BaseReg) { 439 // For 32-bit addressing, the row and column values in Table 2-2 are 440 // basically the same. It's AX/CX/DX/BX/SP/BP/SI/DI in that order, with 441 // some special cases. And getX86RegNum reflects that numbering. 442 // For 16-bit addressing it's more fun, as shown in the SDM Vol 2A, 443 // Table 2-1 "16-Bit Addressing Forms with the ModR/M byte". We can only 444 // use SI/DI/BP/BX, which have "row" values 4-7 in no particular order, 445 // while values 0-3 indicate the allowed combinations (base+index) of 446 // those: 0 for BX+SI, 1 for BX+DI, 2 for BP+SI, 3 for BP+DI. 447 // 448 // R16Table[] is a lookup from the normal RegNo, to the row values from 449 // Table 2-1 for 16-bit addressing modes. Where zero means disallowed. 450 static const unsigned R16Table[] = {0, 0, 0, 7, 0, 6, 4, 5}; 451 unsigned RMfield = R16Table[BaseRegNo]; 452 453 assert(RMfield && "invalid 16-bit base register"); 454 455 if (IndexReg.getReg()) { 456 unsigned IndexReg16 = R16Table[getX86RegNum(IndexReg)]; 457 458 assert(IndexReg16 && "invalid 16-bit index register"); 459 // We must have one of SI/DI (4,5), and one of BP/BX (6,7). 460 assert(((IndexReg16 ^ RMfield) & 2) && 461 "invalid 16-bit base/index register combination"); 462 assert(Scale.getImm() == 1 && 463 "invalid scale for 16-bit memory reference"); 464 465 // Allow base/index to appear in either order (although GAS doesn't). 466 if (IndexReg16 & 2) 467 RMfield = (RMfield & 1) | ((7 - IndexReg16) << 1); 468 else 469 RMfield = (IndexReg16 & 1) | ((7 - RMfield) << 1); 470 } 471 472 if (Disp.isImm() && isDisp8(Disp.getImm())) { 473 if (Disp.getImm() == 0 && RMfield != 6) { 474 // There is no displacement; just the register. 475 emitByte(modRMByte(0, RegOpcodeField, RMfield), CurByte, OS); 476 return; 477 } 478 // Use the [REG]+disp8 form, including for [BP] which cannot be encoded. 479 emitByte(modRMByte(1, RegOpcodeField, RMfield), CurByte, OS); 480 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 481 return; 482 } 483 // This is the [REG]+disp16 case. 484 emitByte(modRMByte(2, RegOpcodeField, RMfield), CurByte, OS); 485 } else { 486 // There is no BaseReg; this is the plain [disp16] case. 487 emitByte(modRMByte(0, RegOpcodeField, 6), CurByte, OS); 488 } 489 490 // Emit 16-bit displacement for plain disp16 or [REG]+disp16 cases. 491 emitImmediate(Disp, MI.getLoc(), 2, FK_Data_2, CurByte, OS, Fixups); 492 return; 493 } 494 495 // Determine whether a SIB byte is needed. 496 // If no BaseReg, issue a RIP relative instruction only if the MCE can 497 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table 498 // 2-7) and absolute references. 499 500 if ( // The SIB byte must be used if there is an index register. 501 IndexReg.getReg() == 0 && 502 // The SIB byte must be used if the base is ESP/RSP/R12, all of which 503 // encode to an R/M value of 4, which indicates that a SIB byte is 504 // present. 505 BaseRegNo != N86::ESP && 506 // If there is no base register and we're in 64-bit mode, we need a SIB 507 // byte to emit an addr that is just 'disp32' (the non-RIP relative form). 508 (!STI.hasFeature(X86::Mode64Bit) || BaseReg != 0)) { 509 510 if (BaseReg == 0) { // [disp32] in X86-32 mode 511 emitByte(modRMByte(0, RegOpcodeField, 5), CurByte, OS); 512 emitImmediate(Disp, MI.getLoc(), 4, FK_Data_4, CurByte, OS, Fixups); 513 return; 514 } 515 516 // If the base is not EBP/ESP and there is no displacement, use simple 517 // indirect register encoding, this handles addresses like [EAX]. The 518 // encoding for [EBP] with no displacement means [disp32] so we handle it 519 // by emitting a displacement of 0 below. 520 if (BaseRegNo != N86::EBP) { 521 if (Disp.isImm() && Disp.getImm() == 0) { 522 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 523 return; 524 } 525 526 // If the displacement is @tlscall, treat it as a zero. 527 if (Disp.isExpr()) { 528 auto *Sym = dyn_cast<MCSymbolRefExpr>(Disp.getExpr()); 529 if (Sym && Sym->getKind() == MCSymbolRefExpr::VK_TLSCALL) { 530 // This is exclusively used by call *a@tlscall(base). The relocation 531 // (R_386_TLSCALL or R_X86_64_TLSCALL) applies to the beginning. 532 Fixups.push_back(MCFixup::create(0, Sym, FK_NONE, MI.getLoc())); 533 emitByte(modRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS); 534 return; 535 } 536 } 537 } 538 539 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8]. 540 if (Disp.isImm()) { 541 if (!HasEVEX && isDisp8(Disp.getImm())) { 542 emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 543 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups); 544 return; 545 } 546 // Try EVEX compressed 8-bit displacement first; if failed, fall back to 547 // 32-bit displacement. 548 int CDisp8 = 0; 549 if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 550 emitByte(modRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS); 551 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 552 CDisp8 - Disp.getImm()); 553 return; 554 } 555 } 556 557 // Otherwise, emit the most general non-SIB encoding: [REG+disp32] 558 emitByte(modRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS); 559 unsigned Opcode = MI.getOpcode(); 560 unsigned FixupKind = Opcode == X86::MOV32rm ? X86::reloc_signed_4byte_relax 561 : X86::reloc_signed_4byte; 562 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(FixupKind), CurByte, OS, 563 Fixups); 564 return; 565 } 566 567 // We need a SIB byte, so start by outputting the ModR/M byte first 568 assert(IndexReg.getReg() != X86::ESP && IndexReg.getReg() != X86::RSP && 569 "Cannot use ESP as index reg!"); 570 571 bool ForceDisp32 = false; 572 bool ForceDisp8 = false; 573 int CDisp8 = 0; 574 int ImmOffset = 0; 575 if (BaseReg == 0) { 576 // If there is no base register, we emit the special case SIB byte with 577 // MOD=0, BASE=5, to JUST get the index, scale, and displacement. 578 emitByte(modRMByte(0, RegOpcodeField, 4), CurByte, OS); 579 ForceDisp32 = true; 580 } else if (!Disp.isImm()) { 581 // Emit the normal disp32 encoding. 582 emitByte(modRMByte(2, RegOpcodeField, 4), CurByte, OS); 583 ForceDisp32 = true; 584 } else if (Disp.getImm() == 0 && 585 // Base reg can't be anything that ends up with '5' as the base 586 // reg, it is the magic [*] nomenclature that indicates no base. 587 BaseRegNo != N86::EBP) { 588 // Emit no displacement ModR/M byte 589 emitByte(modRMByte(0, RegOpcodeField, 4), CurByte, OS); 590 } else if (!HasEVEX && isDisp8(Disp.getImm())) { 591 // Emit the disp8 encoding. 592 emitByte(modRMByte(1, RegOpcodeField, 4), CurByte, OS); 593 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 594 } else if (HasEVEX && isCDisp8(TSFlags, Disp.getImm(), CDisp8)) { 595 // Emit the disp8 encoding. 596 emitByte(modRMByte(1, RegOpcodeField, 4), CurByte, OS); 597 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP 598 ImmOffset = CDisp8 - Disp.getImm(); 599 } else { 600 // Emit the normal disp32 encoding. 601 emitByte(modRMByte(2, RegOpcodeField, 4), CurByte, OS); 602 } 603 604 // Calculate what the SS field value should be... 605 static const unsigned SSTable[] = {~0U, 0, 1, ~0U, 2, ~0U, ~0U, ~0U, 3}; 606 unsigned SS = SSTable[Scale.getImm()]; 607 608 if (BaseReg == 0) { 609 // Handle the SIB byte for the case where there is no base, see Intel 610 // Manual 2A, table 2-7. The displacement has already been output. 611 unsigned IndexRegNo; 612 if (IndexReg.getReg()) 613 IndexRegNo = getX86RegNum(IndexReg); 614 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5) 615 IndexRegNo = 4; 616 emitSIBByte(SS, IndexRegNo, 5, CurByte, OS); 617 } else { 618 unsigned IndexRegNo; 619 if (IndexReg.getReg()) 620 IndexRegNo = getX86RegNum(IndexReg); 621 else 622 IndexRegNo = 4; // For example [ESP+1*<noreg>+4] 623 emitSIBByte(SS, IndexRegNo, getX86RegNum(Base), CurByte, OS); 624 } 625 626 // Do we need to output a displacement? 627 if (ForceDisp8) 628 emitImmediate(Disp, MI.getLoc(), 1, FK_Data_1, CurByte, OS, Fixups, 629 ImmOffset); 630 else if (ForceDisp32 || Disp.getImm() != 0) 631 emitImmediate(Disp, MI.getLoc(), 4, MCFixupKind(X86::reloc_signed_4byte), 632 CurByte, OS, Fixups); 633 } 634 635 void X86MCCodeEmitter::emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, 636 unsigned &CurByte, bool &Rex, 637 const MCInst &MI, const MCInstrDesc &Desc, 638 const MCSubtargetInfo &STI, 639 raw_ostream &OS) const { 640 // Determine where the memory operand starts, if present. 641 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); 642 if (MemoryOperand != -1) 643 MemoryOperand += CurOp; 644 645 // Emit segment override opcode prefix as needed. 646 if (MemoryOperand >= 0) 647 emitSegmentOverridePrefix(CurByte, MemoryOperand + X86::AddrSegmentReg, MI, 648 OS); 649 650 // Emit the repeat opcode prefix as needed. 651 unsigned Flags = MI.getFlags(); 652 if (TSFlags & X86II::REP || Flags & X86::IP_HAS_REPEAT) 653 emitByte(0xF3, CurByte, OS); 654 if (Flags & X86::IP_HAS_REPEAT_NE) 655 emitByte(0xF2, CurByte, OS); 656 657 // Emit the address size opcode prefix as needed. 658 bool need_address_override; 659 uint64_t AdSize = TSFlags & X86II::AdSizeMask; 660 if ((STI.hasFeature(X86::Mode16Bit) && AdSize == X86II::AdSize32) || 661 (STI.hasFeature(X86::Mode32Bit) && AdSize == X86II::AdSize16) || 662 (STI.hasFeature(X86::Mode64Bit) && AdSize == X86II::AdSize32)) { 663 need_address_override = true; 664 } else if (MemoryOperand < 0) { 665 need_address_override = false; 666 } else if (STI.hasFeature(X86::Mode64Bit)) { 667 assert(!is16BitMemOperand(MI, MemoryOperand, STI)); 668 need_address_override = is32BitMemOperand(MI, MemoryOperand); 669 } else if (STI.hasFeature(X86::Mode32Bit)) { 670 assert(!is64BitMemOperand(MI, MemoryOperand)); 671 need_address_override = is16BitMemOperand(MI, MemoryOperand, STI); 672 } else { 673 assert(STI.hasFeature(X86::Mode16Bit)); 674 assert(!is64BitMemOperand(MI, MemoryOperand)); 675 need_address_override = !is16BitMemOperand(MI, MemoryOperand, STI); 676 } 677 678 if (need_address_override) 679 emitByte(0x67, CurByte, OS); 680 681 // Encoding type for this instruction. 682 uint64_t Encoding = TSFlags & X86II::EncodingMask; 683 if (Encoding == 0) 684 Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS); 685 else 686 emitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS); 687 688 uint64_t Form = TSFlags & X86II::FormMask; 689 switch (Form) { 690 default: 691 break; 692 case X86II::RawFrmDstSrc: { 693 unsigned siReg = MI.getOperand(1).getReg(); 694 assert(((siReg == X86::SI && MI.getOperand(0).getReg() == X86::DI) || 695 (siReg == X86::ESI && MI.getOperand(0).getReg() == X86::EDI) || 696 (siReg == X86::RSI && MI.getOperand(0).getReg() == X86::RDI)) && 697 "SI and DI register sizes do not match"); 698 // Emit segment override opcode prefix as needed (not for %ds). 699 if (MI.getOperand(2).getReg() != X86::DS) 700 emitSegmentOverridePrefix(CurByte, 2, MI, OS); 701 // Emit AdSize prefix as needed. 702 if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::ESI) || 703 (STI.hasFeature(X86::Mode32Bit) && siReg == X86::SI)) 704 emitByte(0x67, CurByte, OS); 705 CurOp += 3; // Consume operands. 706 break; 707 } 708 case X86II::RawFrmSrc: { 709 unsigned siReg = MI.getOperand(0).getReg(); 710 // Emit segment override opcode prefix as needed (not for %ds). 711 if (MI.getOperand(1).getReg() != X86::DS) 712 emitSegmentOverridePrefix(CurByte, 1, MI, OS); 713 // Emit AdSize prefix as needed. 714 if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::ESI) || 715 (STI.hasFeature(X86::Mode32Bit) && siReg == X86::SI)) 716 emitByte(0x67, CurByte, OS); 717 CurOp += 2; // Consume operands. 718 break; 719 } 720 case X86II::RawFrmDst: { 721 unsigned siReg = MI.getOperand(0).getReg(); 722 // Emit AdSize prefix as needed. 723 if ((!STI.hasFeature(X86::Mode32Bit) && siReg == X86::EDI) || 724 (STI.hasFeature(X86::Mode32Bit) && siReg == X86::DI)) 725 emitByte(0x67, CurByte, OS); 726 ++CurOp; // Consume operand. 727 break; 728 } 729 case X86II::RawFrmMemOffs: { 730 // Emit segment override opcode prefix as needed. 731 emitSegmentOverridePrefix(CurByte, 1, MI, OS); 732 break; 733 } 734 } 735 } 736 737 /// emitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix 738 /// called VEX. 739 void X86MCCodeEmitter::emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 740 int MemOperand, const MCInst &MI, 741 const MCInstrDesc &Desc, 742 raw_ostream &OS) const { 743 assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX."); 744 745 uint64_t Encoding = TSFlags & X86II::EncodingMask; 746 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 747 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 748 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 749 750 // VEX_R: opcode externsion equivalent to REX.R in 751 // 1's complement (inverted) form 752 // 753 // 1: Same as REX_R=0 (must be 1 in 32-bit mode) 754 // 0: Same as REX_R=1 (64 bit mode only) 755 // 756 uint8_t VEX_R = 0x1; 757 uint8_t EVEX_R2 = 0x1; 758 759 // VEX_X: equivalent to REX.X, only used when a 760 // register is used for index in SIB Byte. 761 // 762 // 1: Same as REX.X=0 (must be 1 in 32-bit mode) 763 // 0: Same as REX.X=1 (64-bit mode only) 764 uint8_t VEX_X = 0x1; 765 766 // VEX_B: 767 // 768 // 1: Same as REX_B=0 (ignored in 32-bit mode) 769 // 0: Same as REX_B=1 (64 bit mode only) 770 // 771 uint8_t VEX_B = 0x1; 772 773 // VEX_W: opcode specific (use like REX.W, or used for 774 // opcode extension, or ignored, depending on the opcode byte) 775 uint8_t VEX_W = (TSFlags & X86II::VEX_W) ? 1 : 0; 776 777 // VEX_5M (VEX m-mmmmm field): 778 // 779 // 0b00000: Reserved for future use 780 // 0b00001: implied 0F leading opcode 781 // 0b00010: implied 0F 38 leading opcode bytes 782 // 0b00011: implied 0F 3A leading opcode bytes 783 // 0b00100-0b11111: Reserved for future use 784 // 0b01000: XOP map select - 08h instructions with imm byte 785 // 0b01001: XOP map select - 09h instructions with no imm byte 786 // 0b01010: XOP map select - 0Ah instructions with imm dword 787 uint8_t VEX_5M; 788 switch (TSFlags & X86II::OpMapMask) { 789 default: 790 llvm_unreachable("Invalid prefix!"); 791 case X86II::TB: 792 VEX_5M = 0x1; 793 break; // 0F 794 case X86II::T8: 795 VEX_5M = 0x2; 796 break; // 0F 38 797 case X86II::TA: 798 VEX_5M = 0x3; 799 break; // 0F 3A 800 case X86II::XOP8: 801 VEX_5M = 0x8; 802 break; 803 case X86II::XOP9: 804 VEX_5M = 0x9; 805 break; 806 case X86II::XOPA: 807 VEX_5M = 0xA; 808 break; 809 } 810 811 // VEX_4V (VEX vvvv field): a register specifier 812 // (in 1's complement form) or 1111 if unused. 813 uint8_t VEX_4V = 0xf; 814 uint8_t EVEX_V2 = 0x1; 815 816 // EVEX_L2/VEX_L (Vector Length): 817 // 818 // L2 L 819 // 0 0: scalar or 128-bit vector 820 // 0 1: 256-bit vector 821 // 1 0: 512-bit vector 822 // 823 uint8_t VEX_L = (TSFlags & X86II::VEX_L) ? 1 : 0; 824 uint8_t EVEX_L2 = (TSFlags & X86II::EVEX_L2) ? 1 : 0; 825 826 // VEX_PP: opcode extension providing equivalent 827 // functionality of a SIMD prefix 828 // 829 // 0b00: None 830 // 0b01: 66 831 // 0b10: F3 832 // 0b11: F2 833 // 834 uint8_t VEX_PP = 0; 835 switch (TSFlags & X86II::OpPrefixMask) { 836 case X86II::PD: 837 VEX_PP = 0x1; 838 break; // 66 839 case X86II::XS: 840 VEX_PP = 0x2; 841 break; // F3 842 case X86II::XD: 843 VEX_PP = 0x3; 844 break; // F2 845 } 846 847 // EVEX_U 848 uint8_t EVEX_U = 1; // Always '1' so far 849 850 // EVEX_z 851 uint8_t EVEX_z = (HasEVEX_K && (TSFlags & X86II::EVEX_Z)) ? 1 : 0; 852 853 // EVEX_b 854 uint8_t EVEX_b = (TSFlags & X86II::EVEX_B) ? 1 : 0; 855 856 // EVEX_rc 857 uint8_t EVEX_rc = 0; 858 859 // EVEX_aaa 860 uint8_t EVEX_aaa = 0; 861 862 bool EncodeRC = false; 863 864 // Classify VEX_B, VEX_4V, VEX_R, VEX_X 865 unsigned NumOps = Desc.getNumOperands(); 866 unsigned CurOp = X86II::getOperandBias(Desc); 867 868 switch (TSFlags & X86II::FormMask) { 869 default: 870 llvm_unreachable("Unexpected form in emitVEXOpcodePrefix!"); 871 case X86II::RawFrm: 872 break; 873 case X86II::MRMDestMem: { 874 // MRMDestMem instructions forms: 875 // MemAddr, src1(ModR/M) 876 // MemAddr, src1(VEX_4V), src2(ModR/M) 877 // MemAddr, src1(ModR/M), imm8 878 // 879 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 880 VEX_B = ~(BaseRegEnc >> 3) & 1; 881 unsigned IndexRegEnc = 882 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 883 VEX_X = ~(IndexRegEnc >> 3) & 1; 884 if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 885 EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 886 887 CurOp += X86::AddrNumOperands; 888 889 if (HasEVEX_K) 890 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 891 892 if (HasVEX_4V) { 893 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 894 VEX_4V = ~VRegEnc & 0xf; 895 EVEX_V2 = ~(VRegEnc >> 4) & 1; 896 } 897 898 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 899 VEX_R = ~(RegEnc >> 3) & 1; 900 EVEX_R2 = ~(RegEnc >> 4) & 1; 901 break; 902 } 903 case X86II::MRMSrcMem: { 904 // MRMSrcMem instructions forms: 905 // src1(ModR/M), MemAddr 906 // src1(ModR/M), src2(VEX_4V), MemAddr 907 // src1(ModR/M), MemAddr, imm8 908 // src1(ModR/M), MemAddr, src2(Imm[7:4]) 909 // 910 // FMA4: 911 // dst(ModR/M.reg), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 912 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 913 VEX_R = ~(RegEnc >> 3) & 1; 914 EVEX_R2 = ~(RegEnc >> 4) & 1; 915 916 if (HasEVEX_K) 917 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 918 919 if (HasVEX_4V) { 920 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 921 VEX_4V = ~VRegEnc & 0xf; 922 EVEX_V2 = ~(VRegEnc >> 4) & 1; 923 } 924 925 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 926 VEX_B = ~(BaseRegEnc >> 3) & 1; 927 unsigned IndexRegEnc = 928 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 929 VEX_X = ~(IndexRegEnc >> 3) & 1; 930 if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 931 EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 932 933 break; 934 } 935 case X86II::MRMSrcMem4VOp3: { 936 // Instruction format for 4VOp3: 937 // src1(ModR/M), MemAddr, src3(VEX_4V) 938 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 939 VEX_R = ~(RegEnc >> 3) & 1; 940 941 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 942 VEX_B = ~(BaseRegEnc >> 3) & 1; 943 unsigned IndexRegEnc = 944 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 945 VEX_X = ~(IndexRegEnc >> 3) & 1; 946 947 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; 948 break; 949 } 950 case X86II::MRMSrcMemOp4: { 951 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 952 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 953 VEX_R = ~(RegEnc >> 3) & 1; 954 955 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 956 VEX_4V = ~VRegEnc & 0xf; 957 958 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 959 VEX_B = ~(BaseRegEnc >> 3) & 1; 960 unsigned IndexRegEnc = 961 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 962 VEX_X = ~(IndexRegEnc >> 3) & 1; 963 break; 964 } 965 case X86II::MRM0m: 966 case X86II::MRM1m: 967 case X86II::MRM2m: 968 case X86II::MRM3m: 969 case X86II::MRM4m: 970 case X86II::MRM5m: 971 case X86II::MRM6m: 972 case X86II::MRM7m: { 973 // MRM[0-9]m instructions forms: 974 // MemAddr 975 // src1(VEX_4V), MemAddr 976 if (HasVEX_4V) { 977 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 978 VEX_4V = ~VRegEnc & 0xf; 979 EVEX_V2 = ~(VRegEnc >> 4) & 1; 980 } 981 982 if (HasEVEX_K) 983 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 984 985 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 986 VEX_B = ~(BaseRegEnc >> 3) & 1; 987 unsigned IndexRegEnc = 988 getX86RegEncoding(MI, MemOperand + X86::AddrIndexReg); 989 VEX_X = ~(IndexRegEnc >> 3) & 1; 990 if (!HasVEX_4V) // Only needed with VSIB which don't use VVVV. 991 EVEX_V2 = ~(IndexRegEnc >> 4) & 1; 992 993 break; 994 } 995 case X86II::MRMSrcReg: { 996 // MRMSrcReg instructions forms: 997 // dst(ModR/M), src1(VEX_4V), src2(ModR/M), src3(Imm[7:4]) 998 // dst(ModR/M), src1(ModR/M) 999 // dst(ModR/M), src1(ModR/M), imm8 1000 // 1001 // FMA4: 1002 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 1003 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1004 VEX_R = ~(RegEnc >> 3) & 1; 1005 EVEX_R2 = ~(RegEnc >> 4) & 1; 1006 1007 if (HasEVEX_K) 1008 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1009 1010 if (HasVEX_4V) { 1011 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1012 VEX_4V = ~VRegEnc & 0xf; 1013 EVEX_V2 = ~(VRegEnc >> 4) & 1; 1014 } 1015 1016 RegEnc = getX86RegEncoding(MI, CurOp++); 1017 VEX_B = ~(RegEnc >> 3) & 1; 1018 VEX_X = ~(RegEnc >> 4) & 1; 1019 1020 if (EVEX_b) { 1021 if (HasEVEX_RC) { 1022 unsigned RcOperand = NumOps - 1; 1023 assert(RcOperand >= CurOp); 1024 EVEX_rc = MI.getOperand(RcOperand).getImm(); 1025 assert(EVEX_rc <= 3 && "Invalid rounding control!"); 1026 } 1027 EncodeRC = true; 1028 } 1029 break; 1030 } 1031 case X86II::MRMSrcReg4VOp3: { 1032 // Instruction format for 4VOp3: 1033 // src1(ModR/M), src2(ModR/M), src3(VEX_4V) 1034 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1035 VEX_R = ~(RegEnc >> 3) & 1; 1036 1037 RegEnc = getX86RegEncoding(MI, CurOp++); 1038 VEX_B = ~(RegEnc >> 3) & 1; 1039 1040 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; 1041 break; 1042 } 1043 case X86II::MRMSrcRegOp4: { 1044 // dst(ModR/M.reg), src1(VEX_4V), src2(Imm[7:4]), src3(ModR/M), 1045 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1046 VEX_R = ~(RegEnc >> 3) & 1; 1047 1048 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1049 VEX_4V = ~VRegEnc & 0xf; 1050 1051 // Skip second register source (encoded in Imm[7:4]) 1052 ++CurOp; 1053 1054 RegEnc = getX86RegEncoding(MI, CurOp++); 1055 VEX_B = ~(RegEnc >> 3) & 1; 1056 VEX_X = ~(RegEnc >> 4) & 1; 1057 break; 1058 } 1059 case X86II::MRMDestReg: { 1060 // MRMDestReg instructions forms: 1061 // dst(ModR/M), src(ModR/M) 1062 // dst(ModR/M), src(ModR/M), imm8 1063 // dst(ModR/M), src1(VEX_4V), src2(ModR/M) 1064 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1065 VEX_B = ~(RegEnc >> 3) & 1; 1066 VEX_X = ~(RegEnc >> 4) & 1; 1067 1068 if (HasEVEX_K) 1069 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1070 1071 if (HasVEX_4V) { 1072 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1073 VEX_4V = ~VRegEnc & 0xf; 1074 EVEX_V2 = ~(VRegEnc >> 4) & 1; 1075 } 1076 1077 RegEnc = getX86RegEncoding(MI, CurOp++); 1078 VEX_R = ~(RegEnc >> 3) & 1; 1079 EVEX_R2 = ~(RegEnc >> 4) & 1; 1080 if (EVEX_b) 1081 EncodeRC = true; 1082 break; 1083 } 1084 case X86II::MRM0r: 1085 case X86II::MRM1r: 1086 case X86II::MRM2r: 1087 case X86II::MRM3r: 1088 case X86II::MRM4r: 1089 case X86II::MRM5r: 1090 case X86II::MRM6r: 1091 case X86II::MRM7r: { 1092 // MRM0r-MRM7r instructions forms: 1093 // dst(VEX_4V), src(ModR/M), imm8 1094 if (HasVEX_4V) { 1095 unsigned VRegEnc = getX86RegEncoding(MI, CurOp++); 1096 VEX_4V = ~VRegEnc & 0xf; 1097 EVEX_V2 = ~(VRegEnc >> 4) & 1; 1098 } 1099 if (HasEVEX_K) 1100 EVEX_aaa = getX86RegEncoding(MI, CurOp++); 1101 1102 unsigned RegEnc = getX86RegEncoding(MI, CurOp++); 1103 VEX_B = ~(RegEnc >> 3) & 1; 1104 VEX_X = ~(RegEnc >> 4) & 1; 1105 break; 1106 } 1107 } 1108 1109 if (Encoding == X86II::VEX || Encoding == X86II::XOP) { 1110 // VEX opcode prefix can have 2 or 3 bytes 1111 // 1112 // 3 bytes: 1113 // +-----+ +--------------+ +-------------------+ 1114 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp | 1115 // +-----+ +--------------+ +-------------------+ 1116 // 2 bytes: 1117 // +-----+ +-------------------+ 1118 // | C5h | | R | vvvv | L | pp | 1119 // +-----+ +-------------------+ 1120 // 1121 // XOP uses a similar prefix: 1122 // +-----+ +--------------+ +-------------------+ 1123 // | 8Fh | | RXB | m-mmmm | | W | vvvv | L | pp | 1124 // +-----+ +--------------+ +-------------------+ 1125 uint8_t LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); 1126 1127 // Can we use the 2 byte VEX prefix? 1128 if (!(MI.getFlags() & X86::IP_USE_VEX3) && Encoding == X86II::VEX && 1129 VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { 1130 emitByte(0xC5, CurByte, OS); 1131 emitByte(LastByte | (VEX_R << 7), CurByte, OS); 1132 return; 1133 } 1134 1135 // 3 byte VEX prefix 1136 emitByte(Encoding == X86II::XOP ? 0x8F : 0xC4, CurByte, OS); 1137 emitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS); 1138 emitByte(LastByte | (VEX_W << 7), CurByte, OS); 1139 } else { 1140 assert(Encoding == X86II::EVEX && "unknown encoding!"); 1141 // EVEX opcode prefix can have 4 bytes 1142 // 1143 // +-----+ +--------------+ +-------------------+ +------------------------+ 1144 // | 62h | | RXBR' | 00mm | | W | vvvv | U | pp | | z | L'L | b | v' | aaa | 1145 // +-----+ +--------------+ +-------------------+ +------------------------+ 1146 assert((VEX_5M & 0x3) == VEX_5M && 1147 "More than 2 significant bits in VEX.m-mmmm fields for EVEX!"); 1148 1149 emitByte(0x62, CurByte, OS); 1150 emitByte((VEX_R << 7) | (VEX_X << 6) | (VEX_B << 5) | (EVEX_R2 << 4) | 1151 VEX_5M, 1152 CurByte, OS); 1153 emitByte((VEX_W << 7) | (VEX_4V << 3) | (EVEX_U << 2) | VEX_PP, CurByte, 1154 OS); 1155 if (EncodeRC) 1156 emitByte((EVEX_z << 7) | (EVEX_rc << 5) | (EVEX_b << 4) | (EVEX_V2 << 3) | 1157 EVEX_aaa, 1158 CurByte, OS); 1159 else 1160 emitByte((EVEX_z << 7) | (EVEX_L2 << 6) | (VEX_L << 5) | (EVEX_b << 4) | 1161 (EVEX_V2 << 3) | EVEX_aaa, 1162 CurByte, OS); 1163 } 1164 } 1165 1166 /// Determine if the MCInst has to be encoded with a X86-64 REX prefix which 1167 /// specifies 1) 64-bit instructions, 2) non-default operand size, and 3) use 1168 /// of X86-64 extended registers. 1169 uint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI, uint64_t TSFlags, 1170 int MemOperand, 1171 const MCInstrDesc &Desc) const { 1172 uint8_t REX = 0; 1173 bool UsesHighByteReg = false; 1174 1175 if (TSFlags & X86II::REX_W) 1176 REX |= 1 << 3; // set REX.W 1177 1178 if (MI.getNumOperands() == 0) 1179 return REX; 1180 1181 unsigned NumOps = MI.getNumOperands(); 1182 unsigned CurOp = X86II::getOperandBias(Desc); 1183 1184 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 1185 for (unsigned i = CurOp; i != NumOps; ++i) { 1186 const MCOperand &MO = MI.getOperand(i); 1187 if (!MO.isReg()) 1188 continue; 1189 unsigned Reg = MO.getReg(); 1190 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) 1191 UsesHighByteReg = true; 1192 if (X86II::isX86_64NonExtLowByteReg(Reg)) 1193 // FIXME: The caller of determineREXPrefix slaps this prefix onto anything 1194 // that returns non-zero. 1195 REX |= 0x40; // REX fixed encoding prefix 1196 } 1197 1198 switch (TSFlags & X86II::FormMask) { 1199 case X86II::AddRegFrm: 1200 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1201 break; 1202 case X86II::MRMSrcReg: 1203 case X86II::MRMSrcRegCC: 1204 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1205 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1206 break; 1207 case X86II::MRMSrcMem: 1208 case X86II::MRMSrcMemCC: 1209 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1210 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1211 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1212 CurOp += X86::AddrNumOperands; 1213 break; 1214 case X86II::MRMDestReg: 1215 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1216 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1217 break; 1218 case X86II::MRMDestMem: 1219 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1220 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1221 CurOp += X86::AddrNumOperands; 1222 REX |= isREXExtendedReg(MI, CurOp++) << 2; // REX.R 1223 break; 1224 case X86II::MRMXmCC: 1225 case X86II::MRMXm: 1226 case X86II::MRM0m: 1227 case X86II::MRM1m: 1228 case X86II::MRM2m: 1229 case X86II::MRM3m: 1230 case X86II::MRM4m: 1231 case X86II::MRM5m: 1232 case X86II::MRM6m: 1233 case X86II::MRM7m: 1234 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B 1235 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrIndexReg) << 1; // REX.X 1236 break; 1237 case X86II::MRMXrCC: 1238 case X86II::MRMXr: 1239 case X86II::MRM0r: 1240 case X86II::MRM1r: 1241 case X86II::MRM2r: 1242 case X86II::MRM3r: 1243 case X86II::MRM4r: 1244 case X86II::MRM5r: 1245 case X86II::MRM6r: 1246 case X86II::MRM7r: 1247 REX |= isREXExtendedReg(MI, CurOp++) << 0; // REX.B 1248 break; 1249 } 1250 if (REX && UsesHighByteReg) 1251 report_fatal_error( 1252 "Cannot encode high byte register in REX-prefixed instruction"); 1253 1254 return REX; 1255 } 1256 1257 /// Emit segment override opcode prefix as needed. 1258 void X86MCCodeEmitter::emitSegmentOverridePrefix(unsigned &CurByte, 1259 unsigned SegOperand, 1260 const MCInst &MI, 1261 raw_ostream &OS) const { 1262 // Check for explicit segment override on memory operand. 1263 switch (MI.getOperand(SegOperand).getReg()) { 1264 default: 1265 llvm_unreachable("Unknown segment register!"); 1266 case 0: 1267 break; 1268 case X86::CS: 1269 emitByte(0x2E, CurByte, OS); 1270 break; 1271 case X86::SS: 1272 emitByte(0x36, CurByte, OS); 1273 break; 1274 case X86::DS: 1275 emitByte(0x3E, CurByte, OS); 1276 break; 1277 case X86::ES: 1278 emitByte(0x26, CurByte, OS); 1279 break; 1280 case X86::FS: 1281 emitByte(0x64, CurByte, OS); 1282 break; 1283 case X86::GS: 1284 emitByte(0x65, CurByte, OS); 1285 break; 1286 } 1287 } 1288 1289 /// Emit all instruction prefixes prior to the opcode. 1290 /// 1291 /// \param MemOperand the operand # of the start of a memory operand if present. 1292 /// If not present, it is -1. 1293 /// 1294 /// \returns true if a REX prefix was used. 1295 bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, 1296 int MemOperand, const MCInst &MI, 1297 const MCInstrDesc &Desc, 1298 const MCSubtargetInfo &STI, 1299 raw_ostream &OS) const { 1300 bool Ret = false; 1301 // Emit the operand size opcode prefix as needed. 1302 if ((TSFlags & X86II::OpSizeMask) == 1303 (STI.hasFeature(X86::Mode16Bit) ? X86II::OpSize32 : X86II::OpSize16)) 1304 emitByte(0x66, CurByte, OS); 1305 1306 // Emit the LOCK opcode prefix. 1307 if (TSFlags & X86II::LOCK || MI.getFlags() & X86::IP_HAS_LOCK) 1308 emitByte(0xF0, CurByte, OS); 1309 1310 // Emit the NOTRACK opcode prefix. 1311 if (TSFlags & X86II::NOTRACK || MI.getFlags() & X86::IP_HAS_NOTRACK) 1312 emitByte(0x3E, CurByte, OS); 1313 1314 switch (TSFlags & X86II::OpPrefixMask) { 1315 case X86II::PD: // 66 1316 emitByte(0x66, CurByte, OS); 1317 break; 1318 case X86II::XS: // F3 1319 emitByte(0xF3, CurByte, OS); 1320 break; 1321 case X86II::XD: // F2 1322 emitByte(0xF2, CurByte, OS); 1323 break; 1324 } 1325 1326 // Handle REX prefix. 1327 // FIXME: Can this come before F2 etc to simplify emission? 1328 if (STI.hasFeature(X86::Mode64Bit)) { 1329 if (uint8_t REX = determineREXPrefix(MI, TSFlags, MemOperand, Desc)) { 1330 emitByte(0x40 | REX, CurByte, OS); 1331 Ret = true; 1332 } 1333 } else { 1334 assert(!(TSFlags & X86II::REX_W) && "REX.W requires 64bit mode."); 1335 } 1336 1337 // 0x0F escape code must be emitted just before the opcode. 1338 switch (TSFlags & X86II::OpMapMask) { 1339 case X86II::TB: // Two-byte opcode map 1340 case X86II::T8: // 0F 38 1341 case X86II::TA: // 0F 3A 1342 case X86II::ThreeDNow: // 0F 0F, second 0F emitted by caller. 1343 emitByte(0x0F, CurByte, OS); 1344 break; 1345 } 1346 1347 switch (TSFlags & X86II::OpMapMask) { 1348 case X86II::T8: // 0F 38 1349 emitByte(0x38, CurByte, OS); 1350 break; 1351 case X86II::TA: // 0F 3A 1352 emitByte(0x3A, CurByte, OS); 1353 break; 1354 } 1355 return Ret; 1356 } 1357 1358 void X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS, 1359 const MCSubtargetInfo &STI) const { 1360 unsigned Opcode = MI.getOpcode(); 1361 const MCInstrDesc &Desc = MCII.get(Opcode); 1362 uint64_t TSFlags = Desc.TSFlags; 1363 1364 // Pseudo instructions don't get encoded. 1365 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1366 return; 1367 1368 unsigned CurOp = X86II::getOperandBias(Desc); 1369 1370 // Keep track of the current byte being emitted. 1371 unsigned CurByte = 0; 1372 1373 bool Rex = false; 1374 emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS); 1375 } 1376 1377 void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, 1378 SmallVectorImpl<MCFixup> &Fixups, 1379 const MCSubtargetInfo &STI) const { 1380 unsigned Opcode = MI.getOpcode(); 1381 const MCInstrDesc &Desc = MCII.get(Opcode); 1382 uint64_t TSFlags = Desc.TSFlags; 1383 1384 // Pseudo instructions don't get encoded. 1385 if ((TSFlags & X86II::FormMask) == X86II::Pseudo) 1386 return; 1387 1388 unsigned NumOps = Desc.getNumOperands(); 1389 unsigned CurOp = X86II::getOperandBias(Desc); 1390 1391 // Keep track of the current byte being emitted. 1392 unsigned CurByte = 0; 1393 1394 bool Rex = false; 1395 emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS); 1396 1397 // It uses the VEX.VVVV field? 1398 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1399 bool HasVEX_I8Reg = (TSFlags & X86II::ImmMask) == X86II::Imm8Reg; 1400 1401 // It uses the EVEX.aaa field? 1402 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1403 bool HasEVEX_RC = TSFlags & X86II::EVEX_RC; 1404 1405 // Used if a register is encoded in 7:4 of immediate. 1406 unsigned I8RegNum = 0; 1407 1408 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); 1409 1410 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow) 1411 BaseOpcode = 0x0F; // Weird 3DNow! encoding. 1412 1413 unsigned OpcodeOffset = 0; 1414 1415 uint64_t Form = TSFlags & X86II::FormMask; 1416 switch (Form) { 1417 default: 1418 errs() << "FORM: " << Form << "\n"; 1419 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!"); 1420 case X86II::Pseudo: 1421 llvm_unreachable("Pseudo instruction shouldn't be emitted"); 1422 case X86II::RawFrmDstSrc: 1423 case X86II::RawFrmSrc: 1424 case X86II::RawFrmDst: 1425 emitByte(BaseOpcode, CurByte, OS); 1426 break; 1427 case X86II::AddCCFrm: { 1428 // This will be added to the opcode in the fallthrough. 1429 OpcodeOffset = MI.getOperand(NumOps - 1).getImm(); 1430 assert(OpcodeOffset < 16 && "Unexpected opcode offset!"); 1431 --NumOps; // Drop the operand from the end. 1432 LLVM_FALLTHROUGH; 1433 case X86II::RawFrm: 1434 emitByte(BaseOpcode + OpcodeOffset, CurByte, OS); 1435 1436 if (!STI.hasFeature(X86::Mode64Bit) || !isPCRel32Branch(MI, MCII)) 1437 break; 1438 1439 const MCOperand &Op = MI.getOperand(CurOp++); 1440 emitImmediate(Op, MI.getLoc(), X86II::getSizeOfImm(TSFlags), 1441 MCFixupKind(X86::reloc_branch_4byte_pcrel), CurByte, OS, 1442 Fixups); 1443 break; 1444 } 1445 case X86II::RawFrmMemOffs: 1446 emitByte(BaseOpcode, CurByte, OS); 1447 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1448 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1449 CurByte, OS, Fixups); 1450 ++CurOp; // skip segment operand 1451 break; 1452 case X86II::RawFrmImm8: 1453 emitByte(BaseOpcode, CurByte, OS); 1454 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1455 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1456 CurByte, OS, Fixups); 1457 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1, FK_Data_1, CurByte, 1458 OS, Fixups); 1459 break; 1460 case X86II::RawFrmImm16: 1461 emitByte(BaseOpcode, CurByte, OS); 1462 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1463 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1464 CurByte, OS, Fixups); 1465 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 2, FK_Data_2, CurByte, 1466 OS, Fixups); 1467 break; 1468 1469 case X86II::AddRegFrm: 1470 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); 1471 break; 1472 1473 case X86II::MRMDestReg: { 1474 emitByte(BaseOpcode, CurByte, OS); 1475 unsigned SrcRegNum = CurOp + 1; 1476 1477 if (HasEVEX_K) // Skip writemask 1478 ++SrcRegNum; 1479 1480 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1481 ++SrcRegNum; 1482 1483 emitRegModRMByte(MI.getOperand(CurOp), 1484 getX86RegNum(MI.getOperand(SrcRegNum)), CurByte, OS); 1485 CurOp = SrcRegNum + 1; 1486 break; 1487 } 1488 case X86II::MRMDestMem: { 1489 emitByte(BaseOpcode, CurByte, OS); 1490 unsigned SrcRegNum = CurOp + X86::AddrNumOperands; 1491 1492 if (HasEVEX_K) // Skip writemask 1493 ++SrcRegNum; 1494 1495 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1496 ++SrcRegNum; 1497 1498 emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(SrcRegNum)), TSFlags, 1499 Rex, CurByte, OS, Fixups, STI); 1500 CurOp = SrcRegNum + 1; 1501 break; 1502 } 1503 case X86II::MRMSrcReg: { 1504 emitByte(BaseOpcode, CurByte, OS); 1505 unsigned SrcRegNum = CurOp + 1; 1506 1507 if (HasEVEX_K) // Skip writemask 1508 ++SrcRegNum; 1509 1510 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV) 1511 ++SrcRegNum; 1512 1513 emitRegModRMByte(MI.getOperand(SrcRegNum), 1514 getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1515 CurOp = SrcRegNum + 1; 1516 if (HasVEX_I8Reg) 1517 I8RegNum = getX86RegEncoding(MI, CurOp++); 1518 // do not count the rounding control operand 1519 if (HasEVEX_RC) 1520 --NumOps; 1521 break; 1522 } 1523 case X86II::MRMSrcReg4VOp3: { 1524 emitByte(BaseOpcode, CurByte, OS); 1525 unsigned SrcRegNum = CurOp + 1; 1526 1527 emitRegModRMByte(MI.getOperand(SrcRegNum), 1528 getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1529 CurOp = SrcRegNum + 1; 1530 ++CurOp; // Encoded in VEX.VVVV 1531 break; 1532 } 1533 case X86II::MRMSrcRegOp4: { 1534 emitByte(BaseOpcode, CurByte, OS); 1535 unsigned SrcRegNum = CurOp + 1; 1536 1537 // Skip 1st src (which is encoded in VEX_VVVV) 1538 ++SrcRegNum; 1539 1540 // Capture 2nd src (which is encoded in Imm[7:4]) 1541 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1542 I8RegNum = getX86RegEncoding(MI, SrcRegNum++); 1543 1544 emitRegModRMByte(MI.getOperand(SrcRegNum), 1545 getX86RegNum(MI.getOperand(CurOp)), CurByte, OS); 1546 CurOp = SrcRegNum + 1; 1547 break; 1548 } 1549 case X86II::MRMSrcRegCC: { 1550 unsigned FirstOp = CurOp++; 1551 unsigned SecondOp = CurOp++; 1552 1553 unsigned CC = MI.getOperand(CurOp++).getImm(); 1554 emitByte(BaseOpcode + CC, CurByte, OS); 1555 1556 emitRegModRMByte(MI.getOperand(SecondOp), 1557 getX86RegNum(MI.getOperand(FirstOp)), CurByte, OS); 1558 break; 1559 } 1560 case X86II::MRMSrcMem: { 1561 unsigned FirstMemOp = CurOp + 1; 1562 1563 if (HasEVEX_K) // Skip writemask 1564 ++FirstMemOp; 1565 1566 if (HasVEX_4V) 1567 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1568 1569 emitByte(BaseOpcode, CurByte, OS); 1570 1571 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1572 TSFlags, Rex, CurByte, OS, Fixups, STI); 1573 CurOp = FirstMemOp + X86::AddrNumOperands; 1574 if (HasVEX_I8Reg) 1575 I8RegNum = getX86RegEncoding(MI, CurOp++); 1576 break; 1577 } 1578 case X86II::MRMSrcMem4VOp3: { 1579 unsigned FirstMemOp = CurOp + 1; 1580 1581 emitByte(BaseOpcode, CurByte, OS); 1582 1583 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1584 TSFlags, Rex, CurByte, OS, Fixups, STI); 1585 CurOp = FirstMemOp + X86::AddrNumOperands; 1586 ++CurOp; // Encoded in VEX.VVVV. 1587 break; 1588 } 1589 case X86II::MRMSrcMemOp4: { 1590 unsigned FirstMemOp = CurOp + 1; 1591 1592 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV). 1593 1594 // Capture second register source (encoded in Imm[7:4]) 1595 assert(HasVEX_I8Reg && "MRMSrcRegOp4 should imply VEX_I8Reg"); 1596 I8RegNum = getX86RegEncoding(MI, FirstMemOp++); 1597 1598 emitByte(BaseOpcode, CurByte, OS); 1599 1600 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(CurOp)), 1601 TSFlags, Rex, CurByte, OS, Fixups, STI); 1602 CurOp = FirstMemOp + X86::AddrNumOperands; 1603 break; 1604 } 1605 case X86II::MRMSrcMemCC: { 1606 unsigned RegOp = CurOp++; 1607 unsigned FirstMemOp = CurOp; 1608 CurOp = FirstMemOp + X86::AddrNumOperands; 1609 1610 unsigned CC = MI.getOperand(CurOp++).getImm(); 1611 emitByte(BaseOpcode + CC, CurByte, OS); 1612 1613 emitMemModRMByte(MI, FirstMemOp, getX86RegNum(MI.getOperand(RegOp)), 1614 TSFlags, Rex, CurByte, OS, Fixups, STI); 1615 break; 1616 } 1617 1618 case X86II::MRMXrCC: { 1619 unsigned RegOp = CurOp++; 1620 1621 unsigned CC = MI.getOperand(CurOp++).getImm(); 1622 emitByte(BaseOpcode + CC, CurByte, OS); 1623 emitRegModRMByte(MI.getOperand(RegOp), 0, CurByte, OS); 1624 break; 1625 } 1626 1627 case X86II::MRMXr: 1628 case X86II::MRM0r: 1629 case X86II::MRM1r: 1630 case X86II::MRM2r: 1631 case X86II::MRM3r: 1632 case X86II::MRM4r: 1633 case X86II::MRM5r: 1634 case X86II::MRM6r: 1635 case X86II::MRM7r: 1636 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1637 ++CurOp; 1638 if (HasEVEX_K) // Skip writemask 1639 ++CurOp; 1640 emitByte(BaseOpcode, CurByte, OS); 1641 emitRegModRMByte(MI.getOperand(CurOp++), 1642 (Form == X86II::MRMXr) ? 0 : Form - X86II::MRM0r, CurByte, 1643 OS); 1644 break; 1645 1646 case X86II::MRMXmCC: { 1647 unsigned FirstMemOp = CurOp; 1648 CurOp = FirstMemOp + X86::AddrNumOperands; 1649 1650 unsigned CC = MI.getOperand(CurOp++).getImm(); 1651 emitByte(BaseOpcode + CC, CurByte, OS); 1652 1653 emitMemModRMByte(MI, FirstMemOp, 0, TSFlags, Rex, CurByte, OS, Fixups, STI); 1654 break; 1655 } 1656 1657 case X86II::MRMXm: 1658 case X86II::MRM0m: 1659 case X86II::MRM1m: 1660 case X86II::MRM2m: 1661 case X86II::MRM3m: 1662 case X86II::MRM4m: 1663 case X86II::MRM5m: 1664 case X86II::MRM6m: 1665 case X86II::MRM7m: 1666 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV). 1667 ++CurOp; 1668 if (HasEVEX_K) // Skip writemask 1669 ++CurOp; 1670 emitByte(BaseOpcode, CurByte, OS); 1671 emitMemModRMByte(MI, CurOp, 1672 (Form == X86II::MRMXm) ? 0 : Form - X86II::MRM0m, TSFlags, 1673 Rex, CurByte, OS, Fixups, STI); 1674 CurOp += X86::AddrNumOperands; 1675 break; 1676 1677 case X86II::MRM_C0: 1678 case X86II::MRM_C1: 1679 case X86II::MRM_C2: 1680 case X86II::MRM_C3: 1681 case X86II::MRM_C4: 1682 case X86II::MRM_C5: 1683 case X86II::MRM_C6: 1684 case X86II::MRM_C7: 1685 case X86II::MRM_C8: 1686 case X86II::MRM_C9: 1687 case X86II::MRM_CA: 1688 case X86II::MRM_CB: 1689 case X86II::MRM_CC: 1690 case X86II::MRM_CD: 1691 case X86II::MRM_CE: 1692 case X86II::MRM_CF: 1693 case X86II::MRM_D0: 1694 case X86II::MRM_D1: 1695 case X86II::MRM_D2: 1696 case X86II::MRM_D3: 1697 case X86II::MRM_D4: 1698 case X86II::MRM_D5: 1699 case X86II::MRM_D6: 1700 case X86II::MRM_D7: 1701 case X86II::MRM_D8: 1702 case X86II::MRM_D9: 1703 case X86II::MRM_DA: 1704 case X86II::MRM_DB: 1705 case X86II::MRM_DC: 1706 case X86II::MRM_DD: 1707 case X86II::MRM_DE: 1708 case X86II::MRM_DF: 1709 case X86II::MRM_E0: 1710 case X86II::MRM_E1: 1711 case X86II::MRM_E2: 1712 case X86II::MRM_E3: 1713 case X86II::MRM_E4: 1714 case X86II::MRM_E5: 1715 case X86II::MRM_E6: 1716 case X86II::MRM_E7: 1717 case X86II::MRM_E8: 1718 case X86II::MRM_E9: 1719 case X86II::MRM_EA: 1720 case X86II::MRM_EB: 1721 case X86II::MRM_EC: 1722 case X86II::MRM_ED: 1723 case X86II::MRM_EE: 1724 case X86II::MRM_EF: 1725 case X86II::MRM_F0: 1726 case X86II::MRM_F1: 1727 case X86II::MRM_F2: 1728 case X86II::MRM_F3: 1729 case X86II::MRM_F4: 1730 case X86II::MRM_F5: 1731 case X86II::MRM_F6: 1732 case X86II::MRM_F7: 1733 case X86II::MRM_F8: 1734 case X86II::MRM_F9: 1735 case X86II::MRM_FA: 1736 case X86II::MRM_FB: 1737 case X86II::MRM_FC: 1738 case X86II::MRM_FD: 1739 case X86II::MRM_FE: 1740 case X86II::MRM_FF: 1741 emitByte(BaseOpcode, CurByte, OS); 1742 emitByte(0xC0 + Form - X86II::MRM_C0, CurByte, OS); 1743 break; 1744 } 1745 1746 if (HasVEX_I8Reg) { 1747 // The last source register of a 4 operand instruction in AVX is encoded 1748 // in bits[7:4] of a immediate byte. 1749 assert(I8RegNum < 16 && "Register encoding out of range"); 1750 I8RegNum <<= 4; 1751 if (CurOp != NumOps) { 1752 unsigned Val = MI.getOperand(CurOp++).getImm(); 1753 assert(Val < 16 && "Immediate operand value out of range"); 1754 I8RegNum |= Val; 1755 } 1756 emitImmediate(MCOperand::createImm(I8RegNum), MI.getLoc(), 1, FK_Data_1, 1757 CurByte, OS, Fixups); 1758 } else { 1759 // If there is a remaining operand, it must be a trailing immediate. Emit it 1760 // according to the right size for the instruction. Some instructions 1761 // (SSE4a extrq and insertq) have two trailing immediates. 1762 while (CurOp != NumOps && NumOps - CurOp <= 2) { 1763 emitImmediate(MI.getOperand(CurOp++), MI.getLoc(), 1764 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags), 1765 CurByte, OS, Fixups); 1766 } 1767 } 1768 1769 if ((TSFlags & X86II::OpMapMask) == X86II::ThreeDNow) 1770 emitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS); 1771 1772 #ifndef NDEBUG 1773 // FIXME: Verify. 1774 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) { 1775 errs() << "Cannot encode all operands of: "; 1776 MI.dump(); 1777 errs() << '\n'; 1778 abort(); 1779 } 1780 #endif 1781 } 1782 1783 MCCodeEmitter *llvm::createX86MCCodeEmitter(const MCInstrInfo &MCII, 1784 const MCRegisterInfo &MRI, 1785 MCContext &Ctx) { 1786 return new X86MCCodeEmitter(MCII, Ctx); 1787 } 1788