1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file includes common code for rendering MCInst instances as Intel-style 10 // and Intel-style assembly. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstPrinterCommon.h" 15 #include "X86BaseInfo.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/Support/raw_ostream.h" 22 #include "llvm/Support/Casting.h" 23 #include <cstdint> 24 #include <cassert> 25 26 using namespace llvm; 27 28 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, 29 raw_ostream &O) { 30 int64_t Imm = MI->getOperand(Op).getImm(); 31 switch (Imm) { 32 default: llvm_unreachable("Invalid condcode argument!"); 33 case 0: O << "o"; break; 34 case 1: O << "no"; break; 35 case 2: O << "b"; break; 36 case 3: O << "ae"; break; 37 case 4: O << "e"; break; 38 case 5: O << "ne"; break; 39 case 6: O << "be"; break; 40 case 7: O << "a"; break; 41 case 8: O << "s"; break; 42 case 9: O << "ns"; break; 43 case 0xa: O << "p"; break; 44 case 0xb: O << "np"; break; 45 case 0xc: O << "l"; break; 46 case 0xd: O << "ge"; break; 47 case 0xe: O << "le"; break; 48 case 0xf: O << "g"; break; 49 } 50 } 51 52 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, 53 raw_ostream &O) { 54 int64_t Imm = MI->getOperand(Op).getImm(); 55 switch (Imm) { 56 default: llvm_unreachable("Invalid ssecc/avxcc argument!"); 57 case 0: O << "eq"; break; 58 case 1: O << "lt"; break; 59 case 2: O << "le"; break; 60 case 3: O << "unord"; break; 61 case 4: O << "neq"; break; 62 case 5: O << "nlt"; break; 63 case 6: O << "nle"; break; 64 case 7: O << "ord"; break; 65 case 8: O << "eq_uq"; break; 66 case 9: O << "nge"; break; 67 case 0xa: O << "ngt"; break; 68 case 0xb: O << "false"; break; 69 case 0xc: O << "neq_oq"; break; 70 case 0xd: O << "ge"; break; 71 case 0xe: O << "gt"; break; 72 case 0xf: O << "true"; break; 73 case 0x10: O << "eq_os"; break; 74 case 0x11: O << "lt_oq"; break; 75 case 0x12: O << "le_oq"; break; 76 case 0x13: O << "unord_s"; break; 77 case 0x14: O << "neq_us"; break; 78 case 0x15: O << "nlt_uq"; break; 79 case 0x16: O << "nle_uq"; break; 80 case 0x17: O << "ord_s"; break; 81 case 0x18: O << "eq_us"; break; 82 case 0x19: O << "nge_uq"; break; 83 case 0x1a: O << "ngt_uq"; break; 84 case 0x1b: O << "false_os"; break; 85 case 0x1c: O << "neq_os"; break; 86 case 0x1d: O << "ge_oq"; break; 87 case 0x1e: O << "gt_oq"; break; 88 case 0x1f: O << "true_us"; break; 89 } 90 } 91 92 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI, 93 raw_ostream &OS) { 94 OS << "vpcom"; 95 96 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); 97 switch (Imm) { 98 default: llvm_unreachable("Invalid vpcom argument!"); 99 case 0: OS << "lt"; break; 100 case 1: OS << "le"; break; 101 case 2: OS << "gt"; break; 102 case 3: OS << "ge"; break; 103 case 4: OS << "eq"; break; 104 case 5: OS << "neq"; break; 105 case 6: OS << "false"; break; 106 case 7: OS << "true"; break; 107 } 108 109 switch (MI->getOpcode()) { 110 default: llvm_unreachable("Unexpected opcode!"); 111 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; 112 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; 113 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; 114 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; 115 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; 116 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; 117 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; 118 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; 119 } 120 } 121 122 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI, 123 raw_ostream &OS) { 124 OS << "vpcmp"; 125 126 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 127 128 switch (MI->getOpcode()) { 129 default: llvm_unreachable("Unexpected opcode!"); 130 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: 131 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: 132 case X86::VPCMPBZrmi: case X86::VPCMPBZrri: 133 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: 134 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: 135 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: 136 OS << "b\t"; 137 break; 138 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: 139 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: 140 case X86::VPCMPDZrmi: case X86::VPCMPDZrri: 141 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: 142 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: 143 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: 144 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: 145 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: 146 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: 147 OS << "d\t"; 148 break; 149 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: 150 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: 151 case X86::VPCMPQZrmi: case X86::VPCMPQZrri: 152 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: 153 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: 154 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: 155 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: 156 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: 157 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: 158 OS << "q\t"; 159 break; 160 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: 161 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: 162 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: 163 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: 164 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: 165 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: 166 OS << "ub\t"; 167 break; 168 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: 169 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: 170 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: 171 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: 172 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: 173 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: 174 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: 175 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: 176 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: 177 OS << "ud\t"; 178 break; 179 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: 180 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: 181 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: 182 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: 183 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: 184 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: 185 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: 186 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: 187 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: 188 OS << "uq\t"; 189 break; 190 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: 191 case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi: 192 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: 193 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: 194 case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik: 195 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: 196 OS << "uw\t"; 197 break; 198 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: 199 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: 200 case X86::VPCMPWZrmi: case X86::VPCMPWZrri: 201 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: 202 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: 203 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: 204 OS << "w\t"; 205 break; 206 } 207 } 208 209 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp, 210 raw_ostream &OS) { 211 OS << (IsVCmp ? "vcmp" : "cmp"); 212 213 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 214 215 switch (MI->getOpcode()) { 216 default: llvm_unreachable("Unexpected opcode!"); 217 case X86::CMPPDrmi: case X86::CMPPDrri: 218 case X86::VCMPPDrmi: case X86::VCMPPDrri: 219 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: 220 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: 221 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: 222 case X86::VCMPPDZrmi: case X86::VCMPPDZrri: 223 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: 224 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: 225 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: 226 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: 227 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: 228 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: 229 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: 230 OS << "pd\t"; 231 break; 232 case X86::CMPPSrmi: case X86::CMPPSrri: 233 case X86::VCMPPSrmi: case X86::VCMPPSrri: 234 case X86::VCMPPSYrmi: case X86::VCMPPSYrri: 235 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: 236 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: 237 case X86::VCMPPSZrmi: case X86::VCMPPSZrri: 238 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: 239 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: 240 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: 241 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: 242 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: 243 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: 244 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: 245 OS << "ps\t"; 246 break; 247 case X86::CMPSDrm: case X86::CMPSDrr: 248 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: 249 case X86::VCMPSDrm: case X86::VCMPSDrr: 250 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: 251 case X86::VCMPSDZrm: case X86::VCMPSDZrr: 252 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: 253 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: 254 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: 255 OS << "sd\t"; 256 break; 257 case X86::CMPSSrm: case X86::CMPSSrr: 258 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: 259 case X86::VCMPSSrm: case X86::VCMPSSrr: 260 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: 261 case X86::VCMPSSZrm: case X86::VCMPSSZrr: 262 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: 263 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: 264 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: 265 OS << "ss\t"; 266 break; 267 } 268 } 269 270 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, 271 raw_ostream &O) { 272 int64_t Imm = MI->getOperand(Op).getImm(); 273 switch (Imm) { 274 default: 275 llvm_unreachable("Invalid rounding control!"); 276 case X86::TO_NEAREST_INT: 277 O << "{rn-sae}"; 278 break; 279 case X86::TO_NEG_INF: 280 O << "{rd-sae}"; 281 break; 282 case X86::TO_POS_INF: 283 O << "{ru-sae}"; 284 break; 285 case X86::TO_ZERO: 286 O << "{rz-sae}"; 287 break; 288 } 289 } 290 291 /// value (e.g. for jumps and calls). In Intel-style these print slightly 292 /// differently than normal immediates. For example, a $ is not emitted. 293 /// 294 /// \p Address The address of the next instruction. 295 /// \see MCInstPrinter::printInst 296 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address, 297 unsigned OpNo, raw_ostream &O) { 298 const MCOperand &Op = MI->getOperand(OpNo); 299 if (Op.isImm()) { 300 if (PrintBranchImmAsAddress) { 301 uint64_t Target = Address + Op.getImm(); 302 if (MAI.getCodePointerSize() == 4) 303 Target &= 0xffffffff; 304 O << formatHex(Target); 305 } else 306 O << formatImm(Op.getImm()); 307 } else { 308 assert(Op.isExpr() && "unknown pcrel immediate operand"); 309 // If a symbolic branch target was added as a constant expression then print 310 // that address in hex. 311 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 312 int64_t Address; 313 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 314 O << formatHex((uint64_t)Address); 315 } else { 316 // Otherwise, just print the expression. 317 Op.getExpr()->print(O, &MAI); 318 } 319 } 320 } 321 322 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, 323 raw_ostream &O) { 324 if (MI->getOperand(OpNo).getReg()) { 325 printOperand(MI, OpNo, O); 326 O << ':'; 327 } 328 } 329 330 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) { 331 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 332 uint64_t TSFlags = Desc.TSFlags; 333 unsigned Flags = MI->getFlags(); 334 335 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) 336 O << "\tlock\t"; 337 338 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) 339 O << "\tnotrack\t"; 340 341 if (Flags & X86::IP_HAS_REPEAT_NE) 342 O << "\trepne\t"; 343 else if (Flags & X86::IP_HAS_REPEAT) 344 O << "\trep\t"; 345 } 346 347 void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo, 348 raw_ostream &OS) { 349 // In assembly listings, a pair is represented by one of its members, any 350 // of the two. Here, we pick k0, k2, k4, k6, but we could as well 351 // print K2_K3 as "k3". It would probably make a lot more sense, if 352 // the assembly would look something like: 353 // "vp2intersect %zmm5, %zmm7, {%k2, %k3}" 354 // but this can work too. 355 switch (MI->getOperand(OpNo).getReg()) { 356 case X86::K0_K1: 357 printRegName(OS, X86::K0); 358 return; 359 case X86::K2_K3: 360 printRegName(OS, X86::K2); 361 return; 362 case X86::K4_K5: 363 printRegName(OS, X86::K4); 364 return; 365 case X86::K6_K7: 366 printRegName(OS, X86::K6); 367 return; 368 } 369 llvm_unreachable("Unknown mask pair register name"); 370 } 371