1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file includes common code for rendering MCInst instances as Intel-style 10 // and Intel-style assembly. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstPrinterCommon.h" 15 #include "X86BaseInfo.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Casting.h" 23 #include "llvm/Support/raw_ostream.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, 30 raw_ostream &O) { 31 int64_t Imm = MI->getOperand(Op).getImm(); 32 bool Flavor = MI->getOpcode() == X86::CMPCCXADDmr32 || 33 MI->getOpcode() == X86::CMPCCXADDmr64; 34 switch (Imm) { 35 default: llvm_unreachable("Invalid condcode argument!"); 36 case 0: O << "o"; break; 37 case 1: O << "no"; break; 38 case 2: O << "b"; break; 39 case 3: O << (Flavor ? "nb" : "ae"); break; 40 case 4: O << (Flavor ? "z" : "e"); break; 41 case 5: O << (Flavor ? "nz" : "ne"); break; 42 case 6: O << "be"; break; 43 case 7: O << (Flavor ? "nbe" : "a"); break; 44 case 8: O << "s"; break; 45 case 9: O << "ns"; break; 46 case 0xa: O << "p"; break; 47 case 0xb: O << "np"; break; 48 case 0xc: O << "l"; break; 49 case 0xd: O << (Flavor ? "nl" : "ge"); break; 50 case 0xe: O << "le"; break; 51 case 0xf: O << (Flavor ? "nle" : "g"); break; 52 } 53 } 54 55 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, 56 raw_ostream &O) { 57 int64_t Imm = MI->getOperand(Op).getImm(); 58 switch (Imm) { 59 default: llvm_unreachable("Invalid ssecc/avxcc argument!"); 60 case 0: O << "eq"; break; 61 case 1: O << "lt"; break; 62 case 2: O << "le"; break; 63 case 3: O << "unord"; break; 64 case 4: O << "neq"; break; 65 case 5: O << "nlt"; break; 66 case 6: O << "nle"; break; 67 case 7: O << "ord"; break; 68 case 8: O << "eq_uq"; break; 69 case 9: O << "nge"; break; 70 case 0xa: O << "ngt"; break; 71 case 0xb: O << "false"; break; 72 case 0xc: O << "neq_oq"; break; 73 case 0xd: O << "ge"; break; 74 case 0xe: O << "gt"; break; 75 case 0xf: O << "true"; break; 76 case 0x10: O << "eq_os"; break; 77 case 0x11: O << "lt_oq"; break; 78 case 0x12: O << "le_oq"; break; 79 case 0x13: O << "unord_s"; break; 80 case 0x14: O << "neq_us"; break; 81 case 0x15: O << "nlt_uq"; break; 82 case 0x16: O << "nle_uq"; break; 83 case 0x17: O << "ord_s"; break; 84 case 0x18: O << "eq_us"; break; 85 case 0x19: O << "nge_uq"; break; 86 case 0x1a: O << "ngt_uq"; break; 87 case 0x1b: O << "false_os"; break; 88 case 0x1c: O << "neq_os"; break; 89 case 0x1d: O << "ge_oq"; break; 90 case 0x1e: O << "gt_oq"; break; 91 case 0x1f: O << "true_us"; break; 92 } 93 } 94 95 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI, 96 raw_ostream &OS) { 97 OS << "vpcom"; 98 99 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); 100 switch (Imm) { 101 default: llvm_unreachable("Invalid vpcom argument!"); 102 case 0: OS << "lt"; break; 103 case 1: OS << "le"; break; 104 case 2: OS << "gt"; break; 105 case 3: OS << "ge"; break; 106 case 4: OS << "eq"; break; 107 case 5: OS << "neq"; break; 108 case 6: OS << "false"; break; 109 case 7: OS << "true"; break; 110 } 111 112 switch (MI->getOpcode()) { 113 default: llvm_unreachable("Unexpected opcode!"); 114 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; 115 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; 116 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; 117 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; 118 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; 119 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; 120 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; 121 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; 122 } 123 } 124 125 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI, 126 raw_ostream &OS) { 127 OS << "vpcmp"; 128 129 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 130 131 switch (MI->getOpcode()) { 132 default: llvm_unreachable("Unexpected opcode!"); 133 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: 134 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: 135 case X86::VPCMPBZrmi: case X86::VPCMPBZrri: 136 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: 137 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: 138 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: 139 OS << "b\t"; 140 break; 141 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: 142 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: 143 case X86::VPCMPDZrmi: case X86::VPCMPDZrri: 144 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: 145 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: 146 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: 147 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: 148 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: 149 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: 150 OS << "d\t"; 151 break; 152 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: 153 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: 154 case X86::VPCMPQZrmi: case X86::VPCMPQZrri: 155 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: 156 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: 157 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: 158 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: 159 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: 160 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: 161 OS << "q\t"; 162 break; 163 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: 164 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: 165 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: 166 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: 167 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: 168 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: 169 OS << "ub\t"; 170 break; 171 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: 172 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: 173 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: 174 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: 175 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: 176 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: 177 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: 178 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: 179 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: 180 OS << "ud\t"; 181 break; 182 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: 183 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: 184 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: 185 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: 186 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: 187 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: 188 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: 189 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: 190 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: 191 OS << "uq\t"; 192 break; 193 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: 194 case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi: 195 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: 196 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: 197 case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik: 198 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: 199 OS << "uw\t"; 200 break; 201 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: 202 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: 203 case X86::VPCMPWZrmi: case X86::VPCMPWZrri: 204 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: 205 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: 206 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: 207 OS << "w\t"; 208 break; 209 } 210 } 211 212 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp, 213 raw_ostream &OS) { 214 OS << (IsVCmp ? "vcmp" : "cmp"); 215 216 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 217 218 switch (MI->getOpcode()) { 219 default: llvm_unreachable("Unexpected opcode!"); 220 case X86::CMPPDrmi: case X86::CMPPDrri: 221 case X86::VCMPPDrmi: case X86::VCMPPDrri: 222 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: 223 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: 224 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: 225 case X86::VCMPPDZrmi: case X86::VCMPPDZrri: 226 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: 227 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: 228 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: 229 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: 230 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: 231 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: 232 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: 233 OS << "pd\t"; 234 break; 235 case X86::CMPPSrmi: case X86::CMPPSrri: 236 case X86::VCMPPSrmi: case X86::VCMPPSrri: 237 case X86::VCMPPSYrmi: case X86::VCMPPSYrri: 238 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: 239 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: 240 case X86::VCMPPSZrmi: case X86::VCMPPSZrri: 241 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: 242 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: 243 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: 244 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: 245 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: 246 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: 247 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: 248 OS << "ps\t"; 249 break; 250 case X86::CMPSDrm: case X86::CMPSDrr: 251 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: 252 case X86::VCMPSDrm: case X86::VCMPSDrr: 253 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: 254 case X86::VCMPSDZrm: case X86::VCMPSDZrr: 255 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: 256 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: 257 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: 258 OS << "sd\t"; 259 break; 260 case X86::CMPSSrm: case X86::CMPSSrr: 261 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: 262 case X86::VCMPSSrm: case X86::VCMPSSrr: 263 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: 264 case X86::VCMPSSZrm: case X86::VCMPSSZrr: 265 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: 266 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: 267 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: 268 OS << "ss\t"; 269 break; 270 case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri: 271 case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri: 272 case X86::VCMPPHZrmi: case X86::VCMPPHZrri: 273 case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik: 274 case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik: 275 case X86::VCMPPHZrmik: case X86::VCMPPHZrrik: 276 case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik: 277 case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik: 278 case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik: 279 case X86::VCMPPHZrrib: case X86::VCMPPHZrribk: 280 OS << "ph\t"; 281 break; 282 case X86::VCMPSHZrm: case X86::VCMPSHZrr: 283 case X86::VCMPSHZrm_Int: case X86::VCMPSHZrr_Int: 284 case X86::VCMPSHZrrb_Int: case X86::VCMPSHZrrb_Intk: 285 case X86::VCMPSHZrm_Intk: case X86::VCMPSHZrr_Intk: 286 OS << "sh\t"; 287 break; 288 } 289 } 290 291 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, 292 raw_ostream &O) { 293 int64_t Imm = MI->getOperand(Op).getImm(); 294 switch (Imm) { 295 default: 296 llvm_unreachable("Invalid rounding control!"); 297 case X86::TO_NEAREST_INT: 298 O << "{rn-sae}"; 299 break; 300 case X86::TO_NEG_INF: 301 O << "{rd-sae}"; 302 break; 303 case X86::TO_POS_INF: 304 O << "{ru-sae}"; 305 break; 306 case X86::TO_ZERO: 307 O << "{rz-sae}"; 308 break; 309 } 310 } 311 312 /// value (e.g. for jumps and calls). In Intel-style these print slightly 313 /// differently than normal immediates. For example, a $ is not emitted. 314 /// 315 /// \p Address The address of the next instruction. 316 /// \see MCInstPrinter::printInst 317 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address, 318 unsigned OpNo, raw_ostream &O) { 319 // Do not print the numberic target address when symbolizing. 320 if (SymbolizeOperands) 321 return; 322 323 const MCOperand &Op = MI->getOperand(OpNo); 324 if (Op.isImm()) { 325 O << markup("<imm:"); 326 if (PrintBranchImmAsAddress) { 327 uint64_t Target = Address + Op.getImm(); 328 if (MAI.getCodePointerSize() == 4) 329 Target &= 0xffffffff; 330 O << formatHex(Target); 331 } else 332 O << formatImm(Op.getImm()); 333 O << markup(">"); 334 } else { 335 assert(Op.isExpr() && "unknown pcrel immediate operand"); 336 // If a symbolic branch target was added as a constant expression then print 337 // that address in hex. 338 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 339 int64_t Address; 340 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 341 O << markup("<imm:") << formatHex((uint64_t)Address) << markup(">"); 342 } else { 343 // Otherwise, just print the expression. 344 Op.getExpr()->print(O, &MAI); 345 } 346 } 347 } 348 349 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, 350 raw_ostream &O) { 351 if (MI->getOperand(OpNo).getReg()) { 352 printOperand(MI, OpNo, O); 353 O << ':'; 354 } 355 } 356 357 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O, 358 const MCSubtargetInfo &STI) { 359 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 360 uint64_t TSFlags = Desc.TSFlags; 361 unsigned Flags = MI->getFlags(); 362 363 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) 364 O << "\tlock\t"; 365 366 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) 367 O << "\tnotrack\t"; 368 369 if (Flags & X86::IP_HAS_REPEAT_NE) 370 O << "\trepne\t"; 371 else if (Flags & X86::IP_HAS_REPEAT) 372 O << "\trep\t"; 373 374 // These all require a pseudo prefix 375 if ((Flags & X86::IP_USE_VEX) || (TSFlags & X86II::ExplicitVEXPrefix)) 376 O << "\t{vex}"; 377 else if (Flags & X86::IP_USE_VEX2) 378 O << "\t{vex2}"; 379 else if (Flags & X86::IP_USE_VEX3) 380 O << "\t{vex3}"; 381 else if (Flags & X86::IP_USE_EVEX) 382 O << "\t{evex}"; 383 384 if (Flags & X86::IP_USE_DISP8) 385 O << "\t{disp8}"; 386 else if (Flags & X86::IP_USE_DISP32) 387 O << "\t{disp32}"; 388 389 // Determine where the memory operand starts, if present 390 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); 391 if (MemoryOperand != -1) 392 MemoryOperand += X86II::getOperandBias(Desc); 393 394 // Address-Size override prefix 395 if (Flags & X86::IP_HAS_AD_SIZE && 396 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { 397 if (STI.hasFeature(X86::Is16Bit) || STI.hasFeature(X86::Is64Bit)) 398 O << "\taddr32\t"; 399 else if (STI.hasFeature(X86::Is32Bit)) 400 O << "\taddr16\t"; 401 } 402 } 403 404 void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo, 405 raw_ostream &OS) { 406 // In assembly listings, a pair is represented by one of its members, any 407 // of the two. Here, we pick k0, k2, k4, k6, but we could as well 408 // print K2_K3 as "k3". It would probably make a lot more sense, if 409 // the assembly would look something like: 410 // "vp2intersect %zmm5, %zmm7, {%k2, %k3}" 411 // but this can work too. 412 switch (MI->getOperand(OpNo).getReg()) { 413 case X86::K0_K1: 414 printRegName(OS, X86::K0); 415 return; 416 case X86::K2_K3: 417 printRegName(OS, X86::K2); 418 return; 419 case X86::K4_K5: 420 printRegName(OS, X86::K4); 421 return; 422 case X86::K6_K7: 423 printRegName(OS, X86::K6); 424 return; 425 } 426 llvm_unreachable("Unknown mask pair register name"); 427 } 428