1 //===--- X86InstPrinterCommon.cpp - X86 assembly instruction printing -----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file includes common code for rendering MCInst instances as Intel-style 10 // and Intel-style assembly. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86InstPrinterCommon.h" 15 #include "X86BaseInfo.h" 16 #include "llvm/MC/MCAsmInfo.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/Support/Casting.h" 23 #include "llvm/Support/raw_ostream.h" 24 #include <cassert> 25 #include <cstdint> 26 27 using namespace llvm; 28 29 void X86InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op, 30 raw_ostream &O) { 31 int64_t Imm = MI->getOperand(Op).getImm(); 32 bool Flavor = MI->getOpcode() == X86::CMPCCXADDmr32 || 33 MI->getOpcode() == X86::CMPCCXADDmr64 || 34 MI->getOpcode() == X86::CMPCCXADDmr32_EVEX || 35 MI->getOpcode() == X86::CMPCCXADDmr64_EVEX; 36 switch (Imm) { 37 default: llvm_unreachable("Invalid condcode argument!"); 38 case 0: O << "o"; break; 39 case 1: O << "no"; break; 40 case 2: O << "b"; break; 41 case 3: O << (Flavor ? "nb" : "ae"); break; 42 case 4: O << (Flavor ? "z" : "e"); break; 43 case 5: O << (Flavor ? "nz" : "ne"); break; 44 case 6: O << "be"; break; 45 case 7: O << (Flavor ? "nbe" : "a"); break; 46 case 8: O << "s"; break; 47 case 9: O << "ns"; break; 48 case 0xa: O << "p"; break; 49 case 0xb: O << "np"; break; 50 case 0xc: O << "l"; break; 51 case 0xd: O << (Flavor ? "nl" : "ge"); break; 52 case 0xe: O << "le"; break; 53 case 0xf: O << (Flavor ? "nle" : "g"); break; 54 } 55 } 56 57 void X86InstPrinterCommon::printSSEAVXCC(const MCInst *MI, unsigned Op, 58 raw_ostream &O) { 59 int64_t Imm = MI->getOperand(Op).getImm(); 60 switch (Imm) { 61 default: llvm_unreachable("Invalid ssecc/avxcc argument!"); 62 case 0: O << "eq"; break; 63 case 1: O << "lt"; break; 64 case 2: O << "le"; break; 65 case 3: O << "unord"; break; 66 case 4: O << "neq"; break; 67 case 5: O << "nlt"; break; 68 case 6: O << "nle"; break; 69 case 7: O << "ord"; break; 70 case 8: O << "eq_uq"; break; 71 case 9: O << "nge"; break; 72 case 0xa: O << "ngt"; break; 73 case 0xb: O << "false"; break; 74 case 0xc: O << "neq_oq"; break; 75 case 0xd: O << "ge"; break; 76 case 0xe: O << "gt"; break; 77 case 0xf: O << "true"; break; 78 case 0x10: O << "eq_os"; break; 79 case 0x11: O << "lt_oq"; break; 80 case 0x12: O << "le_oq"; break; 81 case 0x13: O << "unord_s"; break; 82 case 0x14: O << "neq_us"; break; 83 case 0x15: O << "nlt_uq"; break; 84 case 0x16: O << "nle_uq"; break; 85 case 0x17: O << "ord_s"; break; 86 case 0x18: O << "eq_us"; break; 87 case 0x19: O << "nge_uq"; break; 88 case 0x1a: O << "ngt_uq"; break; 89 case 0x1b: O << "false_os"; break; 90 case 0x1c: O << "neq_os"; break; 91 case 0x1d: O << "ge_oq"; break; 92 case 0x1e: O << "gt_oq"; break; 93 case 0x1f: O << "true_us"; break; 94 } 95 } 96 97 void X86InstPrinterCommon::printVPCOMMnemonic(const MCInst *MI, 98 raw_ostream &OS) { 99 OS << "vpcom"; 100 101 int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm(); 102 switch (Imm) { 103 default: llvm_unreachable("Invalid vpcom argument!"); 104 case 0: OS << "lt"; break; 105 case 1: OS << "le"; break; 106 case 2: OS << "gt"; break; 107 case 3: OS << "ge"; break; 108 case 4: OS << "eq"; break; 109 case 5: OS << "neq"; break; 110 case 6: OS << "false"; break; 111 case 7: OS << "true"; break; 112 } 113 114 switch (MI->getOpcode()) { 115 default: llvm_unreachable("Unexpected opcode!"); 116 case X86::VPCOMBmi: case X86::VPCOMBri: OS << "b\t"; break; 117 case X86::VPCOMDmi: case X86::VPCOMDri: OS << "d\t"; break; 118 case X86::VPCOMQmi: case X86::VPCOMQri: OS << "q\t"; break; 119 case X86::VPCOMUBmi: case X86::VPCOMUBri: OS << "ub\t"; break; 120 case X86::VPCOMUDmi: case X86::VPCOMUDri: OS << "ud\t"; break; 121 case X86::VPCOMUQmi: case X86::VPCOMUQri: OS << "uq\t"; break; 122 case X86::VPCOMUWmi: case X86::VPCOMUWri: OS << "uw\t"; break; 123 case X86::VPCOMWmi: case X86::VPCOMWri: OS << "w\t"; break; 124 } 125 } 126 127 void X86InstPrinterCommon::printVPCMPMnemonic(const MCInst *MI, 128 raw_ostream &OS) { 129 OS << "vpcmp"; 130 131 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 132 133 switch (MI->getOpcode()) { 134 default: llvm_unreachable("Unexpected opcode!"); 135 case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri: 136 case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri: 137 case X86::VPCMPBZrmi: case X86::VPCMPBZrri: 138 case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik: 139 case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik: 140 case X86::VPCMPBZrmik: case X86::VPCMPBZrrik: 141 OS << "b\t"; 142 break; 143 case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri: 144 case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri: 145 case X86::VPCMPDZrmi: case X86::VPCMPDZrri: 146 case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik: 147 case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik: 148 case X86::VPCMPDZrmik: case X86::VPCMPDZrrik: 149 case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk: 150 case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk: 151 case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk: 152 OS << "d\t"; 153 break; 154 case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri: 155 case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri: 156 case X86::VPCMPQZrmi: case X86::VPCMPQZrri: 157 case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik: 158 case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik: 159 case X86::VPCMPQZrmik: case X86::VPCMPQZrrik: 160 case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk: 161 case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk: 162 case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk: 163 OS << "q\t"; 164 break; 165 case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri: 166 case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri: 167 case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri: 168 case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik: 169 case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik: 170 case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik: 171 OS << "ub\t"; 172 break; 173 case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri: 174 case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri: 175 case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri: 176 case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik: 177 case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik: 178 case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik: 179 case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk: 180 case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk: 181 case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk: 182 OS << "ud\t"; 183 break; 184 case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri: 185 case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri: 186 case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri: 187 case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik: 188 case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik: 189 case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik: 190 case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk: 191 case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk: 192 case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk: 193 OS << "uq\t"; 194 break; 195 case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri: 196 case X86::VPCMPUWZ256rri: case X86::VPCMPUWZ256rmi: 197 case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri: 198 case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik: 199 case X86::VPCMPUWZ256rrik: case X86::VPCMPUWZ256rmik: 200 case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik: 201 OS << "uw\t"; 202 break; 203 case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri: 204 case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri: 205 case X86::VPCMPWZrmi: case X86::VPCMPWZrri: 206 case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik: 207 case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik: 208 case X86::VPCMPWZrmik: case X86::VPCMPWZrrik: 209 OS << "w\t"; 210 break; 211 } 212 } 213 214 void X86InstPrinterCommon::printCMPMnemonic(const MCInst *MI, bool IsVCmp, 215 raw_ostream &OS) { 216 OS << (IsVCmp ? "vcmp" : "cmp"); 217 218 printSSEAVXCC(MI, MI->getNumOperands() - 1, OS); 219 220 switch (MI->getOpcode()) { 221 default: llvm_unreachable("Unexpected opcode!"); 222 case X86::CMPPDrmi: case X86::CMPPDrri: 223 case X86::VCMPPDrmi: case X86::VCMPPDrri: 224 case X86::VCMPPDYrmi: case X86::VCMPPDYrri: 225 case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri: 226 case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri: 227 case X86::VCMPPDZrmi: case X86::VCMPPDZrri: 228 case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik: 229 case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik: 230 case X86::VCMPPDZrmik: case X86::VCMPPDZrrik: 231 case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik: 232 case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik: 233 case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik: 234 case X86::VCMPPDZrrib: case X86::VCMPPDZrribk: 235 OS << "pd\t"; 236 break; 237 case X86::CMPPSrmi: case X86::CMPPSrri: 238 case X86::VCMPPSrmi: case X86::VCMPPSrri: 239 case X86::VCMPPSYrmi: case X86::VCMPPSYrri: 240 case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri: 241 case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri: 242 case X86::VCMPPSZrmi: case X86::VCMPPSZrri: 243 case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik: 244 case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik: 245 case X86::VCMPPSZrmik: case X86::VCMPPSZrrik: 246 case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik: 247 case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik: 248 case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik: 249 case X86::VCMPPSZrrib: case X86::VCMPPSZrribk: 250 OS << "ps\t"; 251 break; 252 case X86::CMPSDrm: case X86::CMPSDrr: 253 case X86::CMPSDrm_Int: case X86::CMPSDrr_Int: 254 case X86::VCMPSDrm: case X86::VCMPSDrr: 255 case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int: 256 case X86::VCMPSDZrm: case X86::VCMPSDZrr: 257 case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int: 258 case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk: 259 case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk: 260 OS << "sd\t"; 261 break; 262 case X86::CMPSSrm: case X86::CMPSSrr: 263 case X86::CMPSSrm_Int: case X86::CMPSSrr_Int: 264 case X86::VCMPSSrm: case X86::VCMPSSrr: 265 case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int: 266 case X86::VCMPSSZrm: case X86::VCMPSSZrr: 267 case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int: 268 case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk: 269 case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk: 270 OS << "ss\t"; 271 break; 272 case X86::VCMPPHZ128rmi: case X86::VCMPPHZ128rri: 273 case X86::VCMPPHZ256rmi: case X86::VCMPPHZ256rri: 274 case X86::VCMPPHZrmi: case X86::VCMPPHZrri: 275 case X86::VCMPPHZ128rmik: case X86::VCMPPHZ128rrik: 276 case X86::VCMPPHZ256rmik: case X86::VCMPPHZ256rrik: 277 case X86::VCMPPHZrmik: case X86::VCMPPHZrrik: 278 case X86::VCMPPHZ128rmbi: case X86::VCMPPHZ128rmbik: 279 case X86::VCMPPHZ256rmbi: case X86::VCMPPHZ256rmbik: 280 case X86::VCMPPHZrmbi: case X86::VCMPPHZrmbik: 281 case X86::VCMPPHZrrib: case X86::VCMPPHZrribk: 282 OS << "ph\t"; 283 break; 284 case X86::VCMPSHZrm: case X86::VCMPSHZrr: 285 case X86::VCMPSHZrm_Int: case X86::VCMPSHZrr_Int: 286 case X86::VCMPSHZrrb_Int: case X86::VCMPSHZrrb_Intk: 287 case X86::VCMPSHZrm_Intk: case X86::VCMPSHZrr_Intk: 288 OS << "sh\t"; 289 break; 290 } 291 } 292 293 void X86InstPrinterCommon::printRoundingControl(const MCInst *MI, unsigned Op, 294 raw_ostream &O) { 295 int64_t Imm = MI->getOperand(Op).getImm(); 296 switch (Imm) { 297 default: 298 llvm_unreachable("Invalid rounding control!"); 299 case X86::TO_NEAREST_INT: 300 O << "{rn-sae}"; 301 break; 302 case X86::TO_NEG_INF: 303 O << "{rd-sae}"; 304 break; 305 case X86::TO_POS_INF: 306 O << "{ru-sae}"; 307 break; 308 case X86::TO_ZERO: 309 O << "{rz-sae}"; 310 break; 311 } 312 } 313 314 /// value (e.g. for jumps and calls). In Intel-style these print slightly 315 /// differently than normal immediates. For example, a $ is not emitted. 316 /// 317 /// \p Address The address of the next instruction. 318 /// \see MCInstPrinter::printInst 319 void X86InstPrinterCommon::printPCRelImm(const MCInst *MI, uint64_t Address, 320 unsigned OpNo, raw_ostream &O) { 321 // Do not print the numberic target address when symbolizing. 322 if (SymbolizeOperands) 323 return; 324 325 const MCOperand &Op = MI->getOperand(OpNo); 326 if (Op.isImm()) { 327 if (PrintBranchImmAsAddress) { 328 uint64_t Target = Address + Op.getImm(); 329 if (MAI.getCodePointerSize() == 4) 330 Target &= 0xffffffff; 331 markup(O, Markup::Target) << formatHex(Target); 332 } else 333 markup(O, Markup::Immediate) << formatImm(Op.getImm()); 334 } else { 335 assert(Op.isExpr() && "unknown pcrel immediate operand"); 336 // If a symbolic branch target was added as a constant expression then print 337 // that address in hex. 338 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 339 int64_t Address; 340 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) { 341 markup(O, Markup::Immediate) << formatHex((uint64_t)Address); 342 } else { 343 // Otherwise, just print the expression. 344 Op.getExpr()->print(O, &MAI); 345 } 346 } 347 } 348 349 void X86InstPrinterCommon::printOptionalSegReg(const MCInst *MI, unsigned OpNo, 350 raw_ostream &O) { 351 if (MI->getOperand(OpNo).getReg()) { 352 printOperand(MI, OpNo, O); 353 O << ':'; 354 } 355 } 356 357 void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O, 358 const MCSubtargetInfo &STI) { 359 const MCInstrDesc &Desc = MII.get(MI->getOpcode()); 360 uint64_t TSFlags = Desc.TSFlags; 361 unsigned Flags = MI->getFlags(); 362 363 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK)) 364 O << "\tlock\t"; 365 366 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK)) 367 O << "\tnotrack\t"; 368 369 if (Flags & X86::IP_HAS_REPEAT_NE) 370 O << "\trepne\t"; 371 else if (Flags & X86::IP_HAS_REPEAT) 372 O << "\trep\t"; 373 374 if (TSFlags & X86II::EVEX_NF) 375 O << "\t{nf}"; 376 377 // These all require a pseudo prefix 378 if ((Flags & X86::IP_USE_VEX) || 379 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitVEXPrefix) 380 O << "\t{vex}"; 381 else if (Flags & X86::IP_USE_VEX2) 382 O << "\t{vex2}"; 383 else if (Flags & X86::IP_USE_VEX3) 384 O << "\t{vex3}"; 385 else if ((Flags & X86::IP_USE_EVEX) || 386 (TSFlags & X86II::ExplicitOpPrefixMask) == X86II::ExplicitEVEXPrefix) 387 O << "\t{evex}"; 388 389 if (Flags & X86::IP_USE_DISP8) 390 O << "\t{disp8}"; 391 else if (Flags & X86::IP_USE_DISP32) 392 O << "\t{disp32}"; 393 394 // Determine where the memory operand starts, if present 395 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags); 396 if (MemoryOperand != -1) 397 MemoryOperand += X86II::getOperandBias(Desc); 398 399 // Address-Size override prefix 400 if (Flags & X86::IP_HAS_AD_SIZE && 401 !X86_MC::needsAddressSizeOverride(*MI, STI, MemoryOperand, TSFlags)) { 402 if (STI.hasFeature(X86::Is16Bit) || STI.hasFeature(X86::Is64Bit)) 403 O << "\taddr32\t"; 404 else if (STI.hasFeature(X86::Is32Bit)) 405 O << "\taddr16\t"; 406 } 407 } 408 409 void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo, 410 raw_ostream &OS) { 411 // In assembly listings, a pair is represented by one of its members, any 412 // of the two. Here, we pick k0, k2, k4, k6, but we could as well 413 // print K2_K3 as "k3". It would probably make a lot more sense, if 414 // the assembly would look something like: 415 // "vp2intersect %zmm5, %zmm7, {%k2, %k3}" 416 // but this can work too. 417 switch (MI->getOperand(OpNo).getReg()) { 418 case X86::K0_K1: 419 printRegName(OS, X86::K0); 420 return; 421 case X86::K2_K3: 422 printRegName(OS, X86::K2); 423 return; 424 case X86::K4_K5: 425 printRegName(OS, X86::K4); 426 return; 427 case X86::K6_K7: 428 printRegName(OS, X86::K6); 429 return; 430 } 431 llvm_unreachable("Unknown mask pair register name"); 432 } 433