1*0b57cec5SDimitry Andric //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric /// 9*0b57cec5SDimitry Andric /// \file 10*0b57cec5SDimitry Andric /// This file implements the WebAssembly-specific subclass of 11*0b57cec5SDimitry Andric /// TargetSubtarget. 12*0b57cec5SDimitry Andric /// 13*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric #include "WebAssemblySubtarget.h" 16*0b57cec5SDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h" 17*0b57cec5SDimitry Andric #include "WebAssemblyInstrInfo.h" 18*0b57cec5SDimitry Andric #include "llvm/Support/TargetRegistry.h" 19*0b57cec5SDimitry Andric using namespace llvm; 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-subtarget" 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric #define GET_SUBTARGETINFO_CTOR 24*0b57cec5SDimitry Andric #define GET_SUBTARGETINFO_TARGET_DESC 25*0b57cec5SDimitry Andric #include "WebAssemblyGenSubtargetInfo.inc" 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric WebAssemblySubtarget & 28*0b57cec5SDimitry Andric WebAssemblySubtarget::initializeSubtargetDependencies(StringRef FS) { 29*0b57cec5SDimitry Andric // Determine default and user-specified characteristics 30*0b57cec5SDimitry Andric 31*0b57cec5SDimitry Andric if (CPUString.empty()) 32*0b57cec5SDimitry Andric CPUString = "generic"; 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andric ParseSubtargetFeatures(CPUString, FS); 35*0b57cec5SDimitry Andric return *this; 36*0b57cec5SDimitry Andric } 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT, 39*0b57cec5SDimitry Andric const std::string &CPU, 40*0b57cec5SDimitry Andric const std::string &FS, 41*0b57cec5SDimitry Andric const TargetMachine &TM) 42*0b57cec5SDimitry Andric : WebAssemblyGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), 43*0b57cec5SDimitry Andric TargetTriple(TT), FrameLowering(), 44*0b57cec5SDimitry Andric InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), 45*0b57cec5SDimitry Andric TLInfo(TM, *this) {} 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andric bool WebAssemblySubtarget::enableAtomicExpand() const { 48*0b57cec5SDimitry Andric // If atomics are disabled, atomic ops are lowered instead of expanded 49*0b57cec5SDimitry Andric return hasAtomics(); 50*0b57cec5SDimitry Andric } 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric bool WebAssemblySubtarget::enableMachineScheduler() const { 53*0b57cec5SDimitry Andric // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and 54*0b57cec5SDimitry Andric // enableMachineSchedDefaultSched overridden, it appears to have an overall 55*0b57cec5SDimitry Andric // negative effect for the kinds of register optimizations we're doing. 56*0b57cec5SDimitry Andric return false; 57*0b57cec5SDimitry Andric } 58*0b57cec5SDimitry Andric 59*0b57cec5SDimitry Andric bool WebAssemblySubtarget::useAA() const { return true; } 60