10b57cec5SDimitry Andric //===-- WebAssemblySubtarget.cpp - WebAssembly Subtarget Information ------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric ///
90b57cec5SDimitry Andric /// \file
100b57cec5SDimitry Andric /// This file implements the WebAssembly-specific subclass of
110b57cec5SDimitry Andric /// TargetSubtarget.
120b57cec5SDimitry Andric ///
130b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
140b57cec5SDimitry Andric
150b57cec5SDimitry Andric #include "WebAssemblySubtarget.h"
160b57cec5SDimitry Andric #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
170b57cec5SDimitry Andric #include "WebAssemblyInstrInfo.h"
18349cc55cSDimitry Andric #include "llvm/MC/TargetRegistry.h"
190b57cec5SDimitry Andric using namespace llvm;
200b57cec5SDimitry Andric
210b57cec5SDimitry Andric #define DEBUG_TYPE "wasm-subtarget"
220b57cec5SDimitry Andric
230b57cec5SDimitry Andric #define GET_SUBTARGETINFO_CTOR
240b57cec5SDimitry Andric #define GET_SUBTARGETINFO_TARGET_DESC
250b57cec5SDimitry Andric #include "WebAssemblyGenSubtargetInfo.inc"
260b57cec5SDimitry Andric
270b57cec5SDimitry Andric WebAssemblySubtarget &
initializeSubtargetDependencies(StringRef CPU,StringRef FS)285ffd83dbSDimitry Andric WebAssemblySubtarget::initializeSubtargetDependencies(StringRef CPU,
295ffd83dbSDimitry Andric StringRef FS) {
300b57cec5SDimitry Andric // Determine default and user-specified characteristics
315ffd83dbSDimitry Andric LLVM_DEBUG(llvm::dbgs() << "initializeSubtargetDependencies\n");
320b57cec5SDimitry Andric
335ffd83dbSDimitry Andric if (CPU.empty())
345ffd83dbSDimitry Andric CPU = "generic";
350b57cec5SDimitry Andric
36e8d8bef9SDimitry Andric ParseSubtargetFeatures(CPU, /*TuneCPU*/ CPU, FS);
370b57cec5SDimitry Andric return *this;
380b57cec5SDimitry Andric }
390b57cec5SDimitry Andric
WebAssemblySubtarget(const Triple & TT,const std::string & CPU,const std::string & FS,const TargetMachine & TM)400b57cec5SDimitry Andric WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
410b57cec5SDimitry Andric const std::string &CPU,
420b57cec5SDimitry Andric const std::string &FS,
430b57cec5SDimitry Andric const TargetMachine &TM)
44e8d8bef9SDimitry Andric : WebAssemblyGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS),
45*04eeddc0SDimitry Andric TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)),
46e8d8bef9SDimitry Andric TLInfo(TM, *this) {}
470b57cec5SDimitry Andric
enableAtomicExpand() const480b57cec5SDimitry Andric bool WebAssemblySubtarget::enableAtomicExpand() const {
490b57cec5SDimitry Andric // If atomics are disabled, atomic ops are lowered instead of expanded
500b57cec5SDimitry Andric return hasAtomics();
510b57cec5SDimitry Andric }
520b57cec5SDimitry Andric
enableMachineScheduler() const530b57cec5SDimitry Andric bool WebAssemblySubtarget::enableMachineScheduler() const {
540b57cec5SDimitry Andric // Disable the MachineScheduler for now. Even with ShouldTrackPressure set and
550b57cec5SDimitry Andric // enableMachineSchedDefaultSched overridden, it appears to have an overall
560b57cec5SDimitry Andric // negative effect for the kinds of register optimizations we're doing.
570b57cec5SDimitry Andric return false;
580b57cec5SDimitry Andric }
590b57cec5SDimitry Andric
useAA() const600b57cec5SDimitry Andric bool WebAssemblySubtarget::useAA() const { return true; }
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