1*0b57cec5SDimitry Andric//WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*- 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric/// 9*0b57cec5SDimitry Andric/// \file 10*0b57cec5SDimitry Andric/// This file describes the WebAssembly register classes and some nominal 11*0b57cec5SDimitry Andric/// physical registers. 12*0b57cec5SDimitry Andric/// 13*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andricclass WebAssemblyReg<string n> : Register<n> { 16*0b57cec5SDimitry Andric let Namespace = "WebAssembly"; 17*0b57cec5SDimitry Andric} 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andricclass WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList> 20*0b57cec5SDimitry Andric : RegisterClass<"WebAssembly", regTypes, alignment, regList>; 21*0b57cec5SDimitry Andric 22*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 23*0b57cec5SDimitry Andric// Registers 24*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 25*0b57cec5SDimitry Andric 26*0b57cec5SDimitry Andric// Special registers used as the frame and stack pointer. 27*0b57cec5SDimitry Andric// 28*0b57cec5SDimitry Andric// WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same 29*0b57cec5SDimitry Andric// application, which requires separate width FP and SP. 30*0b57cec5SDimitry Andricdef FP32 : WebAssemblyReg<"%FP32">; 31*0b57cec5SDimitry Andricdef FP64 : WebAssemblyReg<"%FP64">; 32*0b57cec5SDimitry Andricdef SP32 : WebAssemblyReg<"%SP32">; 33*0b57cec5SDimitry Andricdef SP64 : WebAssemblyReg<"%SP64">; 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric// The register allocation framework requires register classes have at least 36*0b57cec5SDimitry Andric// one register, so we define a few for the integer / floating point register 37*0b57cec5SDimitry Andric// classes since we otherwise don't need a physical register in those classes. 38*0b57cec5SDimitry Andric// These are also used a "types" in the generated assembly matcher. 39*0b57cec5SDimitry Andricdef I32_0 : WebAssemblyReg<"%i32.0">; 40*0b57cec5SDimitry Andricdef I64_0 : WebAssemblyReg<"%i64.0">; 41*0b57cec5SDimitry Andricdef F32_0 : WebAssemblyReg<"%f32.0">; 42*0b57cec5SDimitry Andricdef F64_0 : WebAssemblyReg<"%f64.0">; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andricdef V128_0: WebAssemblyReg<"%v128">; 45*0b57cec5SDimitry Andric 46*0b57cec5SDimitry Andricdef EXNREF_0 : WebAssemblyReg<"%exnref.0">; 47*0b57cec5SDimitry Andric 48*0b57cec5SDimitry Andric// The value stack "register". This is an opaque entity which serves to order 49*0b57cec5SDimitry Andric// uses and defs that must remain in LIFO order. 50*0b57cec5SDimitry Andricdef VALUE_STACK : WebAssemblyReg<"STACK">; 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric// The incoming arguments "register". This is an opaque entity which serves to 53*0b57cec5SDimitry Andric// order the ARGUMENT instructions that are emulating live-in registers and 54*0b57cec5SDimitry Andric// must not be scheduled below other instructions. 55*0b57cec5SDimitry Andricdef ARGUMENTS : WebAssemblyReg<"ARGUMENTS">; 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 58*0b57cec5SDimitry Andric// Register classes 59*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 60*0b57cec5SDimitry Andric 61*0b57cec5SDimitry Andricdef I32 : WebAssemblyRegClass<[i32], 32, (add FP32, SP32, I32_0)>; 62*0b57cec5SDimitry Andricdef I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>; 63*0b57cec5SDimitry Andricdef F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>; 64*0b57cec5SDimitry Andricdef F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>; 65*0b57cec5SDimitry Andricdef V128 : WebAssemblyRegClass<[v4f32, v2f64, v2i64, v4i32, v16i8, v8i16], 128, 66*0b57cec5SDimitry Andric (add V128_0)>; 67*0b57cec5SDimitry Andricdef EXNREF : WebAssemblyRegClass<[exnref], 0, (add EXNREF_0)>; 68