1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions requiring HasSIMD128 and the simd128 prefix byte 15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 16 list<dag> pattern_r, string asmstr_r = "", 17 string asmstr_s = "", bits<32> simdop = -1> { 18 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 19 !or(0xfd00, !and(0xff, simdop))>, 20 Requires<[HasSIMD128]>; 21} 22 23defm "" : ARGUMENT<V128, v16i8>; 24defm "" : ARGUMENT<V128, v8i16>; 25defm "" : ARGUMENT<V128, v4i32>; 26defm "" : ARGUMENT<V128, v2i64>; 27defm "" : ARGUMENT<V128, v4f32>; 28defm "" : ARGUMENT<V128, v2f64>; 29 30// Constrained immediate argument types 31foreach SIZE = [8, 16] in 32def ImmI#SIZE : ImmLeaf<i32, 33 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 34>; 35foreach SIZE = [2, 4, 8, 16, 32] in 36def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 37 38//===----------------------------------------------------------------------===// 39// Load and store 40//===----------------------------------------------------------------------===// 41 42// Load: v128.load 43let mayLoad = 1, UseNamedOperandTable = 1 in 44defm LOAD_V128 : 45 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 46 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 47 "v128.load\t$dst, ${off}(${addr})$p2align", 48 "v128.load\t$off$p2align", 0>; 49 50// Def load and store patterns from WebAssemblyInstrMemory.td for vector types 51foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 52def : LoadPatNoOffset<vec_t, load, LOAD_V128>; 53def : LoadPatImmOff<vec_t, load, regPlusImm, LOAD_V128>; 54def : LoadPatImmOff<vec_t, load, or_is_add, LOAD_V128>; 55def : LoadPatOffsetOnly<vec_t, load, LOAD_V128>; 56def : LoadPatGlobalAddrOffOnly<vec_t, load, LOAD_V128>; 57} 58 59// vNxM.load_splat 60multiclass SIMDLoadSplat<string vec, bits<32> simdop> { 61 let mayLoad = 1, UseNamedOperandTable = 1, 62 Predicates = [HasUnimplementedSIMD128] in 63 defm LOAD_SPLAT_#vec : 64 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 65 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 66 vec#".load_splat\t$dst, ${off}(${addr})$p2align", 67 vec#".load_splat\t$off$p2align", simdop>; 68} 69 70defm "" : SIMDLoadSplat<"v8x16", 194>; 71defm "" : SIMDLoadSplat<"v16x8", 195>; 72defm "" : SIMDLoadSplat<"v32x4", 196>; 73defm "" : SIMDLoadSplat<"v64x2", 197>; 74 75def wasm_load_splat_t : SDTypeProfile<1, 1, []>; 76def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t>; 77 78foreach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32", "extloadi16"], 79 ["v4i32", "i32", "load"], ["v2i64", "i64", "load"], 80 ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in 81def load_splat_#args[0] : 82 PatFrag<(ops node:$addr), (wasm_load_splat 83 (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2]) node:$addr)))>; 84 85let Predicates = [HasUnimplementedSIMD128] in 86foreach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"], 87 ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in { 88def : LoadPatNoOffset<!cast<ValueType>(args[0]), 89 !cast<PatFrag>("load_splat_"#args[0]), 90 !cast<NI>("LOAD_SPLAT_"#args[1])>; 91def : LoadPatImmOff<!cast<ValueType>(args[0]), 92 !cast<PatFrag>("load_splat_"#args[0]), 93 regPlusImm, 94 !cast<NI>("LOAD_SPLAT_"#args[1])>; 95def : LoadPatImmOff<!cast<ValueType>(args[0]), 96 !cast<PatFrag>("load_splat_"#args[0]), 97 or_is_add, 98 !cast<NI>("LOAD_SPLAT_"#args[1])>; 99def : LoadPatOffsetOnly<!cast<ValueType>(args[0]), 100 !cast<PatFrag>("load_splat_"#args[0]), 101 !cast<NI>("LOAD_SPLAT_"#args[1])>; 102def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]), 103 !cast<PatFrag>("load_splat_"#args[0]), 104 !cast<NI>("LOAD_SPLAT_"#args[1])>; 105} 106 107// Load and extend 108multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> { 109 let mayLoad = 1, UseNamedOperandTable = 1, 110 Predicates = [HasUnimplementedSIMD128] in { 111 defm LOAD_EXTEND_S_#vec_t : 112 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 113 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 114 name#"_s\t$dst, ${off}(${addr})$p2align", 115 name#"_s\t$off$p2align", simdop>; 116 defm LOAD_EXTEND_U_#vec_t : 117 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 118 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 119 name#"_u\t$dst, ${off}(${addr})$p2align", 120 name#"_u\t$off$p2align", !add(simdop, 1)>; 121 } 122} 123 124defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 210>; 125defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>; 126defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 214>; 127 128let Predicates = [HasUnimplementedSIMD128] in 129foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in 130foreach exts = [["sextloadv", "_S"], 131 ["zextloadv", "_U"], 132 ["extloadv", "_U"]] in { 133def : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]), 134 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 135def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm, 136 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 137def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add, 138 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 139def : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 140 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 141def : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]), 142 !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>; 143} 144 145 146// Store: v128.store 147let mayStore = 1, UseNamedOperandTable = 1 in 148defm STORE_V128 : 149 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 150 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 151 "v128.store\t${off}(${addr})$p2align, $vec", 152 "v128.store\t$off$p2align", 1>; 153 154foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 155// Def load and store patterns from WebAssemblyInstrMemory.td for vector types 156def : StorePatNoOffset<vec_t, store, STORE_V128>; 157def : StorePatImmOff<vec_t, store, regPlusImm, STORE_V128>; 158def : StorePatImmOff<vec_t, store, or_is_add, STORE_V128>; 159def : StorePatOffsetOnly<vec_t, store, STORE_V128>; 160def : StorePatGlobalAddrOffOnly<vec_t, store, STORE_V128>; 161} 162 163//===----------------------------------------------------------------------===// 164// Constructing SIMD values 165//===----------------------------------------------------------------------===// 166 167// Constant: v128.const 168multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> { 169 let isMoveImm = 1, isReMaterializable = 1, 170 Predicates = [HasUnimplementedSIMD128] in 171 defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops, 172 [(set V128:$dst, (vec_t pat))], 173 "v128.const\t$dst, "#args, 174 "v128.const\t"#args, 2>; 175} 176 177defm "" : ConstVec<v16i8, 178 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 179 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 180 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 181 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 182 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 183 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 184 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 185 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 186 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 187 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 188 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 189 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 190 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 191 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 192defm "" : ConstVec<v8i16, 193 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 194 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 195 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 196 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 197 (build_vector 198 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 199 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 200 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 201let IsCanonical = 1 in 202defm "" : ConstVec<v4i32, 203 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 204 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 205 (build_vector (i32 imm:$i0), (i32 imm:$i1), 206 (i32 imm:$i2), (i32 imm:$i3)), 207 "$i0, $i1, $i2, $i3">; 208defm "" : ConstVec<v2i64, 209 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 210 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 211 "$i0, $i1">; 212defm "" : ConstVec<v4f32, 213 (ins f32imm_op:$i0, f32imm_op:$i1, 214 f32imm_op:$i2, f32imm_op:$i3), 215 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 216 (f32 fpimm:$i2), (f32 fpimm:$i3)), 217 "$i0, $i1, $i2, $i3">; 218defm "" : ConstVec<v2f64, 219 (ins f64imm_op:$i0, f64imm_op:$i1), 220 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 221 "$i0, $i1">; 222 223// Shuffle lanes: shuffle 224defm SHUFFLE : 225 SIMD_I<(outs V128:$dst), 226 (ins V128:$x, V128:$y, 227 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 228 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 229 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 230 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 231 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 232 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 233 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 234 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 235 (outs), 236 (ins 237 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 238 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 239 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 240 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 241 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 242 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 243 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 244 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 245 [], 246 "v8x16.shuffle\t$dst, $x, $y, "# 247 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 248 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 249 "v8x16.shuffle\t"# 250 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 251 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 252 3>; 253 254// Shuffles after custom lowering 255def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 256def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 257foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in { 258def : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y), 259 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 260 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 261 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 262 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 263 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 264 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 265 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 266 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 267 (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y), 268 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 269 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 270 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 271 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 272 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 273 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 274 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 275 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>; 276} 277 278// Swizzle lanes: v8x16.swizzle 279def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 280def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 281let Predicates = [HasUnimplementedSIMD128] in 282defm SWIZZLE : 283 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 284 [(set (v16i8 V128:$dst), 285 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 286 "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 192>; 287 288def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 289 (SWIZZLE V128:$src, V128:$mask)>; 290 291// Create vector with identical lanes: splat 292def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>; 293def splat4 : PatFrag<(ops node:$x), (build_vector 294 node:$x, node:$x, node:$x, node:$x)>; 295def splat8 : PatFrag<(ops node:$x), (build_vector 296 node:$x, node:$x, node:$x, node:$x, 297 node:$x, node:$x, node:$x, node:$x)>; 298def splat16 : PatFrag<(ops node:$x), (build_vector 299 node:$x, node:$x, node:$x, node:$x, 300 node:$x, node:$x, node:$x, node:$x, 301 node:$x, node:$x, node:$x, node:$x, 302 node:$x, node:$x, node:$x, node:$x)>; 303 304multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t, 305 PatFrag splat_pat, bits<32> simdop> { 306 // Prefer splats over v128.const for const splats (65 is lowest that works) 307 let AddedComplexity = 65 in 308 defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins), 309 [(set (vec_t V128:$dst), (splat_pat reg_t:$x))], 310 vec#".splat\t$dst, $x", vec#".splat", simdop>; 311} 312 313defm "" : Splat<v16i8, "i8x16", I32, splat16, 4>; 314defm "" : Splat<v8i16, "i16x8", I32, splat8, 8>; 315defm "" : Splat<v4i32, "i32x4", I32, splat4, 12>; 316defm "" : Splat<v2i64, "i64x2", I64, splat2, 15>; 317defm "" : Splat<v4f32, "f32x4", F32, splat4, 18>; 318defm "" : Splat<v2f64, "f64x2", F64, splat2, 21>; 319 320// scalar_to_vector leaves high lanes undefined, so can be a splat 321class ScalarSplatPat<ValueType vec_t, ValueType lane_t, 322 WebAssemblyRegClass reg_t> : 323 Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))), 324 (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>; 325 326def : ScalarSplatPat<v16i8, i32, I32>; 327def : ScalarSplatPat<v8i16, i32, I32>; 328def : ScalarSplatPat<v4i32, i32, I32>; 329def : ScalarSplatPat<v2i64, i64, I64>; 330def : ScalarSplatPat<v4f32, f32, F32>; 331def : ScalarSplatPat<v2f64, f64, F64>; 332 333//===----------------------------------------------------------------------===// 334// Accessing lanes 335//===----------------------------------------------------------------------===// 336 337// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 338multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t, 339 WebAssemblyRegClass reg_t, bits<32> simdop, 340 string suffix = "", SDNode extract = vector_extract> { 341 defm EXTRACT_LANE_#vec_t#suffix : 342 SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 343 (outs), (ins vec_i8imm_op:$idx), 344 [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))], 345 vec#".extract_lane"#suffix#"\t$dst, $vec, $idx", 346 vec#".extract_lane"#suffix#"\t$idx", simdop>; 347} 348 349multiclass ExtractPat<ValueType lane_t, int mask> { 350 def _s : PatFrag<(ops node:$vec, node:$idx), 351 (i32 (sext_inreg 352 (i32 (vector_extract 353 node:$vec, 354 node:$idx 355 )), 356 lane_t 357 ))>; 358 def _u : PatFrag<(ops node:$vec, node:$idx), 359 (i32 (and 360 (i32 (vector_extract 361 node:$vec, 362 node:$idx 363 )), 364 (i32 mask) 365 ))>; 366} 367 368defm extract_i8x16 : ExtractPat<i8, 0xff>; 369defm extract_i16x8 : ExtractPat<i16, 0xffff>; 370 371multiclass ExtractLaneExtended<string sign, bits<32> baseInst> { 372 defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign, 373 !cast<PatFrag>("extract_i8x16"#sign)>; 374 defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign, 375 !cast<PatFrag>("extract_i16x8"#sign)>; 376} 377 378defm "" : ExtractLaneExtended<"_s", 5>; 379let Predicates = [HasUnimplementedSIMD128] in 380defm "" : ExtractLaneExtended<"_u", 6>; 381defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>; 382defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>; 383defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>; 384defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>; 385 386// It would be more conventional to use unsigned extracts, but v8 387// doesn't implement them yet 388def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))), 389 (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>; 390def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))), 391 (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>; 392 393// Lower undef lane indices to zero 394def : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)), 395 (EXTRACT_LANE_v16i8_u V128:$vec, 0)>; 396def : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)), 397 (EXTRACT_LANE_v8i16_u V128:$vec, 0)>; 398def : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)), 399 (EXTRACT_LANE_v16i8_u V128:$vec, 0)>; 400def : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)), 401 (EXTRACT_LANE_v8i16_u V128:$vec, 0)>; 402def : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8), 403 (EXTRACT_LANE_v16i8_s V128:$vec, 0)>; 404def : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16), 405 (EXTRACT_LANE_v8i16_s V128:$vec, 0)>; 406def : Pat<(vector_extract (v4i32 V128:$vec), undef), 407 (EXTRACT_LANE_v4i32 V128:$vec, 0)>; 408def : Pat<(vector_extract (v2i64 V128:$vec), undef), 409 (EXTRACT_LANE_v2i64 V128:$vec, 0)>; 410def : Pat<(vector_extract (v4f32 V128:$vec), undef), 411 (EXTRACT_LANE_v4f32 V128:$vec, 0)>; 412def : Pat<(vector_extract (v2f64 V128:$vec), undef), 413 (EXTRACT_LANE_v2f64 V128:$vec, 0)>; 414 415// Replace lane value: replace_lane 416multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t, 417 WebAssemblyRegClass reg_t, ValueType lane_t, 418 bits<32> simdop> { 419 defm REPLACE_LANE_#vec_t : 420 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x), 421 (outs), (ins vec_i8imm_op:$idx), 422 [(set V128:$dst, (vector_insert 423 (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))], 424 vec#".replace_lane\t$dst, $vec, $idx, $x", 425 vec#".replace_lane\t$idx", simdop>; 426} 427 428defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>; 429defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>; 430defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>; 431defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>; 432defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>; 433defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>; 434 435// Lower undef lane indices to zero 436def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 437 (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>; 438def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 439 (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>; 440def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 441 (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>; 442def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 443 (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>; 444def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 445 (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>; 446def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 447 (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>; 448 449//===----------------------------------------------------------------------===// 450// Comparisons 451//===----------------------------------------------------------------------===// 452 453multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec, 454 string name, CondCode cond, bits<32> simdop> { 455 defm _#vec_t : 456 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 457 [(set (out_t V128:$dst), 458 (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond) 459 )], 460 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>; 461} 462 463multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 464 defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>; 465 defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond, 466 !add(baseInst, 10)>; 467 defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond, 468 !add(baseInst, 20)>; 469} 470 471multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 472 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>; 473 defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond, 474 !add(baseInst, 6)>; 475} 476 477// Equality: eq 478let isCommutable = 1 in { 479defm EQ : SIMDConditionInt<"eq", SETEQ, 24>; 480defm EQ : SIMDConditionFP<"eq", SETOEQ, 64>; 481} // isCommutable = 1 482 483// Non-equality: ne 484let isCommutable = 1 in { 485defm NE : SIMDConditionInt<"ne", SETNE, 25>; 486defm NE : SIMDConditionFP<"ne", SETUNE, 65>; 487} // isCommutable = 1 488 489// Less than: lt_s / lt_u / lt 490defm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>; 491defm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>; 492defm LT : SIMDConditionFP<"lt", SETOLT, 66>; 493 494// Greater than: gt_s / gt_u / gt 495defm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>; 496defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>; 497defm GT : SIMDConditionFP<"gt", SETOGT, 67>; 498 499// Less than or equal: le_s / le_u / le 500defm LE_S : SIMDConditionInt<"le_s", SETLE, 30>; 501defm LE_U : SIMDConditionInt<"le_u", SETULE, 31>; 502defm LE : SIMDConditionFP<"le", SETOLE, 68>; 503 504// Greater than or equal: ge_s / ge_u / ge 505defm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>; 506defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>; 507defm GE : SIMDConditionFP<"ge", SETOGE, 69>; 508 509// Lower float comparisons that don't care about NaN to standard WebAssembly 510// float comparisons. These instructions are generated with nnan and in the 511// target-independent expansion of unordered comparisons and ordered ne. 512foreach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32], 513 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in 514def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 515 (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>; 516 517foreach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64], 518 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in 519def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 520 (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>; 521 522 523//===----------------------------------------------------------------------===// 524// Bitwise operations 525//===----------------------------------------------------------------------===// 526 527multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name, 528 bits<32> simdop> { 529 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 530 (outs), (ins), 531 [(set (vec_t V128:$dst), 532 (node (vec_t V128:$lhs), (vec_t V128:$rhs)) 533 )], 534 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, 535 simdop>; 536} 537 538multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> { 539 defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>; 540 defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>; 541 defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>; 542 defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>; 543} 544 545multiclass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name, 546 bits<32> simdop> { 547 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 548 [(set (vec_t V128:$dst), 549 (vec_t (node (vec_t V128:$vec))) 550 )], 551 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 552} 553 554// Bitwise logic: v128.not 555foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 556defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>; 557 558// Bitwise logic: v128.and / v128.or / v128.xor 559let isCommutable = 1 in { 560defm AND : SIMDBitwise<and, "and", 77>; 561defm OR : SIMDBitwise<or, "or", 78>; 562defm XOR : SIMDBitwise<xor, "xor", 79>; 563} // isCommutable = 1 564 565// Bitwise logic: v128.andnot 566def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 567let Predicates = [HasUnimplementedSIMD128] in 568defm ANDNOT : SIMDBitwise<andnot, "andnot", 216>; 569 570// Bitwise select: v128.bitselect 571foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 572 defm BITSELECT_#vec_t : 573 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), 574 [(set (vec_t V128:$dst), 575 (vec_t (int_wasm_bitselect 576 (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c) 577 )) 578 )], 579 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>; 580 581// Bitselect is equivalent to (c & v1) | (~c & v2) 582foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in 583 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)), 584 (and (vnot V128:$c), (vec_t V128:$v2)))), 585 (!cast<Instruction>("BITSELECT_"#vec_t) 586 V128:$v1, V128:$v2, V128:$c)>; 587 588//===----------------------------------------------------------------------===// 589// Integer unary arithmetic 590//===----------------------------------------------------------------------===// 591 592multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> { 593 defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>; 594 defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>; 595 defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>; 596 defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>; 597} 598 599multiclass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name, 600 bits<32> simdop> { 601 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 602 [(set I32:$dst, (i32 (op (vec_t V128:$vec))))], 603 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>; 604} 605 606multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> { 607 defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>; 608 defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>; 609 defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>; 610 defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>; 611} 612 613// Integer vector negation 614def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 615 616// Integer negation: neg 617defm NEG : SIMDUnaryInt<ivneg, "neg", 81>; 618 619// Any lane true: any_true 620defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>; 621 622// All lanes true: all_true 623defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>; 624 625// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 626// can be folded out 627foreach reduction = 628 [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in 629foreach ty = [v16i8, v8i16, v4i32, v2i64] in { 630def : Pat<(i32 (and 631 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 632 (i32 1) 633 )), 634 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 635def : Pat<(i32 (setne 636 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 637 (i32 0) 638 )), 639 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 640def : Pat<(i32 (seteq 641 (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))), 642 (i32 1) 643 )), 644 (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>; 645} 646 647//===----------------------------------------------------------------------===// 648// Bit shifts 649//===----------------------------------------------------------------------===// 650 651multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec, 652 string name, bits<32> simdop> { 653 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), 654 (outs), (ins), 655 [(set (vec_t V128:$dst), 656 (node V128:$vec, (vec_t shift_vec)))], 657 vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>; 658} 659 660multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 661 defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>; 662 defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name, 663 !add(baseInst, 17)>; 664 defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name, 665 !add(baseInst, 34)>; 666 defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))), 667 name, !add(baseInst, 51)>; 668} 669 670// Left shift by scalar: shl 671defm SHL : SIMDShiftInt<shl, "shl", 84>; 672 673// Right shift by scalar: shr_s / shr_u 674defm SHR_S : SIMDShiftInt<sra, "shr_s", 85>; 675defm SHR_U : SIMDShiftInt<srl, "shr_u", 86>; 676 677// Truncate i64 shift operands to i32s, except if they are already i32s 678foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in { 679def : Pat<(v2i64 (shifts[0] 680 (v2i64 V128:$vec), 681 (v2i64 (splat2 (i64 (sext I32:$x)))) 682 )), 683 (v2i64 (shifts[1] (v2i64 V128:$vec), (i32 I32:$x)))>; 684def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))), 685 (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>; 686} 687 688// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping 689def wasm_shift_t : SDTypeProfile<1, 2, 690 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>] 691>; 692def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 693def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 694def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 695foreach shifts = [[wasm_shl, SHL_v2i64], 696 [wasm_shr_s, SHR_S_v2i64], 697 [wasm_shr_u, SHR_U_v2i64]] in 698def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)), 699 (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>; 700 701//===----------------------------------------------------------------------===// 702// Integer binary arithmetic 703//===----------------------------------------------------------------------===// 704 705multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> { 706 defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>; 707 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>; 708} 709 710multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> { 711 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 712 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>; 713} 714 715multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> { 716 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 717 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>; 718} 719 720// Integer addition: add / add_saturate_s / add_saturate_u 721let isCommutable = 1 in { 722defm ADD : SIMDBinaryInt<add, "add", 87>; 723defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>; 724defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>; 725} // isCommutable = 1 726 727// Integer subtraction: sub / sub_saturate_s / sub_saturate_u 728defm SUB : SIMDBinaryInt<sub, "sub", 90>; 729defm SUB_SAT_S : 730 SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>; 731defm SUB_SAT_U : 732 SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>; 733 734// Integer multiplication: mul 735defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>; 736 737//===----------------------------------------------------------------------===// 738// Floating-point unary arithmetic 739//===----------------------------------------------------------------------===// 740 741multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 742 defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>; 743 defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>; 744} 745 746// Absolute value: abs 747defm ABS : SIMDUnaryFP<fabs, "abs", 149>; 748 749// Negation: neg 750defm NEG : SIMDUnaryFP<fneg, "neg", 150>; 751 752// Square root: sqrt 753let Predicates = [HasUnimplementedSIMD128] in 754defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>; 755 756//===----------------------------------------------------------------------===// 757// Floating-point binary arithmetic 758//===----------------------------------------------------------------------===// 759 760multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> { 761 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>; 762 defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>; 763} 764 765// Addition: add 766let isCommutable = 1 in 767defm ADD : SIMDBinaryFP<fadd, "add", 154>; 768 769// Subtraction: sub 770defm SUB : SIMDBinaryFP<fsub, "sub", 155>; 771 772// Multiplication: mul 773let isCommutable = 1 in 774defm MUL : SIMDBinaryFP<fmul, "mul", 156>; 775 776// Division: div 777let Predicates = [HasUnimplementedSIMD128] in 778defm DIV : SIMDBinaryFP<fdiv, "div", 157>; 779 780// NaN-propagating minimum: min 781defm MIN : SIMDBinaryFP<fminimum, "min", 158>; 782 783// NaN-propagating maximum: max 784defm MAX : SIMDBinaryFP<fmaximum, "max", 159>; 785 786//===----------------------------------------------------------------------===// 787// Conversions 788//===----------------------------------------------------------------------===// 789 790multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op, 791 string name, bits<32> simdop> { 792 defm op#_#vec_t#_#arg_t : 793 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 794 [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))], 795 name#"\t$dst, $vec", name, simdop>; 796} 797 798// Integer to floating point: convert 799defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>; 800defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>; 801defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>; 802defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>; 803 804// Floating point to integer with saturation: trunc_sat 805defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>; 806defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>; 807defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>; 808defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>; 809 810// Widening operations 811multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg, 812 bits<32> baseInst> { 813 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed, 814 vec#".widen_low_"#arg#"_s", baseInst>; 815 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed, 816 vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>; 817 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned, 818 vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>; 819 defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned, 820 vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>; 821} 822 823defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 202>; 824defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 206>; 825 826// Narrowing operations 827multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg, 828 bits<32> baseInst> { 829 defm NARROW_S_#vec_t : 830 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 831 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed 832 (arg_t V128:$low), (arg_t V128:$high))))], 833 vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s", 834 baseInst>; 835 defm NARROW_U_#vec_t : 836 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 837 [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned 838 (arg_t V128:$low), (arg_t V128:$high))))], 839 vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u", 840 !add(baseInst, 1)>; 841} 842 843defm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 198>; 844defm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 200>; 845 846// Lower llvm.wasm.trunc.saturate.* to saturating instructions 847def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))), 848 (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>; 849def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))), 850 (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>; 851def : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))), 852 (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>; 853def : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))), 854 (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>; 855 856// Bitcasts are nops 857// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 858foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in 859foreach t2 = !foldl( 860 []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 861 acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)), 862 acc, !listconcat(acc, [cur]) 863 ) 864) in 865def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>; 866 867//===----------------------------------------------------------------------===// 868// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS) 869//===----------------------------------------------------------------------===// 870 871multiclass SIMDQFM<ValueType vec_t, string vec, bits<32> baseInst> { 872 defm QFMA_#vec_t : 873 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 874 (outs), (ins), 875 [(set (vec_t V128:$dst), 876 (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 877 vec#".qfma\t$dst, $a, $b, $c", vec#".qfma", baseInst>; 878 defm QFMS_#vec_t : 879 SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c), 880 (outs), (ins), 881 [(set (vec_t V128:$dst), 882 (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))], 883 vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", !add(baseInst, 1)>; 884} 885 886defm "" : SIMDQFM<v4f32, "f32x4", 0x98>; 887defm "" : SIMDQFM<v2f64, "f64x2", 0xa3>; 888