1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly SIMD operand code-gen constructs. 11/// 12//===----------------------------------------------------------------------===// 13 14// Instructions requiring HasSIMD128 and the simd128 prefix byte 15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 16 list<dag> pattern_r, string asmstr_r = "", 17 string asmstr_s = "", bits<32> simdop = -1> { 18 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s, 19 !if(!ge(simdop, 0x100), 20 !or(0xfd0000, !and(0xffff, simdop)), 21 !or(0xfd00, !and(0xff, simdop)))>, 22 Requires<[HasSIMD128]>; 23} 24 25defm "" : ARGUMENT<V128, v16i8>; 26defm "" : ARGUMENT<V128, v8i16>; 27defm "" : ARGUMENT<V128, v4i32>; 28defm "" : ARGUMENT<V128, v2i64>; 29defm "" : ARGUMENT<V128, v4f32>; 30defm "" : ARGUMENT<V128, v2f64>; 31 32// Constrained immediate argument types 33foreach SIZE = [8, 16] in 34def ImmI#SIZE : ImmLeaf<i32, 35 "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));" 36>; 37foreach SIZE = [2, 4, 8, 16, 32] in 38def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">; 39 40// Create vector with identical lanes: splat 41def splat2 : PatFrag<(ops node:$x), (build_vector $x, $x)>; 42def splat4 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x)>; 43def splat8 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x, 44 $x, $x, $x, $x)>; 45def splat16 : PatFrag<(ops node:$x), 46 (build_vector $x, $x, $x, $x, $x, $x, $x, $x, 47 $x, $x, $x, $x, $x, $x, $x, $x)>; 48 49class Vec { 50 ValueType vt; 51 ValueType int_vt; 52 ValueType lane_vt; 53 WebAssemblyRegClass lane_rc; 54 int lane_bits; 55 ImmLeaf lane_idx; 56 PatFrag splat; 57 string prefix; 58 Vec split; 59} 60 61def I8x16 : Vec { 62 let vt = v16i8; 63 let int_vt = vt; 64 let lane_vt = i32; 65 let lane_rc = I32; 66 let lane_bits = 8; 67 let lane_idx = LaneIdx16; 68 let splat = splat16; 69 let prefix = "i8x16"; 70} 71 72def I16x8 : Vec { 73 let vt = v8i16; 74 let int_vt = vt; 75 let lane_vt = i32; 76 let lane_rc = I32; 77 let lane_bits = 16; 78 let lane_idx = LaneIdx8; 79 let splat = splat8; 80 let prefix = "i16x8"; 81 let split = I8x16; 82} 83 84def I32x4 : Vec { 85 let vt = v4i32; 86 let int_vt = vt; 87 let lane_vt = i32; 88 let lane_rc = I32; 89 let lane_bits = 32; 90 let lane_idx = LaneIdx4; 91 let splat = splat4; 92 let prefix = "i32x4"; 93 let split = I16x8; 94} 95 96def I64x2 : Vec { 97 let vt = v2i64; 98 let int_vt = vt; 99 let lane_vt = i64; 100 let lane_rc = I64; 101 let lane_bits = 64; 102 let lane_idx = LaneIdx2; 103 let splat = splat2; 104 let prefix = "i64x2"; 105 let split = I32x4; 106} 107 108def F32x4 : Vec { 109 let vt = v4f32; 110 let int_vt = v4i32; 111 let lane_vt = f32; 112 let lane_rc = F32; 113 let lane_bits = 32; 114 let lane_idx = LaneIdx4; 115 let splat = splat4; 116 let prefix = "f32x4"; 117} 118 119def F64x2 : Vec { 120 let vt = v2f64; 121 let int_vt = v2i64; 122 let lane_vt = f64; 123 let lane_rc = F64; 124 let lane_bits = 64; 125 let lane_idx = LaneIdx2; 126 let splat = splat2; 127 let prefix = "f64x2"; 128} 129 130defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2]; 131defvar IntVecs = [I8x16, I16x8, I32x4, I64x2]; 132 133//===----------------------------------------------------------------------===// 134// Load and store 135//===----------------------------------------------------------------------===// 136 137// Load: v128.load 138let mayLoad = 1, UseNamedOperandTable = 1 in { 139defm LOAD_V128_A32 : 140 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 141 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 142 "v128.load\t$dst, ${off}(${addr})$p2align", 143 "v128.load\t$off$p2align", 0>; 144defm LOAD_V128_A64 : 145 SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 146 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 147 "v128.load\t$dst, ${off}(${addr})$p2align", 148 "v128.load\t$off$p2align", 0>; 149} 150 151// Def load patterns from WebAssemblyInstrMemory.td for vector types 152foreach vec = AllVecs in { 153defm : LoadPatNoOffset<vec.vt, load, "LOAD_V128">; 154defm : LoadPatImmOff<vec.vt, load, regPlusImm, "LOAD_V128">; 155defm : LoadPatImmOff<vec.vt, load, or_is_add, "LOAD_V128">; 156defm : LoadPatOffsetOnly<vec.vt, load, "LOAD_V128">; 157defm : LoadPatGlobalAddrOffOnly<vec.vt, load, "LOAD_V128">; 158} 159 160// v128.loadX_splat 161multiclass SIMDLoadSplat<int size, bits<32> simdop> { 162 let mayLoad = 1, UseNamedOperandTable = 1 in { 163 defm LOAD#size#_SPLAT_A32 : 164 SIMD_I<(outs V128:$dst), 165 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 166 (outs), 167 (ins P2Align:$p2align, offset32_op:$off), [], 168 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 169 "v128.load"#size#"_splat\t$off$p2align", simdop>; 170 defm LOAD#size#_SPLAT_A64 : 171 SIMD_I<(outs V128:$dst), 172 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 173 (outs), 174 (ins P2Align:$p2align, offset64_op:$off), [], 175 "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align", 176 "v128.load"#size#"_splat\t$off$p2align", simdop>; 177 } 178} 179 180defm "" : SIMDLoadSplat<8, 7>; 181defm "" : SIMDLoadSplat<16, 8>; 182defm "" : SIMDLoadSplat<32, 9>; 183defm "" : SIMDLoadSplat<64, 10>; 184 185def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>; 186def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t, 187 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 188def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>; 189 190foreach vec = AllVecs in { 191defvar inst = "LOAD"#vec.lane_bits#"_SPLAT"; 192defm : LoadPatNoOffset<vec.vt, load_splat, inst>; 193defm : LoadPatImmOff<vec.vt, load_splat, regPlusImm, inst>; 194defm : LoadPatImmOff<vec.vt, load_splat, or_is_add, inst>; 195defm : LoadPatOffsetOnly<vec.vt, load_splat, inst>; 196defm : LoadPatGlobalAddrOffOnly<vec.vt, load_splat, inst>; 197} 198 199// Load and extend 200multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> { 201 defvar signed = vec.prefix#".load"#loadPat#"_s"; 202 defvar unsigned = vec.prefix#".load"#loadPat#"_u"; 203 let mayLoad = 1, UseNamedOperandTable = 1 in { 204 defm LOAD_EXTEND_S_#vec#_A32 : 205 SIMD_I<(outs V128:$dst), 206 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 207 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 208 signed#"\t$dst, ${off}(${addr})$p2align", 209 signed#"\t$off$p2align", simdop>; 210 defm LOAD_EXTEND_U_#vec#_A32 : 211 SIMD_I<(outs V128:$dst), 212 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 213 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 214 unsigned#"\t$dst, ${off}(${addr})$p2align", 215 unsigned#"\t$off$p2align", !add(simdop, 1)>; 216 defm LOAD_EXTEND_S_#vec#_A64 : 217 SIMD_I<(outs V128:$dst), 218 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 219 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 220 signed#"\t$dst, ${off}(${addr})$p2align", 221 signed#"\t$off$p2align", simdop>; 222 defm LOAD_EXTEND_U_#vec#_A64 : 223 SIMD_I<(outs V128:$dst), 224 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 225 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 226 unsigned#"\t$dst, ${off}(${addr})$p2align", 227 unsigned#"\t$off$p2align", !add(simdop, 1)>; 228 } 229} 230 231defm "" : SIMDLoadExtend<I16x8, "8x8", 1>; 232defm "" : SIMDLoadExtend<I32x4, "16x4", 3>; 233defm "" : SIMDLoadExtend<I64x2, "32x2", 5>; 234 235foreach vec = [I16x8, I32x4, I64x2] in 236foreach exts = [["sextloadvi", "_S"], 237 ["zextloadvi", "_U"], 238 ["extloadvi", "_U"]] in { 239defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits); 240defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec; 241defm : LoadPatNoOffset<vec.vt, loadpat, inst>; 242defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>; 243defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>; 244defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>; 245defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>; 246} 247 248// Load lane into zero vector 249multiclass SIMDLoadZero<Vec vec, bits<32> simdop> { 250 defvar name = "v128.load"#vec.lane_bits#"_zero"; 251 let mayLoad = 1, UseNamedOperandTable = 1 in { 252 defm LOAD_ZERO_#vec#_A32 : 253 SIMD_I<(outs V128:$dst), 254 (ins P2Align:$p2align, offset32_op:$off, I32:$addr), 255 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 256 name#"\t$dst, ${off}(${addr})$p2align", 257 name#"\t$off$p2align", simdop>; 258 defm LOAD_ZERO_#vec#_A64 : 259 SIMD_I<(outs V128:$dst), 260 (ins P2Align:$p2align, offset64_op:$off, I64:$addr), 261 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 262 name#"\t$dst, ${off}(${addr})$p2align", 263 name#"\t$off$p2align", simdop>; 264 } // mayLoad = 1, UseNamedOperandTable = 1 265} 266 267defm "" : SIMDLoadZero<I32x4, 0x5c>; 268defm "" : SIMDLoadZero<I64x2, 0x5d>; 269 270// TODO: f32x4 and f64x2 as well 271foreach vec = [I32x4, I64x2] in { 272 defvar inst = "LOAD_ZERO_"#vec; 273 defvar pat = PatFrag<(ops node:$ptr), 274 (vector_insert (vec.splat (vec.lane_vt 0)), (vec.lane_vt (load $ptr)), 0)>; 275 defm : LoadPatNoOffset<vec.vt, pat, inst>; 276 defm : LoadPatImmOff<vec.vt, pat, regPlusImm, inst>; 277 defm : LoadPatImmOff<vec.vt, pat, or_is_add, inst>; 278 defm : LoadPatOffsetOnly<vec.vt, pat, inst>; 279 defm : LoadPatGlobalAddrOffOnly<vec.vt, pat, inst>; 280} 281 282// Load lane 283multiclass SIMDLoadLane<Vec vec, bits<32> simdop> { 284 defvar name = "v128.load"#vec.lane_bits#"_lane"; 285 let mayLoad = 1, UseNamedOperandTable = 1 in { 286 defm LOAD_LANE_#vec#_A32 : 287 SIMD_I<(outs V128:$dst), 288 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 289 I32:$addr, V128:$vec), 290 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 291 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 292 name#"\t$off$p2align, $idx", simdop>; 293 defm LOAD_LANE_#vec#_A64 : 294 SIMD_I<(outs V128:$dst), 295 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 296 I64:$addr, V128:$vec), 297 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 298 [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx", 299 name#"\t$off$p2align, $idx", simdop>; 300 } // mayLoad = 1, UseNamedOperandTable = 1 301} 302 303defm "" : SIMDLoadLane<I8x16, 0x54>; 304defm "" : SIMDLoadLane<I16x8, 0x55>; 305defm "" : SIMDLoadLane<I32x4, 0x56>; 306defm "" : SIMDLoadLane<I64x2, 0x57>; 307 308// Select loads with no constant offset. 309multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> { 310 defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32"); 311 defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64"); 312 def : Pat<(vec.vt (kind (i32 I32:$addr), 313 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 314 (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>, 315 Requires<[HasAddr32]>; 316 def : Pat<(vec.vt (kind (i64 I64:$addr), 317 (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))), 318 (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>, 319 Requires<[HasAddr64]>; 320} 321 322def load8_lane : 323 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 324 (vector_insert $vec, (i32 (extloadi8 $ptr)), $idx)>; 325def load16_lane : 326 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 327 (vector_insert $vec, (i32 (extloadi16 $ptr)), $idx)>; 328def load32_lane : 329 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 330 (vector_insert $vec, (i32 (load $ptr)), $idx)>; 331def load64_lane : 332 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 333 (vector_insert $vec, (i64 (load $ptr)), $idx)>; 334// TODO: floating point lanes as well 335 336defm : LoadLanePatNoOffset<I8x16, load8_lane>; 337defm : LoadLanePatNoOffset<I16x8, load16_lane>; 338defm : LoadLanePatNoOffset<I32x4, load32_lane>; 339defm : LoadLanePatNoOffset<I64x2, load64_lane>; 340 341// TODO: Also support the other load patterns for load_lane once the instructions 342// are merged to the proposal. 343 344// Store: v128.store 345let mayStore = 1, UseNamedOperandTable = 1 in { 346defm STORE_V128_A32 : 347 SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec), 348 (outs), (ins P2Align:$p2align, offset32_op:$off), [], 349 "v128.store\t${off}(${addr})$p2align, $vec", 350 "v128.store\t$off$p2align", 11>; 351defm STORE_V128_A64 : 352 SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec), 353 (outs), (ins P2Align:$p2align, offset64_op:$off), [], 354 "v128.store\t${off}(${addr})$p2align, $vec", 355 "v128.store\t$off$p2align", 11>; 356} 357 358// Def store patterns from WebAssemblyInstrMemory.td for vector types 359foreach vec = AllVecs in { 360defm : StorePatNoOffset<vec.vt, store, "STORE_V128">; 361defm : StorePatImmOff<vec.vt, store, regPlusImm, "STORE_V128">; 362defm : StorePatImmOff<vec.vt, store, or_is_add, "STORE_V128">; 363defm : StorePatOffsetOnly<vec.vt, store, "STORE_V128">; 364defm : StorePatGlobalAddrOffOnly<vec.vt, store, "STORE_V128">; 365} 366 367// Store lane 368multiclass SIMDStoreLane<Vec vec, bits<32> simdop> { 369 defvar name = "v128.store"#vec.lane_bits#"_lane"; 370 let mayStore = 1, UseNamedOperandTable = 1 in { 371 defm STORE_LANE_#vec#_A32 : 372 SIMD_I<(outs), 373 (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx, 374 I32:$addr, V128:$vec), 375 (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx), 376 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 377 name#"\t$off$p2align, $idx", simdop>; 378 defm STORE_LANE_#vec#_A64 : 379 SIMD_I<(outs V128:$dst), 380 (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx, 381 I64:$addr, V128:$vec), 382 (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx), 383 [], name#"\t${off}(${addr})$p2align, $vec, $idx", 384 name#"\t$off$p2align, $idx", simdop>; 385 } // mayStore = 1, UseNamedOperandTable = 1 386} 387 388defm "" : SIMDStoreLane<I8x16, 0x58>; 389defm "" : SIMDStoreLane<I16x8, 0x59>; 390defm "" : SIMDStoreLane<I32x4, 0x5a>; 391defm "" : SIMDStoreLane<I64x2, 0x5b>; 392 393// Select stores with no constant offset. 394multiclass StoreLanePatNoOffset<Vec vec, SDPatternOperator kind> { 395 def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)), 396 (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>, 397 Requires<[HasAddr32]>; 398 def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)), 399 (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>, 400 Requires<[HasAddr64]>; 401} 402 403def store8_lane : 404 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 405 (truncstorei8 (i32 (vector_extract $vec, $idx)), $ptr)>; 406def store16_lane : 407 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 408 (truncstorei16 (i32 (vector_extract $vec, $idx)), $ptr)>; 409def store32_lane : 410 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 411 (store (i32 (vector_extract $vec, $idx)), $ptr)>; 412def store64_lane : 413 PatFrag<(ops node:$ptr, node:$vec, node:$idx), 414 (store (i64 (vector_extract $vec, $idx)), $ptr)>; 415// TODO: floating point lanes as well 416 417let AddedComplexity = 1 in { 418defm : StoreLanePatNoOffset<I8x16, store8_lane>; 419defm : StoreLanePatNoOffset<I16x8, store16_lane>; 420defm : StoreLanePatNoOffset<I32x4, store32_lane>; 421defm : StoreLanePatNoOffset<I64x2, store64_lane>; 422} 423 424//===----------------------------------------------------------------------===// 425// Constructing SIMD values 426//===----------------------------------------------------------------------===// 427 428// Constant: v128.const 429multiclass ConstVec<Vec vec, dag ops, dag pat, string args> { 430 let isMoveImm = 1, isReMaterializable = 1 in 431 defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops, 432 [(set V128:$dst, (vec.vt pat))], 433 "v128.const\t$dst, "#args, 434 "v128.const\t"#args, 12>; 435} 436 437defm "" : ConstVec<I8x16, 438 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1, 439 vec_i8imm_op:$i2, vec_i8imm_op:$i3, 440 vec_i8imm_op:$i4, vec_i8imm_op:$i5, 441 vec_i8imm_op:$i6, vec_i8imm_op:$i7, 442 vec_i8imm_op:$i8, vec_i8imm_op:$i9, 443 vec_i8imm_op:$iA, vec_i8imm_op:$iB, 444 vec_i8imm_op:$iC, vec_i8imm_op:$iD, 445 vec_i8imm_op:$iE, vec_i8imm_op:$iF), 446 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3, 447 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7, 448 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB, 449 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF), 450 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ", 451 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>; 452defm "" : ConstVec<I16x8, 453 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1, 454 vec_i16imm_op:$i2, vec_i16imm_op:$i3, 455 vec_i16imm_op:$i4, vec_i16imm_op:$i5, 456 vec_i16imm_op:$i6, vec_i16imm_op:$i7), 457 (build_vector 458 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3, 459 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7), 460 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">; 461let IsCanonical = 1 in 462defm "" : ConstVec<I32x4, 463 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1, 464 vec_i32imm_op:$i2, vec_i32imm_op:$i3), 465 (build_vector (i32 imm:$i0), (i32 imm:$i1), 466 (i32 imm:$i2), (i32 imm:$i3)), 467 "$i0, $i1, $i2, $i3">; 468defm "" : ConstVec<I64x2, 469 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1), 470 (build_vector (i64 imm:$i0), (i64 imm:$i1)), 471 "$i0, $i1">; 472defm "" : ConstVec<F32x4, 473 (ins f32imm_op:$i0, f32imm_op:$i1, 474 f32imm_op:$i2, f32imm_op:$i3), 475 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1), 476 (f32 fpimm:$i2), (f32 fpimm:$i3)), 477 "$i0, $i1, $i2, $i3">; 478defm "" : ConstVec<F64x2, 479 (ins f64imm_op:$i0, f64imm_op:$i1), 480 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)), 481 "$i0, $i1">; 482 483// Shuffle lanes: shuffle 484defm SHUFFLE : 485 SIMD_I<(outs V128:$dst), 486 (ins V128:$x, V128:$y, 487 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 488 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 489 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 490 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 491 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 492 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 493 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 494 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 495 (outs), 496 (ins 497 vec_i8imm_op:$m0, vec_i8imm_op:$m1, 498 vec_i8imm_op:$m2, vec_i8imm_op:$m3, 499 vec_i8imm_op:$m4, vec_i8imm_op:$m5, 500 vec_i8imm_op:$m6, vec_i8imm_op:$m7, 501 vec_i8imm_op:$m8, vec_i8imm_op:$m9, 502 vec_i8imm_op:$mA, vec_i8imm_op:$mB, 503 vec_i8imm_op:$mC, vec_i8imm_op:$mD, 504 vec_i8imm_op:$mE, vec_i8imm_op:$mF), 505 [], 506 "i8x16.shuffle\t$dst, $x, $y, "# 507 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 508 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 509 "i8x16.shuffle\t"# 510 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "# 511 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF", 512 13>; 513 514// Shuffles after custom lowering 515def wasm_shuffle_t : SDTypeProfile<1, 18, []>; 516def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>; 517foreach vec = AllVecs in { 518def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y), 519 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1), 520 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3), 521 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5), 522 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7), 523 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9), 524 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB), 525 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD), 526 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))), 527 (SHUFFLE $x, $y, 528 imm:$m0, imm:$m1, imm:$m2, imm:$m3, 529 imm:$m4, imm:$m5, imm:$m6, imm:$m7, 530 imm:$m8, imm:$m9, imm:$mA, imm:$mB, 531 imm:$mC, imm:$mD, imm:$mE, imm:$mF)>; 532} 533 534// Swizzle lanes: i8x16.swizzle 535def wasm_swizzle_t : SDTypeProfile<1, 2, []>; 536def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>; 537defm SWIZZLE : 538 SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins), 539 [(set (v16i8 V128:$dst), 540 (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))], 541 "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>; 542 543def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)), 544 (SWIZZLE $src, $mask)>; 545 546multiclass Splat<Vec vec, bits<32> simdop> { 547 defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x), 548 (outs), (ins), 549 [(set (vec.vt V128:$dst), 550 (vec.splat vec.lane_rc:$x))], 551 vec.prefix#".splat\t$dst, $x", vec.prefix#".splat", 552 simdop>; 553} 554 555defm "" : Splat<I8x16, 15>; 556defm "" : Splat<I16x8, 16>; 557defm "" : Splat<I32x4, 17>; 558defm "" : Splat<I64x2, 18>; 559defm "" : Splat<F32x4, 19>; 560defm "" : Splat<F64x2, 20>; 561 562// scalar_to_vector leaves high lanes undefined, so can be a splat 563foreach vec = AllVecs in 564def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))), 565 (!cast<Instruction>("SPLAT_"#vec) $x)>; 566 567//===----------------------------------------------------------------------===// 568// Accessing lanes 569//===----------------------------------------------------------------------===// 570 571// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u 572multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> { 573 defm EXTRACT_LANE_#vec#suffix : 574 SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx), 575 (outs), (ins vec_i8imm_op:$idx), [], 576 vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx", 577 vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>; 578} 579 580defm "" : ExtractLane<I8x16, 21, "_s">; 581defm "" : ExtractLane<I8x16, 22, "_u">; 582defm "" : ExtractLane<I16x8, 24, "_s">; 583defm "" : ExtractLane<I16x8, 25, "_u">; 584defm "" : ExtractLane<I32x4, 27>; 585defm "" : ExtractLane<I64x2, 29>; 586defm "" : ExtractLane<F32x4, 31>; 587defm "" : ExtractLane<F64x2, 33>; 588 589def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), 590 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 591def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), 592 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 593def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)), 594 (EXTRACT_LANE_I32x4 $vec, imm:$idx)>; 595def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)), 596 (EXTRACT_LANE_F32x4 $vec, imm:$idx)>; 597def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)), 598 (EXTRACT_LANE_I64x2 $vec, imm:$idx)>; 599def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)), 600 (EXTRACT_LANE_F64x2 $vec, imm:$idx)>; 601 602def : Pat< 603 (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8), 604 (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>; 605def : Pat< 606 (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)), 607 (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>; 608def : Pat< 609 (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16), 610 (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>; 611def : Pat< 612 (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)), 613 (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>; 614 615// Replace lane value: replace_lane 616multiclass ReplaceLane<Vec vec, bits<32> simdop> { 617 defm REPLACE_LANE_#vec : 618 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x), 619 (outs), (ins vec_i8imm_op:$idx), 620 [(set V128:$dst, (vector_insert 621 (vec.vt V128:$vec), 622 (vec.lane_vt vec.lane_rc:$x), 623 (i32 vec.lane_idx:$idx)))], 624 vec.prefix#".replace_lane\t$dst, $vec, $idx, $x", 625 vec.prefix#".replace_lane\t$idx", simdop>; 626} 627 628defm "" : ReplaceLane<I8x16, 23>; 629defm "" : ReplaceLane<I16x8, 26>; 630defm "" : ReplaceLane<I32x4, 28>; 631defm "" : ReplaceLane<I64x2, 30>; 632defm "" : ReplaceLane<F32x4, 32>; 633defm "" : ReplaceLane<F64x2, 34>; 634 635// Lower undef lane indices to zero 636def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef), 637 (REPLACE_LANE_I8x16 $vec, 0, $x)>; 638def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef), 639 (REPLACE_LANE_I16x8 $vec, 0, $x)>; 640def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef), 641 (REPLACE_LANE_I32x4 $vec, 0, $x)>; 642def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef), 643 (REPLACE_LANE_I64x2 $vec, 0, $x)>; 644def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef), 645 (REPLACE_LANE_F32x4 $vec, 0, $x)>; 646def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef), 647 (REPLACE_LANE_F64x2 $vec, 0, $x)>; 648 649//===----------------------------------------------------------------------===// 650// Comparisons 651//===----------------------------------------------------------------------===// 652 653multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> { 654 defm _#vec : 655 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 656 [(set (vec.int_vt V128:$dst), 657 (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))], 658 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 659 vec.prefix#"."#name, simdop>; 660} 661 662multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> { 663 defm "" : SIMDCondition<I8x16, name, cond, baseInst>; 664 defm "" : SIMDCondition<I16x8, name, cond, !add(baseInst, 10)>; 665 defm "" : SIMDCondition<I32x4, name, cond, !add(baseInst, 20)>; 666} 667 668multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> { 669 defm "" : SIMDCondition<F32x4, name, cond, baseInst>; 670 defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>; 671} 672 673// Equality: eq 674let isCommutable = 1 in { 675defm EQ : SIMDConditionInt<"eq", SETEQ, 35>; 676defm EQ : SIMDCondition<I64x2, "eq", SETEQ, 214>; 677defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>; 678} // isCommutable = 1 679 680// Non-equality: ne 681let isCommutable = 1 in { 682defm NE : SIMDConditionInt<"ne", SETNE, 36>; 683defm NE : SIMDCondition<I64x2, "ne", SETNE, 215>; 684defm NE : SIMDConditionFP<"ne", SETUNE, 66>; 685} // isCommutable = 1 686 687// Less than: lt_s / lt_u / lt 688defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>; 689defm LT_S : SIMDCondition<I64x2, "lt_s", SETLT, 216>; 690defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>; 691defm LT : SIMDConditionFP<"lt", SETOLT, 67>; 692 693// Greater than: gt_s / gt_u / gt 694defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>; 695defm GT_S : SIMDCondition<I64x2, "gt_s", SETGT, 217>; 696defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>; 697defm GT : SIMDConditionFP<"gt", SETOGT, 68>; 698 699// Less than or equal: le_s / le_u / le 700defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>; 701defm LE_S : SIMDCondition<I64x2, "le_s", SETLE, 218>; 702defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>; 703defm LE : SIMDConditionFP<"le", SETOLE, 69>; 704 705// Greater than or equal: ge_s / ge_u / ge 706defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>; 707defm GE_S : SIMDCondition<I64x2, "ge_s", SETGE, 219>; 708defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>; 709defm GE : SIMDConditionFP<"ge", SETOGE, 70>; 710 711// Lower float comparisons that don't care about NaN to standard WebAssembly 712// float comparisons. These instructions are generated with nnan and in the 713// target-independent expansion of unordered comparisons and ordered ne. 714foreach nodes = [[seteq, EQ_F32x4], [setne, NE_F32x4], [setlt, LT_F32x4], 715 [setgt, GT_F32x4], [setle, LE_F32x4], [setge, GE_F32x4]] in 716def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))), 717 (nodes[1] $lhs, $rhs)>; 718 719foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2], 720 [setgt, GT_F64x2], [setle, LE_F64x2], [setge, GE_F64x2]] in 721def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))), 722 (nodes[1] $lhs, $rhs)>; 723 724//===----------------------------------------------------------------------===// 725// Bitwise operations 726//===----------------------------------------------------------------------===// 727 728multiclass SIMDBinary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 729 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 730 (outs), (ins), 731 [(set (vec.vt V128:$dst), 732 (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))], 733 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 734 vec.prefix#"."#name, simdop>; 735} 736 737multiclass SIMDBitwise<SDPatternOperator node, string name, bits<32> simdop, 738 bit commutable = false> { 739 let isCommutable = commutable in 740 defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 741 (outs), (ins), [], 742 "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>; 743 foreach vec = IntVecs in 744 def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 745 (!cast<NI>(NAME) $lhs, $rhs)>; 746} 747 748multiclass SIMDUnary<Vec vec, SDPatternOperator node, string name, bits<32> simdop> { 749 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), 750 [(set (vec.vt V128:$dst), 751 (vec.vt (node (vec.vt V128:$v))))], 752 vec.prefix#"."#name#"\t$dst, $v", 753 vec.prefix#"."#name, simdop>; 754} 755 756// Bitwise logic: v128.not 757defm NOT : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), [], 758 "v128.not\t$dst, $v", "v128.not", 77>; 759foreach vec = IntVecs in 760def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>; 761 762// Bitwise logic: v128.and / v128.or / v128.xor 763defm AND : SIMDBitwise<and, "and", 78, true>; 764defm OR : SIMDBitwise<or, "or", 80, true>; 765defm XOR : SIMDBitwise<xor, "xor", 81, true>; 766 767// Bitwise logic: v128.andnot 768def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>; 769defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>; 770 771// Bitwise select: v128.bitselect 772defm BITSELECT : 773 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [], 774 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>; 775 776foreach vec = AllVecs in 777def : Pat<(vec.vt (int_wasm_bitselect 778 (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))), 779 (BITSELECT $v1, $v2, $c)>; 780 781// Bitselect is equivalent to (c & v1) | (~c & v2) 782foreach vec = IntVecs in 783def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)), 784 (and (vnot V128:$c), (vec.vt V128:$v2)))), 785 (BITSELECT $v1, $v2, $c)>; 786 787// Also implement vselect in terms of bitselect 788foreach vec = AllVecs in 789def : Pat<(vec.vt (vselect 790 (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))), 791 (BITSELECT $v1, $v2, $c)>; 792 793// MVP select on v128 values 794defm SELECT_V128 : 795 I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [], 796 "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>; 797 798foreach vec = AllVecs in { 799def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 800 (SELECT_V128 $lhs, $rhs, $cond)>; 801 802// ISD::SELECT requires its operand to conform to getBooleanContents, but 803// WebAssembly's select interprets any non-zero value as true, so we can fold 804// a setne with 0 into a select. 805def : Pat<(select 806 (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 807 (SELECT_V128 $lhs, $rhs, $cond)>; 808 809// And again, this time with seteq instead of setne and the arms reversed. 810def : Pat<(select 811 (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 812 (SELECT_V128 $rhs, $lhs, $cond)>; 813} // foreach vec 814 815//===----------------------------------------------------------------------===// 816// Integer unary arithmetic 817//===----------------------------------------------------------------------===// 818 819multiclass SIMDUnaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 820 defm "" : SIMDUnary<I8x16, node, name, baseInst>; 821 defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>; 822 defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>; 823 defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>; 824} 825 826// Integer vector negation 827def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>; 828 829// Integer absolute value: abs 830defm ABS : SIMDUnaryInt<abs, "abs", 96>; 831 832// Integer negation: neg 833defm NEG : SIMDUnaryInt<ivneg, "neg", 97>; 834 835// Population count: popcnt 836defm POPCNT : SIMDUnary<I8x16, ctpop, "popcnt", 0x62>; 837 838// Any lane true: any_true 839defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [], 840 "v128.any_true\t$dst, $vec", "v128.any_true", 0x53>; 841 842foreach vec = IntVecs in 843def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>; 844 845// All lanes true: all_true 846multiclass SIMDAllTrue<Vec vec, bits<32> simdop> { 847 defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 848 [(set I32:$dst, 849 (i32 (int_wasm_alltrue (vec.vt V128:$vec))))], 850 vec.prefix#".all_true\t$dst, $vec", 851 vec.prefix#".all_true", simdop>; 852} 853 854defm "" : SIMDAllTrue<I8x16, 0x63>; 855defm "" : SIMDAllTrue<I16x8, 0x83>; 856defm "" : SIMDAllTrue<I32x4, 0xa3>; 857defm "" : SIMDAllTrue<I64x2, 0xc3>; 858 859// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1 860// can be folded out 861foreach reduction = 862 [["int_wasm_anytrue", "ANYTRUE", "I8x16"], 863 ["int_wasm_anytrue", "ANYTRUE", "I16x8"], 864 ["int_wasm_anytrue", "ANYTRUE", "I32x4"], 865 ["int_wasm_anytrue", "ANYTRUE", "I64x2"], 866 ["int_wasm_alltrue", "ALLTRUE_I8x16", "I8x16"], 867 ["int_wasm_alltrue", "ALLTRUE_I16x8", "I16x8"], 868 ["int_wasm_alltrue", "ALLTRUE_I32x4", "I32x4"], 869 ["int_wasm_alltrue", "ALLTRUE_I64x2", "I64x2"]] in { 870defvar intrinsic = !cast<Intrinsic>(reduction[0]); 871defvar inst = !cast<NI>(reduction[1]); 872defvar vec = !cast<Vec>(reduction[2]); 873def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 874def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>; 875def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>; 876} 877 878multiclass SIMDBitmask<Vec vec, bits<32> simdop> { 879 defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), 880 [(set I32:$dst, 881 (i32 (int_wasm_bitmask (vec.vt V128:$vec))))], 882 vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask", 883 simdop>; 884} 885 886defm BITMASK : SIMDBitmask<I8x16, 100>; 887defm BITMASK : SIMDBitmask<I16x8, 132>; 888defm BITMASK : SIMDBitmask<I32x4, 164>; 889defm BITMASK : SIMDBitmask<I64x2, 196>; 890 891//===----------------------------------------------------------------------===// 892// Bit shifts 893//===----------------------------------------------------------------------===// 894 895multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> { 896 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins), 897 [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))], 898 vec.prefix#"."#name#"\t$dst, $vec, $x", 899 vec.prefix#"."#name, simdop>; 900} 901 902multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> { 903 defm "" : SIMDShift<I8x16, node, name, baseInst>; 904 defm "" : SIMDShift<I16x8, node, name, !add(baseInst, 32)>; 905 defm "" : SIMDShift<I32x4, node, name, !add(baseInst, 64)>; 906 defm "" : SIMDShift<I64x2, node, name, !add(baseInst, 96)>; 907} 908 909// WebAssembly SIMD shifts are nonstandard in that the shift amount is 910// an i32 rather than a vector, so they need custom nodes. 911def wasm_shift_t : 912 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>; 913def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>; 914def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>; 915def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>; 916 917// Left shift by scalar: shl 918defm SHL : SIMDShiftInt<wasm_shl, "shl", 107>; 919 920// Right shift by scalar: shr_s / shr_u 921defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>; 922defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>; 923 924// Optimize away an explicit mask on a shift count. 925def : Pat<(wasm_shl (v16i8 V128:$lhs), (and I32:$rhs, 7)), 926 (SHL_I8x16 V128:$lhs, I32:$rhs)>; 927def : Pat<(wasm_shr_s (v16i8 V128:$lhs), (and I32:$rhs, 7)), 928 (SHR_S_I8x16 V128:$lhs, I32:$rhs)>; 929def : Pat<(wasm_shr_u (v16i8 V128:$lhs), (and I32:$rhs, 7)), 930 (SHR_U_I8x16 V128:$lhs, I32:$rhs)>; 931 932def : Pat<(wasm_shl (v8i16 V128:$lhs), (and I32:$rhs, 15)), 933 (SHL_I16x8 V128:$lhs, I32:$rhs)>; 934def : Pat<(wasm_shr_s (v8i16 V128:$lhs), (and I32:$rhs, 15)), 935 (SHR_S_I16x8 V128:$lhs, I32:$rhs)>; 936def : Pat<(wasm_shr_u (v8i16 V128:$lhs), (and I32:$rhs, 15)), 937 (SHR_U_I16x8 V128:$lhs, I32:$rhs)>; 938 939def : Pat<(wasm_shl (v4i32 V128:$lhs), (and I32:$rhs, 31)), 940 (SHL_I32x4 V128:$lhs, I32:$rhs)>; 941def : Pat<(wasm_shr_s (v4i32 V128:$lhs), (and I32:$rhs, 31)), 942 (SHR_S_I32x4 V128:$lhs, I32:$rhs)>; 943def : Pat<(wasm_shr_u (v4i32 V128:$lhs), (and I32:$rhs, 31)), 944 (SHR_U_I32x4 V128:$lhs, I32:$rhs)>; 945 946def : Pat<(wasm_shl (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 947 (SHL_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 948def : Pat<(wasm_shr_s (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 949 (SHR_S_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 950def : Pat<(wasm_shr_u (v2i64 V128:$lhs), (trunc (and I64:$rhs, 63))), 951 (SHR_U_I64x2 V128:$lhs, (I32_WRAP_I64 I64:$rhs))>; 952 953//===----------------------------------------------------------------------===// 954// Integer binary arithmetic 955//===----------------------------------------------------------------------===// 956 957multiclass SIMDBinaryIntNoI8x16<SDPatternOperator node, string name, bits<32> baseInst> { 958 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 959 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 960 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 961} 962 963multiclass SIMDBinaryIntSmall<SDPatternOperator node, string name, bits<32> baseInst> { 964 defm "" : SIMDBinary<I8x16, node, name, baseInst>; 965 defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>; 966} 967 968multiclass SIMDBinaryIntNoI64x2<SDPatternOperator node, string name, bits<32> baseInst> { 969 defm "" : SIMDBinaryIntSmall<node, name, baseInst>; 970 defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>; 971} 972 973multiclass SIMDBinaryInt<SDPatternOperator node, string name, bits<32> baseInst> { 974 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>; 975 defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>; 976} 977 978// Integer addition: add / add_sat_s / add_sat_u 979let isCommutable = 1 in { 980defm ADD : SIMDBinaryInt<add, "add", 110>; 981defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_sat_s", 111>; 982defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_sat_u", 112>; 983} // isCommutable = 1 984 985// Integer subtraction: sub / sub_sat_s / sub_sat_u 986defm SUB : SIMDBinaryInt<sub, "sub", 113>; 987defm SUB_SAT_S : 988 SIMDBinaryIntSmall<int_wasm_sub_sat_signed, "sub_sat_s", 114>; 989defm SUB_SAT_U : 990 SIMDBinaryIntSmall<int_wasm_sub_sat_unsigned, "sub_sat_u", 115>; 991 992// Integer multiplication: mul 993let isCommutable = 1 in 994defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>; 995 996// Integer min_s / min_u / max_s / max_u 997let isCommutable = 1 in { 998defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>; 999defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>; 1000defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>; 1001defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>; 1002} // isCommutable = 1 1003 1004// Integer unsigned rounding average: avgr_u 1005let isCommutable = 1 in { 1006defm AVGR_U : SIMDBinary<I8x16, int_wasm_avgr_unsigned, "avgr_u", 123>; 1007defm AVGR_U : SIMDBinary<I16x8, int_wasm_avgr_unsigned, "avgr_u", 155>; 1008} 1009 1010def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), (add $lhs, $rhs), 1011 "return N->getFlags().hasNoUnsignedWrap();">; 1012 1013foreach vec = [I8x16, I16x8] in { 1014defvar inst = !cast<NI>("AVGR_U_"#vec); 1015def : Pat<(wasm_shr_u 1016 (add_nuw 1017 (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)), 1018 (vec.splat (i32 1))), 1019 (i32 1)), 1020 (inst $lhs, $rhs)>; 1021} 1022 1023// Widening dot product: i32x4.dot_i16x8_s 1024let isCommutable = 1 in 1025defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins), 1026 [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))], 1027 "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s", 1028 186>; 1029 1030// Extending multiplication: extmul_{low,high}_P, extmul_high 1031def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1032def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>; 1033def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>; 1034def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>; 1035def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>; 1036 1037multiclass SIMDExtBinary<Vec vec, SDPatternOperator node, string name, 1038 bits<32> simdop> { 1039 defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), 1040 (outs), (ins), 1041 [(set (vec.vt V128:$dst), (node 1042 (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))], 1043 vec.prefix#"."#name#"\t$dst, $lhs, $rhs", 1044 vec.prefix#"."#name, simdop>; 1045} 1046 1047class ExtMulPat<SDNode extend> : 1048 PatFrag<(ops node:$lhs, node:$rhs), 1049 (mul (extend $lhs), (extend $rhs))> {} 1050 1051def extmul_low_s : ExtMulPat<extend_low_s>; 1052def extmul_high_s : ExtMulPat<extend_high_s>; 1053def extmul_low_u : ExtMulPat<extend_low_u>; 1054def extmul_high_u : ExtMulPat<extend_high_u>; 1055 1056defm EXTMUL_LOW_S : 1057 SIMDExtBinary<I16x8, extmul_low_s, "extmul_low_i8x16_s", 0x9c>; 1058defm EXTMUL_HIGH_S : 1059 SIMDExtBinary<I16x8, extmul_high_s, "extmul_high_i8x16_s", 0x9d>; 1060defm EXTMUL_LOW_U : 1061 SIMDExtBinary<I16x8, extmul_low_u, "extmul_low_i8x16_u", 0x9e>; 1062defm EXTMUL_HIGH_U : 1063 SIMDExtBinary<I16x8, extmul_high_u, "extmul_high_i8x16_u", 0x9f>; 1064 1065defm EXTMUL_LOW_S : 1066 SIMDExtBinary<I32x4, extmul_low_s, "extmul_low_i16x8_s", 0xbc>; 1067defm EXTMUL_HIGH_S : 1068 SIMDExtBinary<I32x4, extmul_high_s, "extmul_high_i16x8_s", 0xbd>; 1069defm EXTMUL_LOW_U : 1070 SIMDExtBinary<I32x4, extmul_low_u, "extmul_low_i16x8_u", 0xbe>; 1071defm EXTMUL_HIGH_U : 1072 SIMDExtBinary<I32x4, extmul_high_u, "extmul_high_i16x8_u", 0xbf>; 1073 1074defm EXTMUL_LOW_S : 1075 SIMDExtBinary<I64x2, extmul_low_s, "extmul_low_i32x4_s", 0xdc>; 1076defm EXTMUL_HIGH_S : 1077 SIMDExtBinary<I64x2, extmul_high_s, "extmul_high_i32x4_s", 0xdd>; 1078defm EXTMUL_LOW_U : 1079 SIMDExtBinary<I64x2, extmul_low_u, "extmul_low_i32x4_u", 0xde>; 1080defm EXTMUL_HIGH_U : 1081 SIMDExtBinary<I64x2, extmul_high_u, "extmul_high_i32x4_u", 0xdf>; 1082 1083//===----------------------------------------------------------------------===// 1084// Floating-point unary arithmetic 1085//===----------------------------------------------------------------------===// 1086 1087multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> { 1088 defm "" : SIMDUnary<F32x4, node, name, baseInst>; 1089 defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>; 1090} 1091 1092// Absolute value: abs 1093defm ABS : SIMDUnaryFP<fabs, "abs", 224>; 1094 1095// Negation: neg 1096defm NEG : SIMDUnaryFP<fneg, "neg", 225>; 1097 1098// Square root: sqrt 1099defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>; 1100 1101// Rounding: ceil, floor, trunc, nearest 1102defm CEIL : SIMDUnary<F32x4, fceil, "ceil", 0x67>; 1103defm FLOOR : SIMDUnary<F32x4, ffloor, "floor", 0x68>; 1104defm TRUNC: SIMDUnary<F32x4, ftrunc, "trunc", 0x69>; 1105defm NEAREST: SIMDUnary<F32x4, fnearbyint, "nearest", 0x6a>; 1106defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>; 1107defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>; 1108defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>; 1109defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>; 1110 1111//===----------------------------------------------------------------------===// 1112// Floating-point binary arithmetic 1113//===----------------------------------------------------------------------===// 1114 1115multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> { 1116 defm "" : SIMDBinary<F32x4, node, name, baseInst>; 1117 defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>; 1118} 1119 1120// Addition: add 1121let isCommutable = 1 in 1122defm ADD : SIMDBinaryFP<fadd, "add", 228>; 1123 1124// Subtraction: sub 1125defm SUB : SIMDBinaryFP<fsub, "sub", 229>; 1126 1127// Multiplication: mul 1128let isCommutable = 1 in 1129defm MUL : SIMDBinaryFP<fmul, "mul", 230>; 1130 1131// Division: div 1132defm DIV : SIMDBinaryFP<fdiv, "div", 231>; 1133 1134// NaN-propagating minimum: min 1135defm MIN : SIMDBinaryFP<fminimum, "min", 232>; 1136 1137// NaN-propagating maximum: max 1138defm MAX : SIMDBinaryFP<fmaximum, "max", 233>; 1139 1140// Pseudo-minimum: pmin 1141def pmin : PatFrag<(ops node:$lhs, node:$rhs), 1142 (vselect (setolt $rhs, $lhs), $rhs, $lhs)>; 1143defm PMIN : SIMDBinaryFP<pmin, "pmin", 234>; 1144 1145// Pseudo-maximum: pmax 1146def pmax : PatFrag<(ops node:$lhs, node:$rhs), 1147 (vselect (setolt $lhs, $rhs), $rhs, $lhs)>; 1148defm PMAX : SIMDBinaryFP<pmax, "pmax", 235>; 1149 1150// Also match the pmin/pmax cases where the operands are int vectors (but the 1151// comparison is still a floating point comparison). This can happen when using 1152// the wasm_simd128.h intrinsics because v128_t is an integer vector. 1153foreach vec = [F32x4, F64x2] in { 1154defvar pmin = !cast<NI>("PMIN_"#vec); 1155defvar pmax = !cast<NI>("PMAX_"#vec); 1156def : Pat<(vec.int_vt (vselect 1157 (setolt (vec.vt (bitconvert V128:$rhs)), 1158 (vec.vt (bitconvert V128:$lhs))), 1159 V128:$rhs, V128:$lhs)), 1160 (pmin $lhs, $rhs)>; 1161def : Pat<(vec.int_vt (vselect 1162 (setolt (vec.vt (bitconvert V128:$lhs)), 1163 (vec.vt (bitconvert V128:$rhs))), 1164 V128:$rhs, V128:$lhs)), 1165 (pmax $lhs, $rhs)>; 1166} 1167 1168//===----------------------------------------------------------------------===// 1169// Conversions 1170//===----------------------------------------------------------------------===// 1171 1172multiclass SIMDConvert<Vec vec, Vec arg, SDPatternOperator op, string name, 1173 bits<32> simdop> { 1174 defm op#_#vec : 1175 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins), 1176 [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))], 1177 vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>; 1178} 1179 1180// Floating point to integer with saturation: trunc_sat 1181defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>; 1182defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>; 1183 1184// Support the saturating variety as well. 1185def trunc_s_sat32 : PatFrag<(ops node:$x), (fp_to_sint_sat $x, i32)>; 1186def trunc_u_sat32 : PatFrag<(ops node:$x), (fp_to_uint_sat $x, i32)>; 1187def : Pat<(v4i32 (trunc_s_sat32 (v4f32 V128:$src))), (fp_to_sint_I32x4 $src)>; 1188def : Pat<(v4i32 (trunc_u_sat32 (v4f32 V128:$src))), (fp_to_uint_I32x4 $src)>; 1189 1190def trunc_sat_zero_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1191def trunc_sat_zero_s : 1192 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_S", trunc_sat_zero_t>; 1193def trunc_sat_zero_u : 1194 SDNode<"WebAssemblyISD::TRUNC_SAT_ZERO_U", trunc_sat_zero_t>; 1195defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_s, "trunc_sat_zero_f64x2_s", 1196 0xfc>; 1197defm "" : SIMDConvert<I32x4, F64x2, trunc_sat_zero_u, "trunc_sat_zero_f64x2_u", 1198 0xfd>; 1199 1200// Integer to floating point: convert 1201def convert_low_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1202def convert_low_s : SDNode<"WebAssemblyISD::CONVERT_LOW_S", convert_low_t>; 1203def convert_low_u : SDNode<"WebAssemblyISD::CONVERT_LOW_U", convert_low_t>; 1204defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>; 1205defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>; 1206defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>; 1207defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>; 1208 1209// Extending operations 1210// TODO: refactor this to be uniform for i64x2 if the numbering is not changed. 1211multiclass SIMDExtend<Vec vec, bits<32> baseInst> { 1212 defm "" : SIMDConvert<vec, vec.split, extend_low_s, 1213 "extend_low_"#vec.split.prefix#"_s", baseInst>; 1214 defm "" : SIMDConvert<vec, vec.split, extend_high_s, 1215 "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>; 1216 defm "" : SIMDConvert<vec, vec.split, extend_low_u, 1217 "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>; 1218 defm "" : SIMDConvert<vec, vec.split, extend_high_u, 1219 "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>; 1220} 1221 1222defm "" : SIMDExtend<I16x8, 0x87>; 1223defm "" : SIMDExtend<I32x4, 0xa7>; 1224defm "" : SIMDExtend<I64x2, 0xc7>; 1225 1226// Narrowing operations 1227multiclass SIMDNarrow<Vec vec, bits<32> baseInst> { 1228 defvar name = vec.split.prefix#".narrow_"#vec.prefix; 1229 defm NARROW_S_#vec.split : 1230 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1231 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed 1232 (vec.vt V128:$low), (vec.vt V128:$high))))], 1233 name#"_s\t$dst, $low, $high", name#"_s", baseInst>; 1234 defm NARROW_U_#vec.split : 1235 SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins), 1236 [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned 1237 (vec.vt V128:$low), (vec.vt V128:$high))))], 1238 name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>; 1239} 1240 1241defm "" : SIMDNarrow<I16x8, 101>; 1242defm "" : SIMDNarrow<I32x4, 133>; 1243 1244// Use narrowing operations for truncating stores. Since the narrowing 1245// operations are saturating instead of truncating, we need to mask 1246// the stored values first. 1247def store_v8i8_trunc_v8i16 : 1248 OutPatFrag<(ops node:$val), 1249 (EXTRACT_LANE_I64x2 1250 (NARROW_U_I8x16 1251 (AND 1252 (CONST_V128_I16x8 1253 0x00ff, 0x00ff, 0x00ff, 0x00ff, 1254 0x00ff, 0x00ff, 0x00ff, 0x00ff), 1255 node:$val), 1256 $val), // Unused input 1257 0)>; 1258 1259def store_v4i16_trunc_v4i32 : 1260 OutPatFrag<(ops node:$val), 1261 (EXTRACT_LANE_I64x2 1262 (NARROW_U_I16x8 1263 (AND 1264 (CONST_V128_I32x4 1265 0x0000ffff, 0x0000ffff, 0x0000ffff, 0x0000ffff), 1266 node:$val), 1267 $val), // Unused input 1268 0)>; 1269 1270// Store patterns adapted from WebAssemblyInstrMemory.td 1271multiclass NarrowingStorePatNoOffset<Vec vec, OutPatFrag out> { 1272 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1273 def : Pat<(node vec.vt:$val, I32:$addr), 1274 (STORE_I64_A32 0, 0, $addr, (out $val))>, 1275 Requires<[HasAddr32]>; 1276 def : Pat<(node vec.vt:$val, I64:$addr), 1277 (STORE_I64_A64 0, 0, $addr, (out $val))>, 1278 Requires<[HasAddr64]>; 1279} 1280 1281defm : NarrowingStorePatNoOffset<I16x8, store_v8i8_trunc_v8i16>; 1282defm : NarrowingStorePatNoOffset<I32x4, store_v4i16_trunc_v4i32>; 1283 1284multiclass NarrowingStorePatImmOff<Vec vec, PatFrag operand, OutPatFrag out> { 1285 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1286 def : Pat<(node vec.vt:$val, (operand I32:$addr, imm:$off)), 1287 (STORE_I64_A32 0, imm:$off, $addr, (out $val))>, 1288 Requires<[HasAddr32]>; 1289 def : Pat<(node vec.vt:$val, (operand I64:$addr, imm:$off)), 1290 (STORE_I64_A64 0, imm:$off, $addr, (out $val))>, 1291 Requires<[HasAddr64]>; 1292} 1293 1294defm : NarrowingStorePatImmOff<I16x8, regPlusImm, store_v8i8_trunc_v8i16>; 1295defm : NarrowingStorePatImmOff<I32x4, regPlusImm, store_v4i16_trunc_v4i32>; 1296defm : NarrowingStorePatImmOff<I16x8, or_is_add, store_v8i8_trunc_v8i16>; 1297defm : NarrowingStorePatImmOff<I32x4, or_is_add, store_v4i16_trunc_v4i32>; 1298 1299multiclass NarrowingStorePatOffsetOnly<Vec vec, OutPatFrag out> { 1300 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1301 def : Pat<(node vec.vt:$val, imm:$off), 1302 (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (out $val))>, 1303 Requires<[HasAddr32]>; 1304 def : Pat<(node vec.vt:$val, imm:$off), 1305 (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (out $val))>, 1306 Requires<[HasAddr64]>; 1307} 1308 1309defm : NarrowingStorePatOffsetOnly<I16x8, store_v8i8_trunc_v8i16>; 1310defm : NarrowingStorePatOffsetOnly<I32x4, store_v4i16_trunc_v4i32>; 1311 1312multiclass NarrowingStorePatGlobalAddrOffOnly<Vec vec, OutPatFrag out> { 1313 defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits); 1314 def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)), 1315 (STORE_I64_A32 0, tglobaladdr:$off, (CONST_I32 0), (out $val))>, 1316 Requires<[IsNotPIC, HasAddr32]>; 1317 def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)), 1318 (STORE_I64_A64 0, tglobaladdr:$off, (CONST_I64 0), (out $val))>, 1319 Requires<[IsNotPIC, HasAddr64]>; 1320} 1321 1322defm : NarrowingStorePatGlobalAddrOffOnly<I16x8, store_v8i8_trunc_v8i16>; 1323defm : NarrowingStorePatGlobalAddrOffOnly<I32x4, store_v4i16_trunc_v4i32>; 1324 1325// Bitcasts are nops 1326// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types 1327foreach t1 = AllVecs in 1328foreach t2 = AllVecs in 1329if !ne(t1, t2) then 1330def : Pat<(t1.vt (bitconvert (t2.vt V128:$v))), (t1.vt V128:$v)>; 1331 1332// Extended pairwise addition 1333defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed, 1334 "extadd_pairwise_i8x16_s", 0x7c>; 1335defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned, 1336 "extadd_pairwise_i8x16_u", 0x7d>; 1337defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed, 1338 "extadd_pairwise_i16x8_s", 0x7e>; 1339defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned, 1340 "extadd_pairwise_i16x8_u", 0x7f>; 1341 1342// f64x2 <-> f32x4 conversions 1343def demote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1344def demote_zero : SDNode<"WebAssemblyISD::DEMOTE_ZERO", demote_t>; 1345defm "" : SIMDConvert<F32x4, F64x2, demote_zero, 1346 "demote_zero_f64x2", 0x5e>; 1347 1348def promote_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>; 1349def promote_low : SDNode<"WebAssemblyISD::PROMOTE_LOW", promote_t>; 1350defm "" : SIMDConvert<F64x2, F32x4, promote_low, "promote_low_f32x4", 0x5f>; 1351 1352//===----------------------------------------------------------------------===// 1353// Saturating Rounding Q-Format Multiplication 1354//===----------------------------------------------------------------------===// 1355 1356defm Q15MULR_SAT_S : 1357 SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>; 1358