xref: /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// WebAssembly SIMD operand code-gen constructs.
11///
12//===----------------------------------------------------------------------===//
13
14// Instructions requiring HasSIMD128 and the simd128 prefix byte
15multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
16                  list<dag> pattern_r, string asmstr_r = "",
17                  string asmstr_s = "", bits<32> simdop = -1> {
18  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
19              !if(!ge(simdop, 0x100),
20                  !or(0xfd0000, !and(0xffff, simdop)),
21                  !or(0xfd00, !and(0xff, simdop)))>,
22            Requires<[HasSIMD128]>;
23}
24
25defm "" : ARGUMENT<V128, v16i8>;
26defm "" : ARGUMENT<V128, v8i16>;
27defm "" : ARGUMENT<V128, v4i32>;
28defm "" : ARGUMENT<V128, v2i64>;
29defm "" : ARGUMENT<V128, v4f32>;
30defm "" : ARGUMENT<V128, v2f64>;
31
32// Constrained immediate argument types
33foreach SIZE = [8, 16] in
34def ImmI#SIZE : ImmLeaf<i32,
35  "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
36>;
37foreach SIZE = [2, 4, 8, 16, 32] in
38def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
39
40// Create vector with identical lanes: splat
41def splat2 : PatFrag<(ops node:$x), (build_vector $x, $x)>;
42def splat4 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x)>;
43def splat8 : PatFrag<(ops node:$x), (build_vector $x, $x, $x, $x,
44                                                  $x, $x, $x, $x)>;
45def splat16 : PatFrag<(ops node:$x),
46                      (build_vector $x, $x, $x, $x, $x, $x, $x, $x,
47                                    $x, $x, $x, $x, $x, $x, $x, $x)>;
48
49class Vec {
50  ValueType vt;
51  ValueType int_vt;
52  ValueType lane_vt;
53  WebAssemblyRegClass lane_rc;
54  int lane_bits;
55  ImmLeaf lane_idx;
56  PatFrag splat;
57  string prefix;
58  Vec split;
59}
60
61def I8x16 : Vec {
62  let vt = v16i8;
63  let int_vt = vt;
64  let lane_vt = i32;
65  let lane_rc = I32;
66  let lane_bits = 8;
67  let lane_idx = LaneIdx16;
68  let splat = splat16;
69  let prefix = "i8x16";
70}
71
72def I16x8 : Vec {
73  let vt = v8i16;
74  let int_vt = vt;
75  let lane_vt = i32;
76  let lane_rc = I32;
77  let lane_bits = 16;
78  let lane_idx = LaneIdx8;
79  let splat = splat8;
80  let prefix = "i16x8";
81  let split = I8x16;
82}
83
84def I32x4 : Vec {
85  let vt = v4i32;
86  let int_vt = vt;
87  let lane_vt = i32;
88  let lane_rc = I32;
89  let lane_bits = 32;
90  let lane_idx = LaneIdx4;
91  let splat = splat4;
92  let prefix = "i32x4";
93  let split = I16x8;
94}
95
96def I64x2 : Vec {
97  let vt = v2i64;
98  let int_vt = vt;
99  let lane_vt = i64;
100  let lane_rc = I64;
101  let lane_bits = 64;
102  let lane_idx = LaneIdx2;
103  let splat = splat2;
104  let prefix = "i64x2";
105  let split = I32x4;
106}
107
108def F32x4 : Vec {
109  let vt = v4f32;
110  let int_vt = v4i32;
111  let lane_vt = f32;
112  let lane_rc = F32;
113  let lane_bits = 32;
114  let lane_idx = LaneIdx4;
115  let splat = splat4;
116  let prefix = "f32x4";
117}
118
119def F64x2 : Vec {
120  let vt = v2f64;
121  let int_vt = v2i64;
122  let lane_vt = f64;
123  let lane_rc = F64;
124  let lane_bits = 64;
125  let lane_idx = LaneIdx2;
126  let splat = splat2;
127  let prefix = "f64x2";
128}
129
130defvar AllVecs = [I8x16, I16x8, I32x4, I64x2, F32x4, F64x2];
131defvar IntVecs = [I8x16, I16x8, I32x4, I64x2];
132
133//===----------------------------------------------------------------------===//
134// Load and store
135//===----------------------------------------------------------------------===//
136
137// Load: v128.load
138let mayLoad = 1, UseNamedOperandTable = 1 in {
139defm LOAD_V128_A32 :
140  SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
141         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
142         "v128.load\t$dst, ${off}(${addr})$p2align",
143         "v128.load\t$off$p2align", 0>;
144defm LOAD_V128_A64 :
145  SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
146         (outs), (ins P2Align:$p2align, offset64_op:$off), [],
147         "v128.load\t$dst, ${off}(${addr})$p2align",
148         "v128.load\t$off$p2align", 0>;
149}
150
151// Def load patterns from WebAssemblyInstrMemory.td for vector types
152foreach vec = AllVecs in {
153defm : LoadPatNoOffset<vec.vt, load, "LOAD_V128">;
154defm : LoadPatImmOff<vec.vt, load, regPlusImm, "LOAD_V128">;
155defm : LoadPatImmOff<vec.vt, load, or_is_add, "LOAD_V128">;
156defm : LoadPatOffsetOnly<vec.vt, load, "LOAD_V128">;
157defm : LoadPatGlobalAddrOffOnly<vec.vt, load, "LOAD_V128">;
158}
159
160// v128.loadX_splat
161multiclass SIMDLoadSplat<int size, bits<32> simdop> {
162  let mayLoad = 1, UseNamedOperandTable = 1 in {
163  defm LOAD#size#_SPLAT_A32 :
164    SIMD_I<(outs V128:$dst),
165           (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
166           (outs),
167           (ins P2Align:$p2align, offset32_op:$off), [],
168           "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
169           "v128.load"#size#"_splat\t$off$p2align", simdop>;
170  defm LOAD#size#_SPLAT_A64 :
171    SIMD_I<(outs V128:$dst),
172           (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
173           (outs),
174           (ins P2Align:$p2align, offset64_op:$off), [],
175           "v128.load"#size#"_splat\t$dst, ${off}(${addr})$p2align",
176           "v128.load"#size#"_splat\t$off$p2align", simdop>;
177  }
178}
179
180defm "" : SIMDLoadSplat<8, 7>;
181defm "" : SIMDLoadSplat<16, 8>;
182defm "" : SIMDLoadSplat<32, 9>;
183defm "" : SIMDLoadSplat<64, 10>;
184
185def wasm_load_splat_t : SDTypeProfile<1, 1, [SDTCisPtrTy<1>]>;
186def wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t,
187                             [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
188def load_splat : PatFrag<(ops node:$addr), (wasm_load_splat node:$addr)>;
189
190foreach vec = AllVecs in {
191defvar inst = "LOAD"#vec.lane_bits#"_SPLAT";
192defm : LoadPatNoOffset<vec.vt, load_splat, inst>;
193defm : LoadPatImmOff<vec.vt, load_splat, regPlusImm, inst>;
194defm : LoadPatImmOff<vec.vt, load_splat, or_is_add, inst>;
195defm : LoadPatOffsetOnly<vec.vt, load_splat, inst>;
196defm : LoadPatGlobalAddrOffOnly<vec.vt, load_splat, inst>;
197}
198
199// Load and extend
200multiclass SIMDLoadExtend<Vec vec, string loadPat, bits<32> simdop> {
201  defvar signed = vec.prefix#".load"#loadPat#"_s";
202  defvar unsigned = vec.prefix#".load"#loadPat#"_u";
203  let mayLoad = 1, UseNamedOperandTable = 1 in {
204  defm LOAD_EXTEND_S_#vec#_A32 :
205    SIMD_I<(outs V128:$dst),
206           (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
207           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
208           signed#"\t$dst, ${off}(${addr})$p2align",
209           signed#"\t$off$p2align", simdop>;
210  defm LOAD_EXTEND_U_#vec#_A32 :
211    SIMD_I<(outs V128:$dst),
212           (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
213           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
214           unsigned#"\t$dst, ${off}(${addr})$p2align",
215           unsigned#"\t$off$p2align", !add(simdop, 1)>;
216  defm LOAD_EXTEND_S_#vec#_A64 :
217    SIMD_I<(outs V128:$dst),
218           (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
219           (outs), (ins P2Align:$p2align, offset64_op:$off), [],
220           signed#"\t$dst, ${off}(${addr})$p2align",
221           signed#"\t$off$p2align", simdop>;
222  defm LOAD_EXTEND_U_#vec#_A64 :
223    SIMD_I<(outs V128:$dst),
224           (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
225           (outs), (ins P2Align:$p2align, offset64_op:$off), [],
226           unsigned#"\t$dst, ${off}(${addr})$p2align",
227           unsigned#"\t$off$p2align", !add(simdop, 1)>;
228  }
229}
230
231defm "" : SIMDLoadExtend<I16x8, "8x8", 1>;
232defm "" : SIMDLoadExtend<I32x4, "16x4", 3>;
233defm "" : SIMDLoadExtend<I64x2, "32x2", 5>;
234
235foreach vec = [I16x8, I32x4, I64x2] in
236foreach exts = [["sextloadvi", "_S"],
237                ["zextloadvi", "_U"],
238                ["extloadvi", "_U"]] in {
239defvar loadpat = !cast<PatFrag>(exts[0]#vec.split.lane_bits);
240defvar inst = "LOAD_EXTEND"#exts[1]#"_"#vec;
241defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
242defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
243defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
244defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
245defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>;
246}
247
248// Load lane into zero vector
249multiclass SIMDLoadZero<Vec vec, bits<32> simdop> {
250  defvar name = "v128.load"#vec.lane_bits#"_zero";
251  let mayLoad = 1, UseNamedOperandTable = 1 in {
252  defm LOAD_ZERO_#vec#_A32 :
253    SIMD_I<(outs V128:$dst),
254           (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
255           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
256           name#"\t$dst, ${off}(${addr})$p2align",
257           name#"\t$off$p2align", simdop>;
258  defm LOAD_ZERO_#vec#_A64 :
259    SIMD_I<(outs V128:$dst),
260           (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
261           (outs), (ins P2Align:$p2align, offset64_op:$off), [],
262           name#"\t$dst, ${off}(${addr})$p2align",
263           name#"\t$off$p2align", simdop>;
264  } // mayLoad = 1, UseNamedOperandTable = 1
265}
266
267// TODO: Also support v4f32 and v2f64 once the instructions are merged
268// to the proposal
269defm "" : SIMDLoadZero<I32x4, 252>;
270defm "" : SIMDLoadZero<I64x2, 253>;
271
272foreach vec = [I32x4, I64x2] in {
273defvar loadpat = !cast<Intrinsic>("int_wasm_load"#vec.lane_bits#"_zero");
274defvar inst = "LOAD_ZERO_"#vec;
275defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
276defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
277defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
278defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
279defm : LoadPatGlobalAddrOffOnly<vec.vt, loadpat, inst>;
280}
281
282// Load lane
283multiclass SIMDLoadLane<Vec vec, bits<32> simdop> {
284  defvar name = "v128.load"#vec.lane_bits#"_lane";
285  let mayLoad = 1, UseNamedOperandTable = 1 in {
286  defm LOAD_LANE_#vec#_A32 :
287    SIMD_I<(outs V128:$dst),
288           (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
289                I32:$addr, V128:$vec),
290           (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
291           [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
292           name#"\t$off$p2align, $idx", simdop>;
293  defm LOAD_LANE_#vec#_A64 :
294    SIMD_I<(outs V128:$dst),
295           (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
296                I64:$addr, V128:$vec),
297           (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
298           [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
299           name#"\t$off$p2align, $idx", simdop>;
300  } // mayLoad = 1, UseNamedOperandTable = 1
301}
302
303// TODO: Also support v4f32 and v2f64 once the instructions are merged
304// to the proposal
305defm "" : SIMDLoadLane<I8x16, 88>;
306defm "" : SIMDLoadLane<I16x8, 89>;
307defm "" : SIMDLoadLane<I32x4, 90>;
308defm "" : SIMDLoadLane<I64x2, 91>;
309
310// Select loads with no constant offset.
311multiclass LoadLanePatNoOffset<Vec vec, PatFrag kind> {
312  defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
313  defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
314  def : Pat<(vec.vt (kind (i32 I32:$addr),
315              (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
316            (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
317        Requires<[HasAddr32]>;
318  def : Pat<(vec.vt (kind (i64 I64:$addr),
319              (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
320            (load_lane_a64 0, 0, imm:$idx, $addr, $vec)>,
321        Requires<[HasAddr64]>;
322}
323
324defm : LoadLanePatNoOffset<I8x16, int_wasm_load8_lane>;
325defm : LoadLanePatNoOffset<I16x8, int_wasm_load16_lane>;
326defm : LoadLanePatNoOffset<I32x4, int_wasm_load32_lane>;
327defm : LoadLanePatNoOffset<I64x2, int_wasm_load64_lane>;
328
329// TODO: Also support the other load patterns for load_lane once the instructions
330// are merged to the proposal.
331
332// Store: v128.store
333let mayStore = 1, UseNamedOperandTable = 1 in {
334defm STORE_V128_A32 :
335  SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
336         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
337         "v128.store\t${off}(${addr})$p2align, $vec",
338         "v128.store\t$off$p2align", 11>;
339defm STORE_V128_A64 :
340  SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr, V128:$vec),
341         (outs), (ins P2Align:$p2align, offset64_op:$off), [],
342         "v128.store\t${off}(${addr})$p2align, $vec",
343         "v128.store\t$off$p2align", 11>;
344}
345
346// Def store patterns from WebAssemblyInstrMemory.td for vector types
347foreach vec = AllVecs in {
348defm : StorePatNoOffset<vec.vt, store, "STORE_V128">;
349defm : StorePatImmOff<vec.vt, store, regPlusImm, "STORE_V128">;
350defm : StorePatImmOff<vec.vt, store, or_is_add, "STORE_V128">;
351defm : StorePatOffsetOnly<vec.vt, store, "STORE_V128">;
352defm : StorePatGlobalAddrOffOnly<vec.vt, store, "STORE_V128">;
353}
354
355// Store lane
356multiclass SIMDStoreLane<Vec vec, bits<32> simdop> {
357  defvar name = "v128.store"#vec.lane_bits#"_lane";
358  let mayStore = 1, UseNamedOperandTable = 1 in {
359  defm STORE_LANE_#vec#_A32 :
360    SIMD_I<(outs),
361           (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx,
362                I32:$addr, V128:$vec),
363           (outs), (ins P2Align:$p2align, offset32_op:$off, vec_i8imm_op:$idx),
364           [], name#"\t${off}(${addr})$p2align, $vec, $idx",
365           name#"\t$off$p2align, $idx", simdop>;
366  defm STORE_LANE_#vec#_A64 :
367    SIMD_I<(outs V128:$dst),
368           (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx,
369                I64:$addr, V128:$vec),
370           (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
371           [], name#"\t${off}(${addr})$p2align, $vec, $idx",
372           name#"\t$off$p2align, $idx", simdop>;
373  } // mayStore = 1, UseNamedOperandTable = 1
374}
375
376// TODO: Also support v4f32 and v2f64 once the instructions are merged
377// to the proposal
378defm "" : SIMDStoreLane<I8x16, 92>;
379defm "" : SIMDStoreLane<I16x8, 93>;
380defm "" : SIMDStoreLane<I32x4, 94>;
381defm "" : SIMDStoreLane<I64x2, 95>;
382
383// Select stores with no constant offset.
384multiclass StoreLanePatNoOffset<Vec vec, PatFrag kind> {
385  def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
386            (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
387        Requires<[HasAddr32]>;
388  def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
389            (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
390        Requires<[HasAddr64]>;
391}
392
393defm : StoreLanePatNoOffset<I8x16, int_wasm_store8_lane>;
394defm : StoreLanePatNoOffset<I16x8, int_wasm_store16_lane>;
395defm : StoreLanePatNoOffset<I32x4, int_wasm_store32_lane>;
396defm : StoreLanePatNoOffset<I64x2, int_wasm_store64_lane>;
397
398// TODO: Also support the other store patterns for store_lane once the
399// instructions are merged to the proposal.
400
401//===----------------------------------------------------------------------===//
402// Constructing SIMD values
403//===----------------------------------------------------------------------===//
404
405// Constant: v128.const
406multiclass ConstVec<Vec vec, dag ops, dag pat, string args> {
407  let isMoveImm = 1, isReMaterializable = 1,
408      Predicates = [HasUnimplementedSIMD128] in
409  defm CONST_V128_#vec : SIMD_I<(outs V128:$dst), ops, (outs), ops,
410                                 [(set V128:$dst, (vec.vt pat))],
411                                 "v128.const\t$dst, "#args,
412                                 "v128.const\t"#args, 12>;
413}
414
415defm "" : ConstVec<I8x16,
416                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
417                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
418                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
419                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
420                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
421                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
422                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
423                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
424                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
425                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
426                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
427                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
428                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
429                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
430defm "" : ConstVec<I16x8,
431                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
432                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
433                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
434                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
435                   (build_vector
436                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
437                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
438                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
439let IsCanonical = 1 in
440defm "" : ConstVec<I32x4,
441                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
442                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
443                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
444                                 (i32 imm:$i2), (i32 imm:$i3)),
445                   "$i0, $i1, $i2, $i3">;
446defm "" : ConstVec<I64x2,
447                   (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
448                   (build_vector (i64 imm:$i0), (i64 imm:$i1)),
449                   "$i0, $i1">;
450defm "" : ConstVec<F32x4,
451                   (ins f32imm_op:$i0, f32imm_op:$i1,
452                        f32imm_op:$i2, f32imm_op:$i3),
453                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
454                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
455                   "$i0, $i1, $i2, $i3">;
456defm "" : ConstVec<F64x2,
457                  (ins f64imm_op:$i0, f64imm_op:$i1),
458                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
459                  "$i0, $i1">;
460
461// Shuffle lanes: shuffle
462defm SHUFFLE :
463  SIMD_I<(outs V128:$dst),
464         (ins V128:$x, V128:$y,
465           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
466           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
467           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
468           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
469           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
470           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
471           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
472           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
473         (outs),
474         (ins
475           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
476           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
477           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
478           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
479           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
480           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
481           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
482           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
483         [],
484         "i8x16.shuffle\t$dst, $x, $y, "#
485           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
486           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
487         "i8x16.shuffle\t"#
488           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
489           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
490         13>;
491
492// Shuffles after custom lowering
493def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
494def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
495foreach vec = AllVecs in {
496def : Pat<(vec.vt (wasm_shuffle (vec.vt V128:$x), (vec.vt V128:$y),
497            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
498            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
499            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
500            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
501            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
502            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
503            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
504            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
505          (SHUFFLE $x, $y,
506            imm:$m0, imm:$m1, imm:$m2, imm:$m3,
507            imm:$m4, imm:$m5, imm:$m6, imm:$m7,
508            imm:$m8, imm:$m9, imm:$mA, imm:$mB,
509            imm:$mC, imm:$mD, imm:$mE, imm:$mF)>;
510}
511
512// Swizzle lanes: i8x16.swizzle
513def wasm_swizzle_t : SDTypeProfile<1, 2, []>;
514def wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
515defm SWIZZLE :
516  SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
517         [(set (v16i8 V128:$dst),
518           (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
519         "i8x16.swizzle\t$dst, $src, $mask", "i8x16.swizzle", 14>;
520
521def : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
522          (SWIZZLE $src, $mask)>;
523
524multiclass Splat<Vec vec, bits<32> simdop> {
525  defm SPLAT_#vec : SIMD_I<(outs V128:$dst), (ins vec.lane_rc:$x),
526                           (outs), (ins),
527                           [(set (vec.vt V128:$dst),
528                              (vec.splat vec.lane_rc:$x))],
529                           vec.prefix#".splat\t$dst, $x", vec.prefix#".splat",
530                           simdop>;
531}
532
533defm "" : Splat<I8x16, 15>;
534defm "" : Splat<I16x8, 16>;
535defm "" : Splat<I32x4, 17>;
536defm "" : Splat<I64x2, 18>;
537defm "" : Splat<F32x4, 19>;
538defm "" : Splat<F64x2, 20>;
539
540// scalar_to_vector leaves high lanes undefined, so can be a splat
541foreach vec = AllVecs in
542def : Pat<(vec.vt (scalar_to_vector (vec.lane_vt vec.lane_rc:$x))),
543          (!cast<Instruction>("SPLAT_"#vec) $x)>;
544
545//===----------------------------------------------------------------------===//
546// Accessing lanes
547//===----------------------------------------------------------------------===//
548
549// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
550multiclass ExtractLane<Vec vec, bits<32> simdop, string suffix = ""> {
551  defm EXTRACT_LANE_#vec#suffix :
552      SIMD_I<(outs vec.lane_rc:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
553             (outs), (ins vec_i8imm_op:$idx), [],
554             vec.prefix#".extract_lane"#suffix#"\t$dst, $vec, $idx",
555             vec.prefix#".extract_lane"#suffix#"\t$idx", simdop>;
556}
557
558defm "" : ExtractLane<I8x16, 21, "_s">;
559defm "" : ExtractLane<I8x16, 22, "_u">;
560defm "" : ExtractLane<I16x8, 24, "_s">;
561defm "" : ExtractLane<I16x8, 25, "_u">;
562defm "" : ExtractLane<I32x4, 27>;
563defm "" : ExtractLane<I64x2, 29>;
564defm "" : ExtractLane<F32x4, 31>;
565defm "" : ExtractLane<F64x2, 33>;
566
567def : Pat<(vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)),
568          (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
569def : Pat<(vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)),
570          (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
571def : Pat<(vector_extract (v4i32 V128:$vec), (i32 LaneIdx4:$idx)),
572          (EXTRACT_LANE_I32x4 $vec, imm:$idx)>;
573def : Pat<(vector_extract (v4f32 V128:$vec), (i32 LaneIdx4:$idx)),
574          (EXTRACT_LANE_F32x4 $vec, imm:$idx)>;
575def : Pat<(vector_extract (v2i64 V128:$vec), (i32 LaneIdx2:$idx)),
576          (EXTRACT_LANE_I64x2 $vec, imm:$idx)>;
577def : Pat<(vector_extract (v2f64 V128:$vec), (i32 LaneIdx2:$idx)),
578          (EXTRACT_LANE_F64x2 $vec, imm:$idx)>;
579
580def : Pat<
581  (sext_inreg (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), i8),
582  (EXTRACT_LANE_I8x16_s $vec, imm:$idx)>;
583def : Pat<
584  (and (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx)), (i32 0xff)),
585  (EXTRACT_LANE_I8x16_u $vec, imm:$idx)>;
586def : Pat<
587  (sext_inreg (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), i16),
588  (EXTRACT_LANE_I16x8_s $vec, imm:$idx)>;
589def : Pat<
590  (and (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx)), (i32 0xffff)),
591  (EXTRACT_LANE_I16x8_u $vec, imm:$idx)>;
592
593// Replace lane value: replace_lane
594multiclass ReplaceLane<Vec vec, bits<32> simdop> {
595  defm REPLACE_LANE_#vec :
596    SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, vec.lane_rc:$x),
597           (outs), (ins vec_i8imm_op:$idx),
598           [(set V128:$dst, (vector_insert
599             (vec.vt V128:$vec),
600             (vec.lane_vt vec.lane_rc:$x),
601             (i32 vec.lane_idx:$idx)))],
602           vec.prefix#".replace_lane\t$dst, $vec, $idx, $x",
603           vec.prefix#".replace_lane\t$idx", simdop>;
604}
605
606defm "" : ReplaceLane<I8x16, 23>;
607defm "" : ReplaceLane<I16x8, 26>;
608defm "" : ReplaceLane<I32x4, 28>;
609defm "" : ReplaceLane<I64x2, 30>;
610defm "" : ReplaceLane<F32x4, 32>;
611defm "" : ReplaceLane<F64x2, 34>;
612
613// Lower undef lane indices to zero
614def : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
615          (REPLACE_LANE_I8x16 $vec, 0, $x)>;
616def : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
617          (REPLACE_LANE_I16x8 $vec, 0, $x)>;
618def : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
619          (REPLACE_LANE_I32x4 $vec, 0, $x)>;
620def : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
621          (REPLACE_LANE_I64x2 $vec, 0, $x)>;
622def : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
623          (REPLACE_LANE_F32x4 $vec, 0, $x)>;
624def : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
625          (REPLACE_LANE_F64x2 $vec, 0, $x)>;
626
627//===----------------------------------------------------------------------===//
628// Comparisons
629//===----------------------------------------------------------------------===//
630
631multiclass SIMDCondition<Vec vec, string name, CondCode cond, bits<32> simdop> {
632  defm _#vec :
633    SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
634           [(set (vec.int_vt V128:$dst),
635             (setcc (vec.vt V128:$lhs), (vec.vt V128:$rhs), cond))],
636           vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
637           vec.prefix#"."#name, simdop>;
638}
639
640multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
641  defm "" : SIMDCondition<I8x16, name, cond, baseInst>;
642  defm "" : SIMDCondition<I16x8, name, cond, !add(baseInst, 10)>;
643  defm "" : SIMDCondition<I32x4, name, cond, !add(baseInst, 20)>;
644}
645
646multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
647  defm "" : SIMDCondition<F32x4, name, cond, baseInst>;
648  defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>;
649}
650
651// Equality: eq
652let isCommutable = 1 in {
653defm EQ : SIMDConditionInt<"eq", SETEQ, 35>;
654defm EQ : SIMDConditionFP<"eq", SETOEQ, 65>;
655} // isCommutable = 1
656
657// Non-equality: ne
658let isCommutable = 1 in {
659defm NE : SIMDConditionInt<"ne", SETNE, 36>;
660defm NE : SIMDConditionFP<"ne", SETUNE, 66>;
661} // isCommutable = 1
662
663// Less than: lt_s / lt_u / lt
664defm LT_S : SIMDConditionInt<"lt_s", SETLT, 37>;
665defm LT_U : SIMDConditionInt<"lt_u", SETULT, 38>;
666defm LT : SIMDConditionFP<"lt", SETOLT, 67>;
667
668// Greater than: gt_s / gt_u / gt
669defm GT_S : SIMDConditionInt<"gt_s", SETGT, 39>;
670defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 40>;
671defm GT : SIMDConditionFP<"gt", SETOGT, 68>;
672
673// Less than or equal: le_s / le_u / le
674defm LE_S : SIMDConditionInt<"le_s", SETLE, 41>;
675defm LE_U : SIMDConditionInt<"le_u", SETULE, 42>;
676defm LE : SIMDConditionFP<"le", SETOLE, 69>;
677
678// Greater than or equal: ge_s / ge_u / ge
679defm GE_S : SIMDConditionInt<"ge_s", SETGE, 43>;
680defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 44>;
681defm GE : SIMDConditionFP<"ge", SETOGE, 70>;
682
683// Lower float comparisons that don't care about NaN to standard WebAssembly
684// float comparisons. These instructions are generated with nnan and in the
685// target-independent expansion of unordered comparisons and ordered ne.
686foreach nodes = [[seteq, EQ_F32x4], [setne, NE_F32x4], [setlt, LT_F32x4],
687                 [setgt, GT_F32x4], [setle, LE_F32x4], [setge, GE_F32x4]] in
688def : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
689          (nodes[1] $lhs, $rhs)>;
690
691foreach nodes = [[seteq, EQ_F64x2], [setne, NE_F64x2], [setlt, LT_F64x2],
692                 [setgt, GT_F64x2], [setle, LE_F64x2], [setge, GE_F64x2]] in
693def : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
694          (nodes[1] $lhs, $rhs)>;
695
696// Prototype i64x2.eq
697defm EQ_v2i64 :
698  SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
699         [(set (v2i64 V128:$dst),
700           (int_wasm_eq (v2i64 V128:$lhs), (v2i64 V128:$rhs)))],
701         "i64x2.eq\t$dst, $lhs, $rhs", "i64x2.eq", 192>;
702
703
704//===----------------------------------------------------------------------===//
705// Bitwise operations
706//===----------------------------------------------------------------------===//
707
708multiclass SIMDBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
709  defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
710                      (outs), (ins),
711                      [(set (vec.vt V128:$dst),
712                        (node (vec.vt V128:$lhs), (vec.vt V128:$rhs)))],
713                      vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
714                      vec.prefix#"."#name, simdop>;
715}
716
717multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop, bit commutable = false> {
718  let isCommutable = commutable in
719  defm "" : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
720                   (outs), (ins), [],
721                   "v128."#name#"\t$dst, $lhs, $rhs", "v128."#name, simdop>;
722  foreach vec = IntVecs in
723  def : Pat<(node (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
724            (!cast<NI>(NAME) $lhs, $rhs)>;
725}
726
727multiclass SIMDUnary<Vec vec, SDNode node, string name, bits<32> simdop> {
728  defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins),
729                      [(set (vec.vt V128:$dst),
730                        (vec.vt (node (vec.vt V128:$v))))],
731                      vec.prefix#"."#name#"\t$dst, $v",
732                      vec.prefix#"."#name, simdop>;
733}
734
735// Bitwise logic: v128.not
736defm NOT : SIMD_I<(outs V128:$dst), (ins V128:$v), (outs), (ins), [],
737                  "v128.not\t$dst, $v", "v128.not", 77>;
738foreach vec = IntVecs in
739def : Pat<(vnot (vec.vt V128:$v)), (NOT $v)>;
740
741// Bitwise logic: v128.and / v128.or / v128.xor
742defm AND : SIMDBitwise<and, "and", 78, true>;
743defm OR : SIMDBitwise<or, "or", 80, true>;
744defm XOR : SIMDBitwise<xor, "xor", 81, true>;
745
746// Bitwise logic: v128.andnot
747def andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>;
748defm ANDNOT : SIMDBitwise<andnot, "andnot", 79>;
749
750// Bitwise select: v128.bitselect
751defm BITSELECT :
752  SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [],
753         "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>;
754
755foreach vec = AllVecs in
756def : Pat<(vec.vt (int_wasm_bitselect
757            (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
758          (BITSELECT $v1, $v2, $c)>;
759
760// Bitselect is equivalent to (c & v1) | (~c & v2)
761foreach vec = IntVecs in
762def : Pat<(vec.vt (or (and (vec.vt V128:$c), (vec.vt V128:$v1)),
763            (and (vnot V128:$c), (vec.vt V128:$v2)))),
764          (BITSELECT $v1, $v2, $c)>;
765
766// Also implement vselect in terms of bitselect
767foreach vec = AllVecs in
768def : Pat<(vec.vt (vselect
769            (vec.int_vt V128:$c), (vec.vt V128:$v1), (vec.vt V128:$v2))),
770          (BITSELECT $v1, $v2, $c)>;
771
772// MVP select on v128 values
773defm SELECT_V128 :
774  I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs, I32:$cond), (outs), (ins), [],
775    "v128.select\t$dst, $lhs, $rhs, $cond", "v128.select", 0x1b>;
776
777foreach vec = AllVecs in {
778def : Pat<(select I32:$cond, (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
779          (SELECT_V128 $lhs, $rhs, $cond)>;
780
781// ISD::SELECT requires its operand to conform to getBooleanContents, but
782// WebAssembly's select interprets any non-zero value as true, so we can fold
783// a setne with 0 into a select.
784def : Pat<(select
785            (i32 (setne I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
786          (SELECT_V128 $lhs, $rhs, $cond)>;
787
788// And again, this time with seteq instead of setne and the arms reversed.
789def : Pat<(select
790            (i32 (seteq I32:$cond, 0)), (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
791          (SELECT_V128 $rhs, $lhs, $cond)>;
792} // foreach vec
793
794// Sign select
795multiclass SIMDSignSelect<Vec vec, bits<32> simdop> {
796  defm SIGNSELECT_#vec :
797    SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
798           [(set (vec.vt V128:$dst),
799             (vec.vt (int_wasm_signselect
800               (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))))],
801           vec.prefix#".signselect\t$dst, $v1, $v2, $c",
802           vec.prefix#".signselect", simdop>;
803}
804
805defm : SIMDSignSelect<I8x16, 125>;
806defm : SIMDSignSelect<I16x8, 126>;
807defm : SIMDSignSelect<I32x4, 127>;
808defm : SIMDSignSelect<I64x2, 148>;
809
810//===----------------------------------------------------------------------===//
811// Integer unary arithmetic
812//===----------------------------------------------------------------------===//
813
814multiclass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
815  defm "" : SIMDUnary<I8x16, node, name, baseInst>;
816  defm "" : SIMDUnary<I16x8, node, name, !add(baseInst, 32)>;
817  defm "" : SIMDUnary<I32x4, node, name, !add(baseInst, 64)>;
818  defm "" : SIMDUnary<I64x2, node, name, !add(baseInst, 96)>;
819}
820
821multiclass SIMDReduceVec<Vec vec, SDNode op, string name, bits<32> simdop> {
822  defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
823                      [(set I32:$dst, (i32 (op (vec.vt V128:$vec))))],
824                      vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name,
825                      simdop>;
826}
827
828multiclass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
829  defm "" : SIMDReduceVec<I8x16, op, name, baseInst>;
830  defm "" : SIMDReduceVec<I16x8, op, name, !add(baseInst, 32)>;
831  defm "" : SIMDReduceVec<I32x4, op, name, !add(baseInst, 64)>;
832  defm "" : SIMDReduceVec<I64x2, op, name, !add(baseInst, 96)>;
833}
834
835// Integer vector negation
836def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, $in)>;
837
838// Integer absolute value: abs
839defm ABS : SIMDUnaryInt<abs, "abs", 96>;
840
841// Integer negation: neg
842defm NEG : SIMDUnaryInt<ivneg, "neg", 97>;
843
844// Any lane true: any_true
845defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>;
846
847// All lanes true: all_true
848defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>;
849
850// Population count: popcnt
851defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 124>;
852
853// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
854// can be folded out
855foreach reduction =
856  [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
857foreach vec = IntVecs in {
858defvar intrinsic = !cast<Intrinsic>(reduction[0]);
859defvar inst = !cast<NI>(reduction[1]#"_"#vec);
860def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
861def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
862def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
863}
864
865multiclass SIMDBitmask<Vec vec, bits<32> simdop> {
866  defm _#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
867                      [(set I32:$dst,
868                         (i32 (int_wasm_bitmask (vec.vt V128:$vec))))],
869                      vec.prefix#".bitmask\t$dst, $vec", vec.prefix#".bitmask",
870                      simdop>;
871}
872
873defm BITMASK : SIMDBitmask<I8x16, 100>;
874defm BITMASK : SIMDBitmask<I16x8, 132>;
875defm BITMASK : SIMDBitmask<I32x4, 164>;
876defm BITMASK : SIMDBitmask<I64x2, 196>;
877
878//===----------------------------------------------------------------------===//
879// Bit shifts
880//===----------------------------------------------------------------------===//
881
882multiclass SIMDShift<Vec vec, SDNode node, string name, bits<32> simdop> {
883  defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x), (outs), (ins),
884                      [(set (vec.vt V128:$dst), (node V128:$vec, I32:$x))],
885                      vec.prefix#"."#name#"\t$dst, $vec, $x",
886                      vec.prefix#"."#name, simdop>;
887}
888
889multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
890  defm "" : SIMDShift<I8x16, node, name, baseInst>;
891  defm "" : SIMDShift<I16x8, node, name, !add(baseInst, 32)>;
892  defm "" : SIMDShift<I32x4, node, name, !add(baseInst, 64)>;
893  defm "" : SIMDShift<I64x2, node, name, !add(baseInst, 96)>;
894}
895
896// WebAssembly SIMD shifts are nonstandard in that the shift amount is
897// an i32 rather than a vector, so they need custom nodes.
898def wasm_shift_t :
899  SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]>;
900def wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
901def wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
902def wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
903
904// Left shift by scalar: shl
905defm SHL : SIMDShiftInt<wasm_shl, "shl", 107>;
906
907// Right shift by scalar: shr_s / shr_u
908defm SHR_S : SIMDShiftInt<wasm_shr_s, "shr_s", 108>;
909defm SHR_U : SIMDShiftInt<wasm_shr_u, "shr_u", 109>;
910
911//===----------------------------------------------------------------------===//
912// Integer binary arithmetic
913//===----------------------------------------------------------------------===//
914
915multiclass SIMDBinaryIntNoI8x16<SDNode node, string name, bits<32> baseInst> {
916  defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
917  defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
918  defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
919}
920
921multiclass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
922  defm "" : SIMDBinary<I8x16, node, name, baseInst>;
923  defm "" : SIMDBinary<I16x8, node, name, !add(baseInst, 32)>;
924}
925
926multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
927  defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
928  defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
929}
930
931multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
932  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
933  defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
934}
935
936// Integer addition: add / add_saturate_s / add_saturate_u
937let isCommutable = 1 in {
938defm ADD : SIMDBinaryInt<add, "add", 110>;
939defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>;
940defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>;
941} // isCommutable = 1
942
943// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
944defm SUB : SIMDBinaryInt<sub, "sub", 113>;
945defm SUB_SAT_S :
946  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>;
947defm SUB_SAT_U :
948  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>;
949
950// Integer multiplication: mul
951let isCommutable = 1 in
952defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>;
953
954// Integer min_s / min_u / max_s / max_u
955let isCommutable = 1 in {
956defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>;
957defm MIN_U : SIMDBinaryIntNoI64x2<umin, "min_u", 119>;
958defm MAX_S : SIMDBinaryIntNoI64x2<smax, "max_s", 120>;
959defm MAX_U : SIMDBinaryIntNoI64x2<umax, "max_u", 121>;
960} // isCommutable = 1
961
962// Integer unsigned rounding average: avgr_u
963let isCommutable = 1 in {
964defm AVGR_U : SIMDBinary<I8x16, int_wasm_avgr_unsigned, "avgr_u", 123>;
965defm AVGR_U : SIMDBinary<I16x8, int_wasm_avgr_unsigned, "avgr_u", 155>;
966}
967
968def add_nuw : PatFrag<(ops node:$lhs, node:$rhs), (add $lhs, $rhs),
969                      "return N->getFlags().hasNoUnsignedWrap();">;
970
971foreach vec = [I8x16, I16x8] in {
972defvar inst = !cast<NI>("AVGR_U_"#vec);
973def : Pat<(wasm_shr_u
974            (add_nuw
975              (add_nuw (vec.vt V128:$lhs), (vec.vt V128:$rhs)),
976              (vec.splat (i32 1))),
977            (i32 1)),
978          (inst $lhs, $rhs)>;
979}
980
981// Widening dot product: i32x4.dot_i16x8_s
982let isCommutable = 1 in
983defm DOT : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
984                  [(set V128:$dst, (int_wasm_dot V128:$lhs, V128:$rhs))],
985                  "i32x4.dot_i16x8_s\t$dst, $lhs, $rhs", "i32x4.dot_i16x8_s",
986                  186>;
987
988// Extending multiplication: extmul_{low,high}_P, extmul_high
989multiclass SIMDExtBinary<Vec vec, SDNode node, string name, bits<32> simdop> {
990  defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
991                      (outs), (ins),
992                      [(set (vec.vt V128:$dst), (node
993                         (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
994                      vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
995                      vec.prefix#"."#name, simdop>;
996}
997
998defm EXTMUL_LOW_S :
999  SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 154>;
1000defm EXTMUL_HIGH_S :
1001  SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 157>;
1002defm EXTMUL_LOW_U :
1003  SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 158>;
1004defm EXTMUL_HIGH_U :
1005  SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 159>;
1006
1007defm EXTMUL_LOW_S :
1008  SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 187>;
1009defm EXTMUL_HIGH_S :
1010  SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 189>;
1011defm EXTMUL_LOW_U :
1012  SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 190>;
1013defm EXTMUL_HIGH_U :
1014  SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 191>;
1015
1016defm EXTMUL_LOW_S :
1017  SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 210>;
1018defm EXTMUL_HIGH_S :
1019  SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 211>;
1020defm EXTMUL_LOW_U :
1021  SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 214>;
1022defm EXTMUL_HIGH_U :
1023  SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 215>;
1024
1025//===----------------------------------------------------------------------===//
1026// Floating-point unary arithmetic
1027//===----------------------------------------------------------------------===//
1028
1029multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
1030  defm "" : SIMDUnary<F32x4, node, name, baseInst>;
1031  defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>;
1032}
1033
1034// Absolute value: abs
1035defm ABS : SIMDUnaryFP<fabs, "abs", 224>;
1036
1037// Negation: neg
1038defm NEG : SIMDUnaryFP<fneg, "neg", 225>;
1039
1040// Square root: sqrt
1041defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>;
1042
1043// Rounding: ceil, floor, trunc, nearest
1044defm CEIL : SIMDUnary<F32x4, int_wasm_ceil, "ceil", 216>;
1045defm FLOOR : SIMDUnary<F32x4, int_wasm_floor, "floor", 217>;
1046defm TRUNC: SIMDUnary<F32x4, int_wasm_trunc, "trunc", 218>;
1047defm NEAREST: SIMDUnary<F32x4, int_wasm_nearest, "nearest", 219>;
1048defm CEIL : SIMDUnary<F64x2, int_wasm_ceil, "ceil", 220>;
1049defm FLOOR : SIMDUnary<F64x2, int_wasm_floor, "floor", 221>;
1050defm TRUNC: SIMDUnary<F64x2, int_wasm_trunc, "trunc", 222>;
1051defm NEAREST: SIMDUnary<F64x2, int_wasm_nearest, "nearest", 223>;
1052
1053//===----------------------------------------------------------------------===//
1054// Floating-point binary arithmetic
1055//===----------------------------------------------------------------------===//
1056
1057multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
1058  defm "" : SIMDBinary<F32x4, node, name, baseInst>;
1059  defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>;
1060}
1061
1062// Addition: add
1063let isCommutable = 1 in
1064defm ADD : SIMDBinaryFP<fadd, "add", 228>;
1065
1066// Subtraction: sub
1067defm SUB : SIMDBinaryFP<fsub, "sub", 229>;
1068
1069// Multiplication: mul
1070let isCommutable = 1 in
1071defm MUL : SIMDBinaryFP<fmul, "mul", 230>;
1072
1073// Division: div
1074defm DIV : SIMDBinaryFP<fdiv, "div", 231>;
1075
1076// NaN-propagating minimum: min
1077defm MIN : SIMDBinaryFP<fminimum, "min", 232>;
1078
1079// NaN-propagating maximum: max
1080defm MAX : SIMDBinaryFP<fmaximum, "max", 233>;
1081
1082// Pseudo-minimum: pmin
1083defm PMIN : SIMDBinaryFP<int_wasm_pmin, "pmin", 234>;
1084
1085// Pseudo-maximum: pmax
1086defm PMAX : SIMDBinaryFP<int_wasm_pmax, "pmax", 235>;
1087
1088//===----------------------------------------------------------------------===//
1089// Conversions
1090//===----------------------------------------------------------------------===//
1091
1092multiclass SIMDConvert<Vec vec, Vec arg, SDNode op, string name,
1093                       bits<32> simdop> {
1094  defm op#_#vec :
1095    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
1096           [(set (vec.vt V128:$dst), (vec.vt (op (arg.vt V128:$vec))))],
1097           vec.prefix#"."#name#"\t$dst, $vec", vec.prefix#"."#name, simdop>;
1098}
1099
1100// Floating point to integer with saturation: trunc_sat
1101defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>;
1102defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>;
1103
1104// Integer to floating point: convert
1105defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
1106defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
1107
1108// Lower llvm.wasm.trunc.saturate.* to saturating instructions
1109def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
1110          (fp_to_sint_I32x4 $src)>;
1111def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
1112          (fp_to_uint_I32x4 $src)>;
1113
1114// Widening operations
1115def widen_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
1116def widen_low_s : SDNode<"WebAssemblyISD::WIDEN_LOW_S", widen_t>;
1117def widen_high_s : SDNode<"WebAssemblyISD::WIDEN_HIGH_S", widen_t>;
1118def widen_low_u : SDNode<"WebAssemblyISD::WIDEN_LOW_U", widen_t>;
1119def widen_high_u : SDNode<"WebAssemblyISD::WIDEN_HIGH_U", widen_t>;
1120
1121// TODO: refactor this to be uniform for i64x2 if the numbering is not changed.
1122multiclass SIMDWiden<Vec vec, bits<32> baseInst> {
1123  defm "" : SIMDConvert<vec, vec.split, widen_low_s,
1124                        "widen_low_"#vec.split.prefix#"_s", baseInst>;
1125  defm "" : SIMDConvert<vec, vec.split, widen_high_s,
1126                        "widen_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
1127  defm "" : SIMDConvert<vec, vec.split, widen_low_u,
1128                        "widen_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
1129  defm "" : SIMDConvert<vec, vec.split, widen_high_u,
1130                        "widen_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
1131}
1132
1133defm "" : SIMDWiden<I16x8, 135>;
1134defm "" : SIMDWiden<I32x4, 167>;
1135
1136defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_signed,
1137                      "widen_low_i32x4_s", 199>;
1138defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_signed,
1139                      "widen_high_i32x4_s", 200>;
1140defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_unsigned,
1141                      "widen_low_i32x4_u", 201>;
1142defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_unsigned,
1143                      "widen_high_i32x4_u", 202>;
1144
1145// Narrowing operations
1146multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
1147  defvar name = vec.split.prefix#".narrow_"#vec.prefix;
1148  defm NARROW_S_#vec.split :
1149    SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
1150           [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
1151             (vec.vt V128:$low), (vec.vt V128:$high))))],
1152           name#"_s\t$dst, $low, $high", name#"_s", baseInst>;
1153  defm NARROW_U_#vec.split :
1154    SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
1155           [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_unsigned
1156             (vec.vt V128:$low), (vec.vt V128:$high))))],
1157           name#"_u\t$dst, $low, $high", name#"_u", !add(baseInst, 1)>;
1158}
1159
1160defm "" : SIMDNarrow<I16x8, 101>;
1161defm "" : SIMDNarrow<I32x4, 133>;
1162
1163// Use narrowing operations for truncating stores. Since the narrowing
1164// operations are saturating instead of truncating, we need to mask
1165// the stored values first.
1166// TODO: Use consts instead of splats
1167def store_v8i8_trunc_v8i16 :
1168  OutPatFrag<(ops node:$val),
1169             (EXTRACT_LANE_I64x2
1170               (NARROW_U_I8x16
1171                 (AND (SPLAT_I32x4 (CONST_I32 0x00ff00ff)), node:$val),
1172                 $val), // Unused input
1173               0)>;
1174
1175def store_v4i16_trunc_v4i32 :
1176  OutPatFrag<(ops node:$val),
1177             (EXTRACT_LANE_I64x2
1178               (NARROW_U_I16x8
1179                 (AND (SPLAT_I32x4 (CONST_I32 0x0000ffff)), node:$val),
1180                 $val), // Unused input
1181               0)>;
1182
1183// Store patterns adapted from WebAssemblyInstrMemory.td
1184multiclass NarrowingStorePatNoOffset<Vec vec, OutPatFrag out> {
1185  defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
1186  def : Pat<(node vec.vt:$val, I32:$addr),
1187            (STORE_I64_A32 0, 0, $addr, (out $val))>,
1188        Requires<[HasAddr32]>;
1189  def : Pat<(node vec.vt:$val, I64:$addr),
1190            (STORE_I64_A64 0, 0, $addr, (out $val))>,
1191        Requires<[HasAddr64]>;
1192}
1193
1194defm : NarrowingStorePatNoOffset<I16x8, store_v8i8_trunc_v8i16>;
1195defm : NarrowingStorePatNoOffset<I32x4, store_v4i16_trunc_v4i32>;
1196
1197multiclass NarrowingStorePatImmOff<Vec vec, PatFrag operand, OutPatFrag out> {
1198  defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
1199  def : Pat<(node vec.vt:$val, (operand I32:$addr, imm:$off)),
1200            (STORE_I64_A32 0, imm:$off, $addr, (out $val))>,
1201        Requires<[HasAddr32]>;
1202  def : Pat<(node vec.vt:$val, (operand I64:$addr, imm:$off)),
1203            (STORE_I64_A64 0, imm:$off, $addr, (out $val))>,
1204        Requires<[HasAddr64]>;
1205}
1206
1207defm : NarrowingStorePatImmOff<I16x8, regPlusImm, store_v8i8_trunc_v8i16>;
1208defm : NarrowingStorePatImmOff<I32x4, regPlusImm, store_v4i16_trunc_v4i32>;
1209defm : NarrowingStorePatImmOff<I16x8, or_is_add, store_v8i8_trunc_v8i16>;
1210defm : NarrowingStorePatImmOff<I32x4, or_is_add, store_v4i16_trunc_v4i32>;
1211
1212multiclass NarrowingStorePatOffsetOnly<Vec vec, OutPatFrag out> {
1213  defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
1214  def : Pat<(node vec.vt:$val, imm:$off),
1215            (STORE_I64_A32 0, imm:$off, (CONST_I32 0), (out $val))>,
1216        Requires<[HasAddr32]>;
1217  def : Pat<(node vec.vt:$val, imm:$off),
1218            (STORE_I64_A64 0, imm:$off, (CONST_I64 0), (out $val))>,
1219        Requires<[HasAddr64]>;
1220}
1221
1222defm : NarrowingStorePatOffsetOnly<I16x8, store_v8i8_trunc_v8i16>;
1223defm : NarrowingStorePatOffsetOnly<I32x4, store_v4i16_trunc_v4i32>;
1224
1225multiclass NarrowingStorePatGlobalAddrOffOnly<Vec vec, OutPatFrag out> {
1226  defvar node = !cast<PatFrag>("truncstorevi"#vec.split.lane_bits);
1227  def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)),
1228            (STORE_I64_A32 0, tglobaladdr:$off, (CONST_I32 0), (out $val))>,
1229        Requires<[IsNotPIC, HasAddr32]>;
1230  def : Pat<(node vec.vt:$val, (WebAssemblywrapper tglobaladdr:$off)),
1231            (STORE_I64_A64  0, tglobaladdr:$off, (CONST_I64 0), (out $val))>,
1232        Requires<[IsNotPIC, HasAddr64]>;
1233}
1234
1235defm : NarrowingStorePatGlobalAddrOffOnly<I16x8, store_v8i8_trunc_v8i16>;
1236defm : NarrowingStorePatGlobalAddrOffOnly<I32x4, store_v4i16_trunc_v4i32>;
1237
1238// Bitcasts are nops
1239// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
1240foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
1241foreach t2 = !foldl(
1242  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
1243  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
1244    acc, !listconcat(acc, [cur])
1245  )
1246) in
1247def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
1248
1249// Extended pairwise addition
1250defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed,
1251                      "extadd_pairwise_i8x16_s", 0xc2>;
1252defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned,
1253                      "extadd_pairwise_i8x16_u", 0xc3>;
1254defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed,
1255                      "extadd_pairwise_i16x8_s", 0xa5>;
1256defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
1257                      "extadd_pairwise_i16x8_u", 0xa6>;
1258
1259
1260// Prototype f64x2 conversions
1261defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
1262                      "convert_low_i32x4_s", 0x53>;
1263defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_unsigned,
1264                      "convert_low_i32x4_u", 0x54>;
1265defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_signed,
1266                      "trunc_sat_zero_f64x2_s", 0x55>;
1267defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_unsigned,
1268                      "trunc_sat_zero_f64x2_u", 0x56>;
1269defm "" : SIMDConvert<F32x4, F64x2, int_wasm_demote_zero,
1270                      "demote_zero_f64x2", 0x57>;
1271defm "" : SIMDConvert<F64x2, F32x4, int_wasm_promote_low,
1272                      "promote_low_f32x4", 0x69>;
1273
1274//===----------------------------------------------------------------------===//
1275// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
1276//===----------------------------------------------------------------------===//
1277
1278multiclass SIMDQFM<Vec vec, bits<32> simdopA, bits<32> simdopS> {
1279  defm QFMA_#vec :
1280    SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
1281           (outs), (ins),
1282           [(set (vec.vt V128:$dst), (int_wasm_qfma
1283              (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1284           vec.prefix#".qfma\t$dst, $a, $b, $c", vec.prefix#".qfma", simdopA>;
1285  defm QFMS_#vec :
1286    SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
1287           (outs), (ins),
1288           [(set (vec.vt V128:$dst), (int_wasm_qfms
1289              (vec.vt V128:$a), (vec.vt V128:$b), (vec.vt V128:$c)))],
1290           vec.prefix#".qfms\t$dst, $a, $b, $c", vec.prefix#".qfms", simdopS>;
1291}
1292
1293defm "" : SIMDQFM<F32x4, 180, 212>;
1294defm "" : SIMDQFM<F64x2, 254, 255>;
1295
1296//===----------------------------------------------------------------------===//
1297// Saturating Rounding Q-Format Multiplication
1298//===----------------------------------------------------------------------===//
1299
1300defm Q15MULR_SAT_S :
1301  SIMDBinary<I16x8, int_wasm_q15mulr_saturate_signed, "q15mulr_sat_s", 156>;
1302
1303//===----------------------------------------------------------------------===//
1304// Experimental prefetch instructions: prefetch.t, prefetch.nt
1305//===----------------------------------------------------------------------===//
1306
1307let mayLoad = true, UseNamedOperandTable = true in {
1308defm PREFETCH_T_A32 :
1309  SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
1310         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
1311         "prefetch.t\t${off}(${addr})$p2align",
1312         "prefetch.t\t$off$p2align", 0xc5>;
1313defm PREFETCH_T_A64 :
1314  SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
1315         (outs), (ins P2Align:$p2align, offset64_op:$off), [],
1316         "prefetch.t\t${off}(${addr})$p2align",
1317         "prefetch.t\t$off$p2align", 0xc5>;
1318defm PREFETCH_NT_A32 :
1319  SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
1320         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
1321         "prefetch.nt\t${off}(${addr})$p2align",
1322         "prefetch.nt\t$off$p2align", 0xc6>;
1323defm PREFETCH_NT_A64 :
1324  SIMD_I<(outs), (ins P2Align:$p2align, offset64_op:$off, I64:$addr),
1325         (outs), (ins P2Align:$p2align, offset64_op:$off), [],
1326         "prefetch.nt\t${off}(${addr})$p2align",
1327         "prefetch.nt\t$off$p2align", 0xc6>;
1328} // mayLoad, UseNamedOperandTable
1329
1330multiclass PrefetchPatNoOffset<PatFrag kind, string inst> {
1331  def : Pat<(kind I32:$addr), (!cast<NI>(inst # "_A32") 0, 0, $addr)>,
1332        Requires<[HasAddr32]>;
1333  def : Pat<(kind I64:$addr), (!cast<NI>(inst # "_A64") 0, 0, $addr)>,
1334        Requires<[HasAddr64]>;
1335}
1336
1337foreach inst = [["PREFETCH_T", "int_wasm_prefetch_t"],
1338                ["PREFETCH_NT", "int_wasm_prefetch_nt"]] in {
1339defvar node = !cast<Intrinsic>(inst[1]);
1340defm : PrefetchPatNoOffset<node, inst[0]>;
1341}
1342