xref: /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (revision 8bcb0991864975618c09697b1aca10683346d9f0)
10b57cec5SDimitry Andric// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
20b57cec5SDimitry Andric//
30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric//
70b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric///
90b57cec5SDimitry Andric/// \file
100b57cec5SDimitry Andric/// WebAssembly SIMD operand code-gen constructs.
110b57cec5SDimitry Andric///
120b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
130b57cec5SDimitry Andric
140b57cec5SDimitry Andric// Instructions requiring HasSIMD128 and the simd128 prefix byte
150b57cec5SDimitry Andricmulticlass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
160b57cec5SDimitry Andric                  list<dag> pattern_r, string asmstr_r = "",
170b57cec5SDimitry Andric                  string asmstr_s = "", bits<32> simdop = -1> {
180b57cec5SDimitry Andric  defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
190b57cec5SDimitry Andric              !or(0xfd00, !and(0xff, simdop))>,
200b57cec5SDimitry Andric            Requires<[HasSIMD128]>;
210b57cec5SDimitry Andric}
220b57cec5SDimitry Andric
230b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v16i8>;
240b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v8i16>;
250b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v4i32>;
260b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v2i64>;
270b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v4f32>;
280b57cec5SDimitry Andricdefm "" : ARGUMENT<V128, v2f64>;
290b57cec5SDimitry Andric
300b57cec5SDimitry Andric// Constrained immediate argument types
310b57cec5SDimitry Andricforeach SIZE = [8, 16] in
320b57cec5SDimitry Andricdef ImmI#SIZE : ImmLeaf<i32,
330b57cec5SDimitry Andric  "return -(1 << ("#SIZE#" - 1)) <= Imm && Imm < (1 << ("#SIZE#" - 1));"
340b57cec5SDimitry Andric>;
350b57cec5SDimitry Andricforeach SIZE = [2, 4, 8, 16, 32] in
360b57cec5SDimitry Andricdef LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
370b57cec5SDimitry Andric
380b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
390b57cec5SDimitry Andric// Load and store
400b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
410b57cec5SDimitry Andric
420b57cec5SDimitry Andric// Load: v128.load
430b57cec5SDimitry Andriclet mayLoad = 1, UseNamedOperandTable = 1 in
44*8bcb0991SDimitry Andricdefm LOAD_V128 :
450b57cec5SDimitry Andric  SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
460b57cec5SDimitry Andric         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
470b57cec5SDimitry Andric         "v128.load\t$dst, ${off}(${addr})$p2align",
480b57cec5SDimitry Andric         "v128.load\t$off$p2align", 0>;
490b57cec5SDimitry Andric
500b57cec5SDimitry Andric// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
51*8bcb0991SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
52*8bcb0991SDimitry Andricdef : LoadPatNoOffset<vec_t, load, LOAD_V128>;
53*8bcb0991SDimitry Andricdef : LoadPatImmOff<vec_t, load, regPlusImm, LOAD_V128>;
54*8bcb0991SDimitry Andricdef : LoadPatImmOff<vec_t, load, or_is_add, LOAD_V128>;
55*8bcb0991SDimitry Andricdef : LoadPatOffsetOnly<vec_t, load, LOAD_V128>;
56*8bcb0991SDimitry Andricdef : LoadPatGlobalAddrOffOnly<vec_t, load, LOAD_V128>;
570b57cec5SDimitry Andric}
580b57cec5SDimitry Andric
59*8bcb0991SDimitry Andric// vNxM.load_splat
60*8bcb0991SDimitry Andricmulticlass SIMDLoadSplat<string vec, bits<32> simdop> {
61*8bcb0991SDimitry Andric  let mayLoad = 1, UseNamedOperandTable = 1,
62*8bcb0991SDimitry Andric      Predicates = [HasUnimplementedSIMD128] in
63*8bcb0991SDimitry Andric  defm LOAD_SPLAT_#vec :
64*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
65*8bcb0991SDimitry Andric           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
66*8bcb0991SDimitry Andric           vec#".load_splat\t$dst, ${off}(${addr})$p2align",
67*8bcb0991SDimitry Andric           vec#".load_splat\t$off$p2align", simdop>;
68*8bcb0991SDimitry Andric}
69*8bcb0991SDimitry Andric
70*8bcb0991SDimitry Andricdefm "" : SIMDLoadSplat<"v8x16", 194>;
71*8bcb0991SDimitry Andricdefm "" : SIMDLoadSplat<"v16x8", 195>;
72*8bcb0991SDimitry Andricdefm "" : SIMDLoadSplat<"v32x4", 196>;
73*8bcb0991SDimitry Andricdefm "" : SIMDLoadSplat<"v64x2", 197>;
74*8bcb0991SDimitry Andric
75*8bcb0991SDimitry Andricdef wasm_load_splat_t : SDTypeProfile<1, 1, []>;
76*8bcb0991SDimitry Andricdef wasm_load_splat : SDNode<"WebAssemblyISD::LOAD_SPLAT", wasm_load_splat_t>;
77*8bcb0991SDimitry Andric
78*8bcb0991SDimitry Andricforeach args = [["v16i8", "i32", "extloadi8"], ["v8i16", "i32", "extloadi16"],
79*8bcb0991SDimitry Andric                ["v4i32", "i32", "load"], ["v2i64", "i64", "load"],
80*8bcb0991SDimitry Andric                ["v4f32", "f32", "load"], ["v2f64", "f64", "load"]] in
81*8bcb0991SDimitry Andricdef load_splat_#args[0] :
82*8bcb0991SDimitry Andric  PatFrag<(ops node:$addr), (wasm_load_splat
83*8bcb0991SDimitry Andric            (!cast<ValueType>(args[1]) (!cast<PatFrag>(args[2]) node:$addr)))>;
84*8bcb0991SDimitry Andric
85*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
86*8bcb0991SDimitry Andricforeach args = [["v16i8", "v8x16"], ["v8i16", "v16x8"], ["v4i32", "v32x4"],
87*8bcb0991SDimitry Andric                ["v2i64", "v64x2"], ["v4f32", "v32x4"], ["v2f64", "v64x2"]] in {
88*8bcb0991SDimitry Andricdef : LoadPatNoOffset<!cast<ValueType>(args[0]),
89*8bcb0991SDimitry Andric                      !cast<PatFrag>("load_splat_"#args[0]),
90*8bcb0991SDimitry Andric                      !cast<NI>("LOAD_SPLAT_"#args[1])>;
91*8bcb0991SDimitry Andricdef : LoadPatImmOff<!cast<ValueType>(args[0]),
92*8bcb0991SDimitry Andric                    !cast<PatFrag>("load_splat_"#args[0]),
93*8bcb0991SDimitry Andric                    regPlusImm,
94*8bcb0991SDimitry Andric                    !cast<NI>("LOAD_SPLAT_"#args[1])>;
95*8bcb0991SDimitry Andricdef : LoadPatImmOff<!cast<ValueType>(args[0]),
96*8bcb0991SDimitry Andric                    !cast<PatFrag>("load_splat_"#args[0]),
97*8bcb0991SDimitry Andric                    or_is_add,
98*8bcb0991SDimitry Andric                    !cast<NI>("LOAD_SPLAT_"#args[1])>;
99*8bcb0991SDimitry Andricdef : LoadPatOffsetOnly<!cast<ValueType>(args[0]),
100*8bcb0991SDimitry Andric                        !cast<PatFrag>("load_splat_"#args[0]),
101*8bcb0991SDimitry Andric                        !cast<NI>("LOAD_SPLAT_"#args[1])>;
102*8bcb0991SDimitry Andricdef : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
103*8bcb0991SDimitry Andric                               !cast<PatFrag>("load_splat_"#args[0]),
104*8bcb0991SDimitry Andric                               !cast<NI>("LOAD_SPLAT_"#args[1])>;
105*8bcb0991SDimitry Andric}
106*8bcb0991SDimitry Andric
107*8bcb0991SDimitry Andric// Load and extend
108*8bcb0991SDimitry Andricmulticlass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
109*8bcb0991SDimitry Andric  let mayLoad = 1, UseNamedOperandTable = 1,
110*8bcb0991SDimitry Andric      Predicates = [HasUnimplementedSIMD128] in {
111*8bcb0991SDimitry Andric  defm LOAD_EXTEND_S_#vec_t :
112*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
113*8bcb0991SDimitry Andric           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
114*8bcb0991SDimitry Andric           name#"_s\t$dst, ${off}(${addr})$p2align",
115*8bcb0991SDimitry Andric           name#"_s\t$off$p2align", simdop>;
116*8bcb0991SDimitry Andric  defm LOAD_EXTEND_U_#vec_t :
117*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
118*8bcb0991SDimitry Andric           (outs), (ins P2Align:$p2align, offset32_op:$off), [],
119*8bcb0991SDimitry Andric           name#"_u\t$dst, ${off}(${addr})$p2align",
120*8bcb0991SDimitry Andric           name#"_u\t$off$p2align", !add(simdop, 1)>;
121*8bcb0991SDimitry Andric  }
122*8bcb0991SDimitry Andric}
123*8bcb0991SDimitry Andric
124*8bcb0991SDimitry Andricdefm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 210>;
125*8bcb0991SDimitry Andricdefm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>;
126*8bcb0991SDimitry Andricdefm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 214>;
127*8bcb0991SDimitry Andric
128*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
129*8bcb0991SDimitry Andricforeach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
130*8bcb0991SDimitry Andricforeach exts = [["sextloadv", "_S"],
131*8bcb0991SDimitry Andric                ["zextloadv", "_U"],
132*8bcb0991SDimitry Andric                ["extloadv", "_U"]] in {
133*8bcb0991SDimitry Andricdef : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]),
134*8bcb0991SDimitry Andric                      !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
135*8bcb0991SDimitry Andricdef : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm,
136*8bcb0991SDimitry Andric                    !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
137*8bcb0991SDimitry Andricdef : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add,
138*8bcb0991SDimitry Andric                    !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
139*8bcb0991SDimitry Andricdef : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
140*8bcb0991SDimitry Andric                        !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
141*8bcb0991SDimitry Andricdef : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
142*8bcb0991SDimitry Andric                               !cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
143*8bcb0991SDimitry Andric}
144*8bcb0991SDimitry Andric
145*8bcb0991SDimitry Andric
1460b57cec5SDimitry Andric// Store: v128.store
1470b57cec5SDimitry Andriclet mayStore = 1, UseNamedOperandTable = 1 in
148*8bcb0991SDimitry Andricdefm STORE_V128 :
1490b57cec5SDimitry Andric  SIMD_I<(outs), (ins P2Align:$p2align, offset32_op:$off, I32:$addr, V128:$vec),
1500b57cec5SDimitry Andric         (outs), (ins P2Align:$p2align, offset32_op:$off), [],
1510b57cec5SDimitry Andric         "v128.store\t${off}(${addr})$p2align, $vec",
1520b57cec5SDimitry Andric         "v128.store\t$off$p2align", 1>;
1530b57cec5SDimitry Andric
1540b57cec5SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
1550b57cec5SDimitry Andric// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
156*8bcb0991SDimitry Andricdef : StorePatNoOffset<vec_t, store, STORE_V128>;
157*8bcb0991SDimitry Andricdef : StorePatImmOff<vec_t, store, regPlusImm, STORE_V128>;
158*8bcb0991SDimitry Andricdef : StorePatImmOff<vec_t, store, or_is_add, STORE_V128>;
159*8bcb0991SDimitry Andricdef : StorePatOffsetOnly<vec_t, store, STORE_V128>;
160*8bcb0991SDimitry Andricdef : StorePatGlobalAddrOffOnly<vec_t, store, STORE_V128>;
1610b57cec5SDimitry Andric}
1620b57cec5SDimitry Andric
1630b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
1640b57cec5SDimitry Andric// Constructing SIMD values
1650b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
1660b57cec5SDimitry Andric
1670b57cec5SDimitry Andric// Constant: v128.const
1680b57cec5SDimitry Andricmulticlass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
1690b57cec5SDimitry Andric  let isMoveImm = 1, isReMaterializable = 1,
170*8bcb0991SDimitry Andric      Predicates = [HasUnimplementedSIMD128] in
1710b57cec5SDimitry Andric  defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
1720b57cec5SDimitry Andric                                  [(set V128:$dst, (vec_t pat))],
1730b57cec5SDimitry Andric                                  "v128.const\t$dst, "#args,
1740b57cec5SDimitry Andric                                  "v128.const\t"#args, 2>;
1750b57cec5SDimitry Andric}
1760b57cec5SDimitry Andric
1770b57cec5SDimitry Andricdefm "" : ConstVec<v16i8,
1780b57cec5SDimitry Andric                   (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
1790b57cec5SDimitry Andric                        vec_i8imm_op:$i2, vec_i8imm_op:$i3,
1800b57cec5SDimitry Andric                        vec_i8imm_op:$i4, vec_i8imm_op:$i5,
1810b57cec5SDimitry Andric                        vec_i8imm_op:$i6, vec_i8imm_op:$i7,
1820b57cec5SDimitry Andric                        vec_i8imm_op:$i8, vec_i8imm_op:$i9,
1830b57cec5SDimitry Andric                        vec_i8imm_op:$iA, vec_i8imm_op:$iB,
1840b57cec5SDimitry Andric                        vec_i8imm_op:$iC, vec_i8imm_op:$iD,
1850b57cec5SDimitry Andric                        vec_i8imm_op:$iE, vec_i8imm_op:$iF),
1860b57cec5SDimitry Andric                   (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
1870b57cec5SDimitry Andric                                 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
1880b57cec5SDimitry Andric                                 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
1890b57cec5SDimitry Andric                                 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
1900b57cec5SDimitry Andric                   !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
1910b57cec5SDimitry Andric                              "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
1920b57cec5SDimitry Andricdefm "" : ConstVec<v8i16,
1930b57cec5SDimitry Andric                   (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
1940b57cec5SDimitry Andric                        vec_i16imm_op:$i2, vec_i16imm_op:$i3,
1950b57cec5SDimitry Andric                        vec_i16imm_op:$i4, vec_i16imm_op:$i5,
1960b57cec5SDimitry Andric                        vec_i16imm_op:$i6, vec_i16imm_op:$i7),
1970b57cec5SDimitry Andric                   (build_vector
1980b57cec5SDimitry Andric                     ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
1990b57cec5SDimitry Andric                     ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
2000b57cec5SDimitry Andric                   "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
2010b57cec5SDimitry Andriclet IsCanonical = 1 in
2020b57cec5SDimitry Andricdefm "" : ConstVec<v4i32,
2030b57cec5SDimitry Andric                   (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
2040b57cec5SDimitry Andric                        vec_i32imm_op:$i2, vec_i32imm_op:$i3),
2050b57cec5SDimitry Andric                   (build_vector (i32 imm:$i0), (i32 imm:$i1),
2060b57cec5SDimitry Andric                                 (i32 imm:$i2), (i32 imm:$i3)),
2070b57cec5SDimitry Andric                   "$i0, $i1, $i2, $i3">;
2080b57cec5SDimitry Andricdefm "" : ConstVec<v2i64,
2090b57cec5SDimitry Andric                   (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
2100b57cec5SDimitry Andric                   (build_vector (i64 imm:$i0), (i64 imm:$i1)),
2110b57cec5SDimitry Andric                   "$i0, $i1">;
2120b57cec5SDimitry Andricdefm "" : ConstVec<v4f32,
2130b57cec5SDimitry Andric                   (ins f32imm_op:$i0, f32imm_op:$i1,
2140b57cec5SDimitry Andric                        f32imm_op:$i2, f32imm_op:$i3),
2150b57cec5SDimitry Andric                   (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
2160b57cec5SDimitry Andric                                 (f32 fpimm:$i2), (f32 fpimm:$i3)),
2170b57cec5SDimitry Andric                   "$i0, $i1, $i2, $i3">;
2180b57cec5SDimitry Andricdefm "" : ConstVec<v2f64,
2190b57cec5SDimitry Andric                  (ins f64imm_op:$i0, f64imm_op:$i1),
2200b57cec5SDimitry Andric                  (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
2210b57cec5SDimitry Andric                  "$i0, $i1">;
2220b57cec5SDimitry Andric
2230b57cec5SDimitry Andric// Shuffle lanes: shuffle
2240b57cec5SDimitry Andricdefm SHUFFLE :
2250b57cec5SDimitry Andric  SIMD_I<(outs V128:$dst),
2260b57cec5SDimitry Andric         (ins V128:$x, V128:$y,
2270b57cec5SDimitry Andric           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
2280b57cec5SDimitry Andric           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
2290b57cec5SDimitry Andric           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
2300b57cec5SDimitry Andric           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
2310b57cec5SDimitry Andric           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
2320b57cec5SDimitry Andric           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
2330b57cec5SDimitry Andric           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
2340b57cec5SDimitry Andric           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
2350b57cec5SDimitry Andric         (outs),
2360b57cec5SDimitry Andric         (ins
2370b57cec5SDimitry Andric           vec_i8imm_op:$m0, vec_i8imm_op:$m1,
2380b57cec5SDimitry Andric           vec_i8imm_op:$m2, vec_i8imm_op:$m3,
2390b57cec5SDimitry Andric           vec_i8imm_op:$m4, vec_i8imm_op:$m5,
2400b57cec5SDimitry Andric           vec_i8imm_op:$m6, vec_i8imm_op:$m7,
2410b57cec5SDimitry Andric           vec_i8imm_op:$m8, vec_i8imm_op:$m9,
2420b57cec5SDimitry Andric           vec_i8imm_op:$mA, vec_i8imm_op:$mB,
2430b57cec5SDimitry Andric           vec_i8imm_op:$mC, vec_i8imm_op:$mD,
2440b57cec5SDimitry Andric           vec_i8imm_op:$mE, vec_i8imm_op:$mF),
2450b57cec5SDimitry Andric         [],
2460b57cec5SDimitry Andric         "v8x16.shuffle\t$dst, $x, $y, "#
2470b57cec5SDimitry Andric           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
2480b57cec5SDimitry Andric           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
2490b57cec5SDimitry Andric         "v8x16.shuffle\t"#
2500b57cec5SDimitry Andric           "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
2510b57cec5SDimitry Andric           "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
2520b57cec5SDimitry Andric         3>;
2530b57cec5SDimitry Andric
2540b57cec5SDimitry Andric// Shuffles after custom lowering
2550b57cec5SDimitry Andricdef wasm_shuffle_t : SDTypeProfile<1, 18, []>;
2560b57cec5SDimitry Andricdef wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
2570b57cec5SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
2580b57cec5SDimitry Andricdef : Pat<(vec_t (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
2590b57cec5SDimitry Andric            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
2600b57cec5SDimitry Andric            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
2610b57cec5SDimitry Andric            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
2620b57cec5SDimitry Andric            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
2630b57cec5SDimitry Andric            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
2640b57cec5SDimitry Andric            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
2650b57cec5SDimitry Andric            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
2660b57cec5SDimitry Andric            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
2670b57cec5SDimitry Andric          (vec_t (SHUFFLE (vec_t V128:$x), (vec_t V128:$y),
2680b57cec5SDimitry Andric            (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
2690b57cec5SDimitry Andric            (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
2700b57cec5SDimitry Andric            (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
2710b57cec5SDimitry Andric            (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
2720b57cec5SDimitry Andric            (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
2730b57cec5SDimitry Andric            (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
2740b57cec5SDimitry Andric            (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
2750b57cec5SDimitry Andric            (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
2760b57cec5SDimitry Andric}
2770b57cec5SDimitry Andric
278*8bcb0991SDimitry Andric// Swizzle lanes: v8x16.swizzle
279*8bcb0991SDimitry Andricdef wasm_swizzle_t : SDTypeProfile<1, 2, []>;
280*8bcb0991SDimitry Andricdef wasm_swizzle : SDNode<"WebAssemblyISD::SWIZZLE", wasm_swizzle_t>;
281*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
282*8bcb0991SDimitry Andricdefm SWIZZLE :
283*8bcb0991SDimitry Andric  SIMD_I<(outs V128:$dst), (ins V128:$src, V128:$mask), (outs), (ins),
284*8bcb0991SDimitry Andric         [(set (v16i8 V128:$dst),
285*8bcb0991SDimitry Andric           (wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)))],
286*8bcb0991SDimitry Andric         "v8x16.swizzle\t$dst, $src, $mask", "v8x16.swizzle", 192>;
287*8bcb0991SDimitry Andric
288*8bcb0991SDimitry Andricdef : Pat<(int_wasm_swizzle (v16i8 V128:$src), (v16i8 V128:$mask)),
289*8bcb0991SDimitry Andric          (SWIZZLE V128:$src, V128:$mask)>;
290*8bcb0991SDimitry Andric
2910b57cec5SDimitry Andric// Create vector with identical lanes: splat
2920b57cec5SDimitry Andricdef splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
2930b57cec5SDimitry Andricdef splat4 : PatFrag<(ops node:$x), (build_vector
2940b57cec5SDimitry Andric                       node:$x, node:$x, node:$x, node:$x)>;
2950b57cec5SDimitry Andricdef splat8 : PatFrag<(ops node:$x), (build_vector
2960b57cec5SDimitry Andric                       node:$x, node:$x, node:$x, node:$x,
2970b57cec5SDimitry Andric                       node:$x, node:$x, node:$x, node:$x)>;
2980b57cec5SDimitry Andricdef splat16 : PatFrag<(ops node:$x), (build_vector
2990b57cec5SDimitry Andric                        node:$x, node:$x, node:$x, node:$x,
3000b57cec5SDimitry Andric                        node:$x, node:$x, node:$x, node:$x,
3010b57cec5SDimitry Andric                        node:$x, node:$x, node:$x, node:$x,
3020b57cec5SDimitry Andric                        node:$x, node:$x, node:$x, node:$x)>;
3030b57cec5SDimitry Andric
3040b57cec5SDimitry Andricmulticlass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
3050b57cec5SDimitry Andric                 PatFrag splat_pat, bits<32> simdop> {
3060b57cec5SDimitry Andric  // Prefer splats over v128.const for const splats (65 is lowest that works)
3070b57cec5SDimitry Andric  let AddedComplexity = 65 in
3080b57cec5SDimitry Andric  defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
3090b57cec5SDimitry Andric                             [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
3100b57cec5SDimitry Andric                             vec#".splat\t$dst, $x", vec#".splat", simdop>;
3110b57cec5SDimitry Andric}
3120b57cec5SDimitry Andric
3130b57cec5SDimitry Andricdefm "" : Splat<v16i8, "i8x16", I32, splat16, 4>;
3140b57cec5SDimitry Andricdefm "" : Splat<v8i16, "i16x8", I32, splat8, 8>;
3150b57cec5SDimitry Andricdefm "" : Splat<v4i32, "i32x4", I32, splat4, 12>;
3160b57cec5SDimitry Andricdefm "" : Splat<v2i64, "i64x2", I64, splat2, 15>;
3170b57cec5SDimitry Andricdefm "" : Splat<v4f32, "f32x4", F32, splat4, 18>;
3180b57cec5SDimitry Andricdefm "" : Splat<v2f64, "f64x2", F64, splat2, 21>;
3190b57cec5SDimitry Andric
3200b57cec5SDimitry Andric// scalar_to_vector leaves high lanes undefined, so can be a splat
3210b57cec5SDimitry Andricclass ScalarSplatPat<ValueType vec_t, ValueType lane_t,
3220b57cec5SDimitry Andric                     WebAssemblyRegClass reg_t> :
3230b57cec5SDimitry Andric  Pat<(vec_t (scalar_to_vector (lane_t reg_t:$x))),
3240b57cec5SDimitry Andric      (!cast<Instruction>("SPLAT_"#vec_t) reg_t:$x)>;
3250b57cec5SDimitry Andric
3260b57cec5SDimitry Andricdef : ScalarSplatPat<v16i8, i32, I32>;
3270b57cec5SDimitry Andricdef : ScalarSplatPat<v8i16, i32, I32>;
3280b57cec5SDimitry Andricdef : ScalarSplatPat<v4i32, i32, I32>;
3290b57cec5SDimitry Andricdef : ScalarSplatPat<v2i64, i64, I64>;
3300b57cec5SDimitry Andricdef : ScalarSplatPat<v4f32, f32, F32>;
3310b57cec5SDimitry Andricdef : ScalarSplatPat<v2f64, f64, F64>;
3320b57cec5SDimitry Andric
3330b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
3340b57cec5SDimitry Andric// Accessing lanes
3350b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
3360b57cec5SDimitry Andric
3370b57cec5SDimitry Andric// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
3380b57cec5SDimitry Andricmulticlass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
3390b57cec5SDimitry Andric                       WebAssemblyRegClass reg_t, bits<32> simdop,
3400b57cec5SDimitry Andric                       string suffix = "", SDNode extract = vector_extract> {
3410b57cec5SDimitry Andric  defm EXTRACT_LANE_#vec_t#suffix :
3420b57cec5SDimitry Andric      SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
3430b57cec5SDimitry Andric             (outs), (ins vec_i8imm_op:$idx),
3440b57cec5SDimitry Andric             [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
3450b57cec5SDimitry Andric             vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
3460b57cec5SDimitry Andric             vec#".extract_lane"#suffix#"\t$idx", simdop>;
3470b57cec5SDimitry Andric}
3480b57cec5SDimitry Andric
3490b57cec5SDimitry Andricmulticlass ExtractPat<ValueType lane_t, int mask> {
3500b57cec5SDimitry Andric  def _s : PatFrag<(ops node:$vec, node:$idx),
3510b57cec5SDimitry Andric                   (i32 (sext_inreg
3520b57cec5SDimitry Andric                     (i32 (vector_extract
3530b57cec5SDimitry Andric                       node:$vec,
3540b57cec5SDimitry Andric                       node:$idx
3550b57cec5SDimitry Andric                     )),
3560b57cec5SDimitry Andric                     lane_t
3570b57cec5SDimitry Andric                   ))>;
3580b57cec5SDimitry Andric  def _u : PatFrag<(ops node:$vec, node:$idx),
3590b57cec5SDimitry Andric                   (i32 (and
3600b57cec5SDimitry Andric                     (i32 (vector_extract
3610b57cec5SDimitry Andric                       node:$vec,
3620b57cec5SDimitry Andric                       node:$idx
3630b57cec5SDimitry Andric                     )),
3640b57cec5SDimitry Andric                     (i32 mask)
3650b57cec5SDimitry Andric                   ))>;
3660b57cec5SDimitry Andric}
3670b57cec5SDimitry Andric
3680b57cec5SDimitry Andricdefm extract_i8x16 : ExtractPat<i8, 0xff>;
3690b57cec5SDimitry Andricdefm extract_i16x8 : ExtractPat<i16, 0xffff>;
3700b57cec5SDimitry Andric
3710b57cec5SDimitry Andricmulticlass ExtractLaneExtended<string sign, bits<32> baseInst> {
3720b57cec5SDimitry Andric  defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
3730b57cec5SDimitry Andric                        !cast<PatFrag>("extract_i8x16"#sign)>;
3740b57cec5SDimitry Andric  defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 4), sign,
3750b57cec5SDimitry Andric                        !cast<PatFrag>("extract_i16x8"#sign)>;
3760b57cec5SDimitry Andric}
3770b57cec5SDimitry Andric
3780b57cec5SDimitry Andricdefm "" : ExtractLaneExtended<"_s", 5>;
379*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
3800b57cec5SDimitry Andricdefm "" : ExtractLaneExtended<"_u", 6>;
3810b57cec5SDimitry Andricdefm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
3820b57cec5SDimitry Andricdefm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 16>;
3830b57cec5SDimitry Andricdefm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 19>;
3840b57cec5SDimitry Andricdefm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 22>;
3850b57cec5SDimitry Andric
3860b57cec5SDimitry Andric// It would be more conventional to use unsigned extracts, but v8
3870b57cec5SDimitry Andric// doesn't implement them yet
3880b57cec5SDimitry Andricdef : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
3890b57cec5SDimitry Andric          (EXTRACT_LANE_v16i8_s V128:$vec, (i32 LaneIdx16:$idx))>;
3900b57cec5SDimitry Andricdef : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
3910b57cec5SDimitry Andric          (EXTRACT_LANE_v8i16_s V128:$vec, (i32 LaneIdx8:$idx))>;
3920b57cec5SDimitry Andric
3930b57cec5SDimitry Andric// Lower undef lane indices to zero
3940b57cec5SDimitry Andricdef : Pat<(and (i32 (vector_extract (v16i8 V128:$vec), undef)), (i32 0xff)),
3950b57cec5SDimitry Andric          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
3960b57cec5SDimitry Andricdef : Pat<(and (i32 (vector_extract (v8i16 V128:$vec), undef)), (i32 0xffff)),
3970b57cec5SDimitry Andric          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
3980b57cec5SDimitry Andricdef : Pat<(i32 (vector_extract (v16i8 V128:$vec), undef)),
3990b57cec5SDimitry Andric          (EXTRACT_LANE_v16i8_u V128:$vec, 0)>;
4000b57cec5SDimitry Andricdef : Pat<(i32 (vector_extract (v8i16 V128:$vec), undef)),
4010b57cec5SDimitry Andric          (EXTRACT_LANE_v8i16_u V128:$vec, 0)>;
4020b57cec5SDimitry Andricdef : Pat<(sext_inreg (i32 (vector_extract (v16i8 V128:$vec), undef)), i8),
4030b57cec5SDimitry Andric          (EXTRACT_LANE_v16i8_s V128:$vec, 0)>;
4040b57cec5SDimitry Andricdef : Pat<(sext_inreg (i32 (vector_extract (v8i16 V128:$vec), undef)), i16),
4050b57cec5SDimitry Andric          (EXTRACT_LANE_v8i16_s V128:$vec, 0)>;
4060b57cec5SDimitry Andricdef : Pat<(vector_extract (v4i32 V128:$vec), undef),
4070b57cec5SDimitry Andric          (EXTRACT_LANE_v4i32 V128:$vec, 0)>;
4080b57cec5SDimitry Andricdef : Pat<(vector_extract (v2i64 V128:$vec), undef),
4090b57cec5SDimitry Andric          (EXTRACT_LANE_v2i64 V128:$vec, 0)>;
4100b57cec5SDimitry Andricdef : Pat<(vector_extract (v4f32 V128:$vec), undef),
4110b57cec5SDimitry Andric          (EXTRACT_LANE_v4f32 V128:$vec, 0)>;
4120b57cec5SDimitry Andricdef : Pat<(vector_extract (v2f64 V128:$vec), undef),
4130b57cec5SDimitry Andric          (EXTRACT_LANE_v2f64 V128:$vec, 0)>;
4140b57cec5SDimitry Andric
4150b57cec5SDimitry Andric// Replace lane value: replace_lane
4160b57cec5SDimitry Andricmulticlass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
4170b57cec5SDimitry Andric                       WebAssemblyRegClass reg_t, ValueType lane_t,
4180b57cec5SDimitry Andric                       bits<32> simdop> {
4190b57cec5SDimitry Andric  defm REPLACE_LANE_#vec_t :
4200b57cec5SDimitry Andric      SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
4210b57cec5SDimitry Andric             (outs), (ins vec_i8imm_op:$idx),
4220b57cec5SDimitry Andric             [(set V128:$dst, (vector_insert
4230b57cec5SDimitry Andric               (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
4240b57cec5SDimitry Andric             vec#".replace_lane\t$dst, $vec, $idx, $x",
4250b57cec5SDimitry Andric             vec#".replace_lane\t$idx", simdop>;
4260b57cec5SDimitry Andric}
4270b57cec5SDimitry Andric
4280b57cec5SDimitry Andricdefm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 7>;
4290b57cec5SDimitry Andricdefm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 11>;
4300b57cec5SDimitry Andricdefm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 14>;
4310b57cec5SDimitry Andricdefm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 17>;
4320b57cec5SDimitry Andricdefm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 20>;
4330b57cec5SDimitry Andricdefm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 23>;
4340b57cec5SDimitry Andric
4350b57cec5SDimitry Andric// Lower undef lane indices to zero
4360b57cec5SDimitry Andricdef : Pat<(vector_insert (v16i8 V128:$vec), I32:$x, undef),
4370b57cec5SDimitry Andric          (REPLACE_LANE_v16i8 V128:$vec, 0, I32:$x)>;
4380b57cec5SDimitry Andricdef : Pat<(vector_insert (v8i16 V128:$vec), I32:$x, undef),
4390b57cec5SDimitry Andric          (REPLACE_LANE_v8i16 V128:$vec, 0, I32:$x)>;
4400b57cec5SDimitry Andricdef : Pat<(vector_insert (v4i32 V128:$vec), I32:$x, undef),
4410b57cec5SDimitry Andric          (REPLACE_LANE_v4i32 V128:$vec, 0, I32:$x)>;
4420b57cec5SDimitry Andricdef : Pat<(vector_insert (v2i64 V128:$vec), I64:$x, undef),
4430b57cec5SDimitry Andric          (REPLACE_LANE_v2i64 V128:$vec, 0, I64:$x)>;
4440b57cec5SDimitry Andricdef : Pat<(vector_insert (v4f32 V128:$vec), F32:$x, undef),
4450b57cec5SDimitry Andric          (REPLACE_LANE_v4f32 V128:$vec, 0, F32:$x)>;
4460b57cec5SDimitry Andricdef : Pat<(vector_insert (v2f64 V128:$vec), F64:$x, undef),
4470b57cec5SDimitry Andric          (REPLACE_LANE_v2f64 V128:$vec, 0, F64:$x)>;
4480b57cec5SDimitry Andric
4490b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
4500b57cec5SDimitry Andric// Comparisons
4510b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
4520b57cec5SDimitry Andric
4530b57cec5SDimitry Andricmulticlass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
4540b57cec5SDimitry Andric                         string name, CondCode cond, bits<32> simdop> {
4550b57cec5SDimitry Andric  defm _#vec_t :
4560b57cec5SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
4570b57cec5SDimitry Andric           [(set (out_t V128:$dst),
4580b57cec5SDimitry Andric             (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond)
4590b57cec5SDimitry Andric           )],
4600b57cec5SDimitry Andric           vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
4610b57cec5SDimitry Andric}
4620b57cec5SDimitry Andric
4630b57cec5SDimitry Andricmulticlass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
4640b57cec5SDimitry Andric  defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
4650b57cec5SDimitry Andric  defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
4660b57cec5SDimitry Andric                          !add(baseInst, 10)>;
4670b57cec5SDimitry Andric  defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
4680b57cec5SDimitry Andric                          !add(baseInst, 20)>;
4690b57cec5SDimitry Andric}
4700b57cec5SDimitry Andric
4710b57cec5SDimitry Andricmulticlass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
4720b57cec5SDimitry Andric  defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
4730b57cec5SDimitry Andric  defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
4740b57cec5SDimitry Andric                          !add(baseInst, 6)>;
4750b57cec5SDimitry Andric}
4760b57cec5SDimitry Andric
4770b57cec5SDimitry Andric// Equality: eq
4780b57cec5SDimitry Andriclet isCommutable = 1 in {
4790b57cec5SDimitry Andricdefm EQ : SIMDConditionInt<"eq", SETEQ, 24>;
4800b57cec5SDimitry Andricdefm EQ : SIMDConditionFP<"eq", SETOEQ, 64>;
4810b57cec5SDimitry Andric} // isCommutable = 1
4820b57cec5SDimitry Andric
4830b57cec5SDimitry Andric// Non-equality: ne
4840b57cec5SDimitry Andriclet isCommutable = 1 in {
4850b57cec5SDimitry Andricdefm NE : SIMDConditionInt<"ne", SETNE, 25>;
4860b57cec5SDimitry Andricdefm NE : SIMDConditionFP<"ne", SETUNE, 65>;
4870b57cec5SDimitry Andric} // isCommutable = 1
4880b57cec5SDimitry Andric
4890b57cec5SDimitry Andric// Less than: lt_s / lt_u / lt
4900b57cec5SDimitry Andricdefm LT_S : SIMDConditionInt<"lt_s", SETLT, 26>;
4910b57cec5SDimitry Andricdefm LT_U : SIMDConditionInt<"lt_u", SETULT, 27>;
4920b57cec5SDimitry Andricdefm LT : SIMDConditionFP<"lt", SETOLT, 66>;
4930b57cec5SDimitry Andric
4940b57cec5SDimitry Andric// Greater than: gt_s / gt_u / gt
4950b57cec5SDimitry Andricdefm GT_S : SIMDConditionInt<"gt_s", SETGT, 28>;
4960b57cec5SDimitry Andricdefm GT_U : SIMDConditionInt<"gt_u", SETUGT, 29>;
4970b57cec5SDimitry Andricdefm GT : SIMDConditionFP<"gt", SETOGT, 67>;
4980b57cec5SDimitry Andric
4990b57cec5SDimitry Andric// Less than or equal: le_s / le_u / le
5000b57cec5SDimitry Andricdefm LE_S : SIMDConditionInt<"le_s", SETLE, 30>;
5010b57cec5SDimitry Andricdefm LE_U : SIMDConditionInt<"le_u", SETULE, 31>;
5020b57cec5SDimitry Andricdefm LE : SIMDConditionFP<"le", SETOLE, 68>;
5030b57cec5SDimitry Andric
5040b57cec5SDimitry Andric// Greater than or equal: ge_s / ge_u / ge
5050b57cec5SDimitry Andricdefm GE_S : SIMDConditionInt<"ge_s", SETGE, 32>;
5060b57cec5SDimitry Andricdefm GE_U : SIMDConditionInt<"ge_u", SETUGE, 33>;
5070b57cec5SDimitry Andricdefm GE : SIMDConditionFP<"ge", SETOGE, 69>;
5080b57cec5SDimitry Andric
5090b57cec5SDimitry Andric// Lower float comparisons that don't care about NaN to standard WebAssembly
5100b57cec5SDimitry Andric// float comparisons. These instructions are generated with nnan and in the
5110b57cec5SDimitry Andric// target-independent expansion of unordered comparisons and ordered ne.
5120b57cec5SDimitry Andricforeach nodes = [[seteq, EQ_v4f32], [setne, NE_v4f32], [setlt, LT_v4f32],
5130b57cec5SDimitry Andric                 [setgt, GT_v4f32], [setle, LE_v4f32], [setge, GE_v4f32]] in
5140b57cec5SDimitry Andricdef : Pat<(v4i32 (nodes[0] (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
5150b57cec5SDimitry Andric          (v4i32 (nodes[1] (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
5160b57cec5SDimitry Andric
5170b57cec5SDimitry Andricforeach nodes = [[seteq, EQ_v2f64], [setne, NE_v2f64], [setlt, LT_v2f64],
5180b57cec5SDimitry Andric                 [setgt, GT_v2f64], [setle, LE_v2f64], [setge, GE_v2f64]] in
5190b57cec5SDimitry Andricdef : Pat<(v2i64 (nodes[0] (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
5200b57cec5SDimitry Andric          (v2i64 (nodes[1] (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
5210b57cec5SDimitry Andric
5220b57cec5SDimitry Andric
5230b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
5240b57cec5SDimitry Andric// Bitwise operations
5250b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
5260b57cec5SDimitry Andric
5270b57cec5SDimitry Andricmulticlass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
5280b57cec5SDimitry Andric                      bits<32> simdop> {
5290b57cec5SDimitry Andric  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
5300b57cec5SDimitry Andric                        (outs), (ins),
5310b57cec5SDimitry Andric                        [(set (vec_t V128:$dst),
5320b57cec5SDimitry Andric                          (node (vec_t V128:$lhs), (vec_t V128:$rhs))
5330b57cec5SDimitry Andric                        )],
5340b57cec5SDimitry Andric                        vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
5350b57cec5SDimitry Andric                        simdop>;
5360b57cec5SDimitry Andric}
5370b57cec5SDimitry Andric
5380b57cec5SDimitry Andricmulticlass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
5390b57cec5SDimitry Andric  defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
5400b57cec5SDimitry Andric  defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
5410b57cec5SDimitry Andric  defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
5420b57cec5SDimitry Andric  defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
5430b57cec5SDimitry Andric}
5440b57cec5SDimitry Andric
5450b57cec5SDimitry Andricmulticlass SIMDUnary<ValueType vec_t, string vec, SDNode node, string name,
5460b57cec5SDimitry Andric                     bits<32> simdop> {
5470b57cec5SDimitry Andric  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
5480b57cec5SDimitry Andric                        [(set (vec_t V128:$dst),
5490b57cec5SDimitry Andric                          (vec_t (node (vec_t V128:$vec)))
5500b57cec5SDimitry Andric                        )],
5510b57cec5SDimitry Andric                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
5520b57cec5SDimitry Andric}
5530b57cec5SDimitry Andric
5540b57cec5SDimitry Andric// Bitwise logic: v128.not
5550b57cec5SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64] in
5560b57cec5SDimitry Andricdefm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
5570b57cec5SDimitry Andric
5580b57cec5SDimitry Andric// Bitwise logic: v128.and / v128.or / v128.xor
5590b57cec5SDimitry Andriclet isCommutable = 1 in {
5600b57cec5SDimitry Andricdefm AND : SIMDBitwise<and, "and", 77>;
5610b57cec5SDimitry Andricdefm OR : SIMDBitwise<or, "or", 78>;
5620b57cec5SDimitry Andricdefm XOR : SIMDBitwise<xor, "xor", 79>;
5630b57cec5SDimitry Andric} // isCommutable = 1
5640b57cec5SDimitry Andric
565*8bcb0991SDimitry Andric// Bitwise logic: v128.andnot
566*8bcb0991SDimitry Andricdef andnot : PatFrag<(ops node:$left, node:$right), (and $left, (vnot $right))>;
567*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
568*8bcb0991SDimitry Andricdefm ANDNOT : SIMDBitwise<andnot, "andnot", 216>;
569*8bcb0991SDimitry Andric
5700b57cec5SDimitry Andric// Bitwise select: v128.bitselect
5710b57cec5SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
5720b57cec5SDimitry Andric  defm BITSELECT_#vec_t :
5730b57cec5SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
5740b57cec5SDimitry Andric           [(set (vec_t V128:$dst),
5750b57cec5SDimitry Andric             (vec_t (int_wasm_bitselect
5760b57cec5SDimitry Andric               (vec_t V128:$v1), (vec_t V128:$v2), (vec_t V128:$c)
5770b57cec5SDimitry Andric             ))
5780b57cec5SDimitry Andric           )],
5790b57cec5SDimitry Andric           "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 80>;
5800b57cec5SDimitry Andric
5810b57cec5SDimitry Andric// Bitselect is equivalent to (c & v1) | (~c & v2)
5820b57cec5SDimitry Andricforeach vec_t = [v16i8, v8i16, v4i32, v2i64] in
5830b57cec5SDimitry Andric  def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
5840b57cec5SDimitry Andric              (and (vnot V128:$c), (vec_t V128:$v2)))),
5850b57cec5SDimitry Andric            (!cast<Instruction>("BITSELECT_"#vec_t)
5860b57cec5SDimitry Andric              V128:$v1, V128:$v2, V128:$c)>;
5870b57cec5SDimitry Andric
5880b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
5890b57cec5SDimitry Andric// Integer unary arithmetic
5900b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
5910b57cec5SDimitry Andric
5920b57cec5SDimitry Andricmulticlass SIMDUnaryInt<SDNode node, string name, bits<32> baseInst> {
5930b57cec5SDimitry Andric  defm "" : SIMDUnary<v16i8, "i8x16", node, name, baseInst>;
5940b57cec5SDimitry Andric  defm "" : SIMDUnary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
5950b57cec5SDimitry Andric  defm "" : SIMDUnary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
5960b57cec5SDimitry Andric  defm "" : SIMDUnary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
5970b57cec5SDimitry Andric}
5980b57cec5SDimitry Andric
5990b57cec5SDimitry Andricmulticlass SIMDReduceVec<ValueType vec_t, string vec, SDNode op, string name,
6000b57cec5SDimitry Andric                         bits<32> simdop> {
6010b57cec5SDimitry Andric  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
6020b57cec5SDimitry Andric                        [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
6030b57cec5SDimitry Andric                        vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
6040b57cec5SDimitry Andric}
6050b57cec5SDimitry Andric
6060b57cec5SDimitry Andricmulticlass SIMDReduce<SDNode op, string name, bits<32> baseInst> {
6070b57cec5SDimitry Andric  defm "" : SIMDReduceVec<v16i8, "i8x16", op, name, baseInst>;
6080b57cec5SDimitry Andric  defm "" : SIMDReduceVec<v8i16, "i16x8", op, name, !add(baseInst, 17)>;
6090b57cec5SDimitry Andric  defm "" : SIMDReduceVec<v4i32, "i32x4", op, name, !add(baseInst, 34)>;
6100b57cec5SDimitry Andric  defm "" : SIMDReduceVec<v2i64, "i64x2", op, name, !add(baseInst, 51)>;
6110b57cec5SDimitry Andric}
6120b57cec5SDimitry Andric
6130b57cec5SDimitry Andric// Integer vector negation
6140b57cec5SDimitry Andricdef ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
6150b57cec5SDimitry Andric
6160b57cec5SDimitry Andric// Integer negation: neg
6170b57cec5SDimitry Andricdefm NEG : SIMDUnaryInt<ivneg, "neg", 81>;
6180b57cec5SDimitry Andric
6190b57cec5SDimitry Andric// Any lane true: any_true
6200b57cec5SDimitry Andricdefm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 82>;
6210b57cec5SDimitry Andric
6220b57cec5SDimitry Andric// All lanes true: all_true
6230b57cec5SDimitry Andricdefm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 83>;
6240b57cec5SDimitry Andric
6250b57cec5SDimitry Andric// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
6260b57cec5SDimitry Andric// can be folded out
6270b57cec5SDimitry Andricforeach reduction =
6280b57cec5SDimitry Andric  [["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
6290b57cec5SDimitry Andricforeach ty = [v16i8, v8i16, v4i32, v2i64] in {
6300b57cec5SDimitry Andricdef : Pat<(i32 (and
6310b57cec5SDimitry Andric            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
6320b57cec5SDimitry Andric            (i32 1)
6330b57cec5SDimitry Andric          )),
6340b57cec5SDimitry Andric          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
6350b57cec5SDimitry Andricdef : Pat<(i32 (setne
6360b57cec5SDimitry Andric            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
6370b57cec5SDimitry Andric            (i32 0)
6380b57cec5SDimitry Andric          )),
6390b57cec5SDimitry Andric          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
6400b57cec5SDimitry Andricdef : Pat<(i32 (seteq
6410b57cec5SDimitry Andric            (i32 (!cast<Intrinsic>(reduction[0]) (ty V128:$x))),
6420b57cec5SDimitry Andric            (i32 1)
6430b57cec5SDimitry Andric          )),
6440b57cec5SDimitry Andric          (i32 (!cast<NI>(reduction[1]#"_"#ty) (ty V128:$x)))>;
6450b57cec5SDimitry Andric}
6460b57cec5SDimitry Andric
6470b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
6480b57cec5SDimitry Andric// Bit shifts
6490b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
6500b57cec5SDimitry Andric
6510b57cec5SDimitry Andricmulticlass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
6520b57cec5SDimitry Andric                     string name, bits<32> simdop> {
6530b57cec5SDimitry Andric  defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
6540b57cec5SDimitry Andric                        (outs), (ins),
6550b57cec5SDimitry Andric                        [(set (vec_t V128:$dst),
6560b57cec5SDimitry Andric                          (node V128:$vec, (vec_t shift_vec)))],
6570b57cec5SDimitry Andric                        vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
6580b57cec5SDimitry Andric}
6590b57cec5SDimitry Andric
6600b57cec5SDimitry Andricmulticlass SIMDShiftInt<SDNode node, string name, bits<32> baseInst> {
6610b57cec5SDimitry Andric  defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
6620b57cec5SDimitry Andric  defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
6630b57cec5SDimitry Andric                      !add(baseInst, 17)>;
6640b57cec5SDimitry Andric  defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
6650b57cec5SDimitry Andric                      !add(baseInst, 34)>;
6660b57cec5SDimitry Andric  defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
6670b57cec5SDimitry Andric                      name, !add(baseInst, 51)>;
6680b57cec5SDimitry Andric}
6690b57cec5SDimitry Andric
6700b57cec5SDimitry Andric// Left shift by scalar: shl
6710b57cec5SDimitry Andricdefm SHL : SIMDShiftInt<shl, "shl", 84>;
6720b57cec5SDimitry Andric
6730b57cec5SDimitry Andric// Right shift by scalar: shr_s / shr_u
6740b57cec5SDimitry Andricdefm SHR_S : SIMDShiftInt<sra, "shr_s", 85>;
6750b57cec5SDimitry Andricdefm SHR_U : SIMDShiftInt<srl, "shr_u", 86>;
6760b57cec5SDimitry Andric
6770b57cec5SDimitry Andric// Truncate i64 shift operands to i32s, except if they are already i32s
6780b57cec5SDimitry Andricforeach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in {
6790b57cec5SDimitry Andricdef : Pat<(v2i64 (shifts[0]
6800b57cec5SDimitry Andric            (v2i64 V128:$vec),
6810b57cec5SDimitry Andric            (v2i64 (splat2 (i64 (sext I32:$x))))
6820b57cec5SDimitry Andric          )),
6830b57cec5SDimitry Andric          (v2i64 (shifts[1] (v2i64 V128:$vec), (i32 I32:$x)))>;
6840b57cec5SDimitry Andricdef : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
6850b57cec5SDimitry Andric          (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
6860b57cec5SDimitry Andric}
6870b57cec5SDimitry Andric
6880b57cec5SDimitry Andric// 2xi64 shifts with constant shift amounts are custom lowered to avoid wrapping
6890b57cec5SDimitry Andricdef wasm_shift_t : SDTypeProfile<1, 2,
6900b57cec5SDimitry Andric  [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisVT<2, i32>]
6910b57cec5SDimitry Andric>;
6920b57cec5SDimitry Andricdef wasm_shl : SDNode<"WebAssemblyISD::VEC_SHL", wasm_shift_t>;
6930b57cec5SDimitry Andricdef wasm_shr_s : SDNode<"WebAssemblyISD::VEC_SHR_S", wasm_shift_t>;
6940b57cec5SDimitry Andricdef wasm_shr_u : SDNode<"WebAssemblyISD::VEC_SHR_U", wasm_shift_t>;
6950b57cec5SDimitry Andricforeach shifts = [[wasm_shl, SHL_v2i64],
6960b57cec5SDimitry Andric                  [wasm_shr_s, SHR_S_v2i64],
6970b57cec5SDimitry Andric                  [wasm_shr_u, SHR_U_v2i64]] in
6980b57cec5SDimitry Andricdef : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), I32:$x)),
6990b57cec5SDimitry Andric          (v2i64 (shifts[1] (v2i64 V128:$vec), I32:$x))>;
7000b57cec5SDimitry Andric
7010b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7020b57cec5SDimitry Andric// Integer binary arithmetic
7030b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7040b57cec5SDimitry Andric
7050b57cec5SDimitry Andricmulticlass SIMDBinaryIntSmall<SDNode node, string name, bits<32> baseInst> {
7060b57cec5SDimitry Andric  defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
7070b57cec5SDimitry Andric  defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 17)>;
7080b57cec5SDimitry Andric}
7090b57cec5SDimitry Andric
7100b57cec5SDimitry Andricmulticlass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
7110b57cec5SDimitry Andric  defm "" : SIMDBinaryIntSmall<node, name, baseInst>;
7120b57cec5SDimitry Andric  defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 34)>;
7130b57cec5SDimitry Andric}
7140b57cec5SDimitry Andric
7150b57cec5SDimitry Andricmulticlass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
7160b57cec5SDimitry Andric  defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
7170b57cec5SDimitry Andric  defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 51)>;
7180b57cec5SDimitry Andric}
7190b57cec5SDimitry Andric
7200b57cec5SDimitry Andric// Integer addition: add / add_saturate_s / add_saturate_u
7210b57cec5SDimitry Andriclet isCommutable = 1 in {
7220b57cec5SDimitry Andricdefm ADD : SIMDBinaryInt<add, "add", 87>;
7230b57cec5SDimitry Andricdefm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 88>;
7240b57cec5SDimitry Andricdefm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 89>;
7250b57cec5SDimitry Andric} // isCommutable = 1
7260b57cec5SDimitry Andric
7270b57cec5SDimitry Andric// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
7280b57cec5SDimitry Andricdefm SUB : SIMDBinaryInt<sub, "sub", 90>;
7290b57cec5SDimitry Andricdefm SUB_SAT_S :
7300b57cec5SDimitry Andric  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 91>;
7310b57cec5SDimitry Andricdefm SUB_SAT_U :
7320b57cec5SDimitry Andric  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 92>;
7330b57cec5SDimitry Andric
7340b57cec5SDimitry Andric// Integer multiplication: mul
7350b57cec5SDimitry Andricdefm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 93>;
7360b57cec5SDimitry Andric
7370b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7380b57cec5SDimitry Andric// Floating-point unary arithmetic
7390b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7400b57cec5SDimitry Andric
7410b57cec5SDimitry Andricmulticlass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
7420b57cec5SDimitry Andric  defm "" : SIMDUnary<v4f32, "f32x4", node, name, baseInst>;
7430b57cec5SDimitry Andric  defm "" : SIMDUnary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
7440b57cec5SDimitry Andric}
7450b57cec5SDimitry Andric
7460b57cec5SDimitry Andric// Absolute value: abs
7470b57cec5SDimitry Andricdefm ABS : SIMDUnaryFP<fabs, "abs", 149>;
7480b57cec5SDimitry Andric
7490b57cec5SDimitry Andric// Negation: neg
7500b57cec5SDimitry Andricdefm NEG : SIMDUnaryFP<fneg, "neg", 150>;
7510b57cec5SDimitry Andric
7520b57cec5SDimitry Andric// Square root: sqrt
753*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
7540b57cec5SDimitry Andricdefm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 151>;
7550b57cec5SDimitry Andric
7560b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7570b57cec5SDimitry Andric// Floating-point binary arithmetic
7580b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7590b57cec5SDimitry Andric
7600b57cec5SDimitry Andricmulticlass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
7610b57cec5SDimitry Andric  defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
7620b57cec5SDimitry Andric  defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 11)>;
7630b57cec5SDimitry Andric}
7640b57cec5SDimitry Andric
7650b57cec5SDimitry Andric// Addition: add
7660b57cec5SDimitry Andriclet isCommutable = 1 in
7670b57cec5SDimitry Andricdefm ADD : SIMDBinaryFP<fadd, "add", 154>;
7680b57cec5SDimitry Andric
7690b57cec5SDimitry Andric// Subtraction: sub
7700b57cec5SDimitry Andricdefm SUB : SIMDBinaryFP<fsub, "sub", 155>;
7710b57cec5SDimitry Andric
7720b57cec5SDimitry Andric// Multiplication: mul
7730b57cec5SDimitry Andriclet isCommutable = 1 in
7740b57cec5SDimitry Andricdefm MUL : SIMDBinaryFP<fmul, "mul", 156>;
7750b57cec5SDimitry Andric
7760b57cec5SDimitry Andric// Division: div
777*8bcb0991SDimitry Andriclet Predicates = [HasUnimplementedSIMD128] in
7780b57cec5SDimitry Andricdefm DIV : SIMDBinaryFP<fdiv, "div", 157>;
7790b57cec5SDimitry Andric
7800b57cec5SDimitry Andric// NaN-propagating minimum: min
7810b57cec5SDimitry Andricdefm MIN : SIMDBinaryFP<fminimum, "min", 158>;
7820b57cec5SDimitry Andric
7830b57cec5SDimitry Andric// NaN-propagating maximum: max
7840b57cec5SDimitry Andricdefm MAX : SIMDBinaryFP<fmaximum, "max", 159>;
7850b57cec5SDimitry Andric
7860b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7870b57cec5SDimitry Andric// Conversions
7880b57cec5SDimitry Andric//===----------------------------------------------------------------------===//
7890b57cec5SDimitry Andric
7900b57cec5SDimitry Andricmulticlass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
7910b57cec5SDimitry Andric                       string name, bits<32> simdop> {
7920b57cec5SDimitry Andric  defm op#_#vec_t#_#arg_t :
7930b57cec5SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
7940b57cec5SDimitry Andric           [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
7950b57cec5SDimitry Andric           name#"\t$dst, $vec", name, simdop>;
7960b57cec5SDimitry Andric}
7970b57cec5SDimitry Andric
7980b57cec5SDimitry Andric// Integer to floating point: convert
7990b57cec5SDimitry Andricdefm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_i32x4_s", 175>;
8000b57cec5SDimitry Andricdefm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_i32x4_u", 176>;
8010b57cec5SDimitry Andricdefm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_i64x2_s", 177>;
8020b57cec5SDimitry Andricdefm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_i64x2_u", 178>;
8030b57cec5SDimitry Andric
8040b57cec5SDimitry Andric// Floating point to integer with saturation: trunc_sat
8050b57cec5SDimitry Andricdefm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_f32x4_s", 171>;
8060b57cec5SDimitry Andricdefm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_f32x4_u", 172>;
8070b57cec5SDimitry Andricdefm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_f64x2_s", 173>;
8080b57cec5SDimitry Andricdefm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_f64x2_u", 174>;
8090b57cec5SDimitry Andric
810*8bcb0991SDimitry Andric// Widening operations
811*8bcb0991SDimitry Andricmulticlass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
812*8bcb0991SDimitry Andric                     bits<32> baseInst> {
813*8bcb0991SDimitry Andric  defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_signed,
814*8bcb0991SDimitry Andric                        vec#".widen_low_"#arg#"_s", baseInst>;
815*8bcb0991SDimitry Andric  defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_signed,
816*8bcb0991SDimitry Andric                        vec#".widen_high_"#arg#"_s", !add(baseInst, 1)>;
817*8bcb0991SDimitry Andric  defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_low_unsigned,
818*8bcb0991SDimitry Andric                        vec#".widen_low_"#arg#"_u", !add(baseInst, 2)>;
819*8bcb0991SDimitry Andric  defm "" : SIMDConvert<vec_t, arg_t, int_wasm_widen_high_unsigned,
820*8bcb0991SDimitry Andric                        vec#".widen_high_"#arg#"_u", !add(baseInst, 3)>;
821*8bcb0991SDimitry Andric}
822*8bcb0991SDimitry Andric
823*8bcb0991SDimitry Andricdefm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 202>;
824*8bcb0991SDimitry Andricdefm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 206>;
825*8bcb0991SDimitry Andric
826*8bcb0991SDimitry Andric// Narrowing operations
827*8bcb0991SDimitry Andricmulticlass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
828*8bcb0991SDimitry Andric                      bits<32> baseInst> {
829*8bcb0991SDimitry Andric  defm NARROW_S_#vec_t :
830*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
831*8bcb0991SDimitry Andric           [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_signed
832*8bcb0991SDimitry Andric             (arg_t V128:$low), (arg_t V128:$high))))],
833*8bcb0991SDimitry Andric           vec#".narrow_"#arg#"_s\t$dst, $low, $high", vec#".narrow_"#arg#"_s",
834*8bcb0991SDimitry Andric           baseInst>;
835*8bcb0991SDimitry Andric  defm NARROW_U_#vec_t :
836*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
837*8bcb0991SDimitry Andric           [(set (vec_t V128:$dst), (vec_t (int_wasm_narrow_unsigned
838*8bcb0991SDimitry Andric             (arg_t V128:$low), (arg_t V128:$high))))],
839*8bcb0991SDimitry Andric           vec#".narrow_"#arg#"_u\t$dst, $low, $high", vec#".narrow_"#arg#"_u",
840*8bcb0991SDimitry Andric           !add(baseInst, 1)>;
841*8bcb0991SDimitry Andric}
842*8bcb0991SDimitry Andric
843*8bcb0991SDimitry Andricdefm "" : SIMDNarrow<v16i8, "i8x16", v8i16, "i16x8", 198>;
844*8bcb0991SDimitry Andricdefm "" : SIMDNarrow<v8i16, "i16x8", v4i32, "i32x4", 200>;
845*8bcb0991SDimitry Andric
8460b57cec5SDimitry Andric// Lower llvm.wasm.trunc.saturate.* to saturating instructions
8470b57cec5SDimitry Andricdef : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
8480b57cec5SDimitry Andric          (fp_to_sint_v4i32_v4f32 (v4f32 V128:$src))>;
8490b57cec5SDimitry Andricdef : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
8500b57cec5SDimitry Andric          (fp_to_uint_v4i32_v4f32 (v4f32 V128:$src))>;
8510b57cec5SDimitry Andricdef : Pat<(v2i64 (int_wasm_trunc_saturate_signed (v2f64 V128:$src))),
8520b57cec5SDimitry Andric          (fp_to_sint_v2i64_v2f64 (v2f64 V128:$src))>;
8530b57cec5SDimitry Andricdef : Pat<(v2i64 (int_wasm_trunc_saturate_unsigned (v2f64 V128:$src))),
8540b57cec5SDimitry Andric          (fp_to_uint_v2i64_v2f64 (v2f64 V128:$src))>;
8550b57cec5SDimitry Andric
8560b57cec5SDimitry Andric// Bitcasts are nops
8570b57cec5SDimitry Andric// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
8580b57cec5SDimitry Andricforeach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
8590b57cec5SDimitry Andricforeach t2 = !foldl(
8600b57cec5SDimitry Andric  []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
8610b57cec5SDimitry Andric  acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
8620b57cec5SDimitry Andric    acc, !listconcat(acc, [cur])
8630b57cec5SDimitry Andric  )
8640b57cec5SDimitry Andric) in
8650b57cec5SDimitry Andricdef : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
866*8bcb0991SDimitry Andric
867*8bcb0991SDimitry Andric//===----------------------------------------------------------------------===//
868*8bcb0991SDimitry Andric// Quasi-Fused Multiply- Add and Subtract (QFMA/QFMS)
869*8bcb0991SDimitry Andric//===----------------------------------------------------------------------===//
870*8bcb0991SDimitry Andric
871*8bcb0991SDimitry Andricmulticlass SIMDQFM<ValueType vec_t, string vec, bits<32> baseInst> {
872*8bcb0991SDimitry Andric  defm QFMA_#vec_t :
873*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
874*8bcb0991SDimitry Andric           (outs), (ins),
875*8bcb0991SDimitry Andric           [(set (vec_t V128:$dst),
876*8bcb0991SDimitry Andric             (int_wasm_qfma (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
877*8bcb0991SDimitry Andric           vec#".qfma\t$dst, $a, $b, $c", vec#".qfma", baseInst>;
878*8bcb0991SDimitry Andric  defm QFMS_#vec_t :
879*8bcb0991SDimitry Andric    SIMD_I<(outs V128:$dst), (ins V128:$a, V128:$b, V128:$c),
880*8bcb0991SDimitry Andric           (outs), (ins),
881*8bcb0991SDimitry Andric           [(set (vec_t V128:$dst),
882*8bcb0991SDimitry Andric             (int_wasm_qfms (vec_t V128:$a), (vec_t V128:$b), (vec_t V128:$c)))],
883*8bcb0991SDimitry Andric           vec#".qfms\t$dst, $a, $b, $c", vec#".qfms", !add(baseInst, 1)>;
884*8bcb0991SDimitry Andric}
885*8bcb0991SDimitry Andric
886*8bcb0991SDimitry Andricdefm "" : SIMDQFM<v4f32, "f32x4", 0x98>;
887*8bcb0991SDimitry Andricdefm "" : SIMDQFM<v2f64, "f64x2", 0xa3>;
888