1// WebAssemblyInstrInfo.td-Describe the WebAssembly Instructions-*- tablegen -*- 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly Instruction definitions. 11/// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// WebAssembly Instruction Predicate Definitions. 16//===----------------------------------------------------------------------===// 17 18def IsPIC : Predicate<"TM.isPositionIndependent()">; 19def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 20 21def HasAddr32 : Predicate<"!Subtarget->hasAddr64()">; 22 23def HasAddr64 : Predicate<"Subtarget->hasAddr64()">; 24 25def HasSIMD128 : 26 Predicate<"Subtarget->hasSIMD128()">, 27 AssemblerPredicate<"FeatureSIMD128", "simd128">; 28 29def HasUnimplementedSIMD128 : 30 Predicate<"Subtarget->hasUnimplementedSIMD128()">, 31 AssemblerPredicate<"FeatureUnimplementedSIMD128", "unimplemented-simd128">; 32 33def HasAtomics : 34 Predicate<"Subtarget->hasAtomics()">, 35 AssemblerPredicate<"FeatureAtomics", "atomics">; 36 37def HasMultivalue : 38 Predicate<"Subtarget->hasMultivalue()">, 39 AssemblerPredicate<"FeatureMultivalue", "multivalue">; 40 41def HasNontrappingFPToInt : 42 Predicate<"Subtarget->hasNontrappingFPToInt()">, 43 AssemblerPredicate<"FeatureNontrappingFPToInt", "nontrapping-fptoint">; 44 45def NotHasNontrappingFPToInt : 46 Predicate<"!Subtarget->hasNontrappingFPToInt()">, 47 AssemblerPredicate<"!FeatureNontrappingFPToInt", "nontrapping-fptoint">; 48 49def HasSignExt : 50 Predicate<"Subtarget->hasSignExt()">, 51 AssemblerPredicate<"FeatureSignExt", "sign-ext">; 52 53def HasTailCall : 54 Predicate<"Subtarget->hasTailCall()">, 55 AssemblerPredicate<"FeatureTailCall", "tail-call">; 56 57def HasExceptionHandling : 58 Predicate<"Subtarget->hasExceptionHandling()">, 59 AssemblerPredicate<"FeatureExceptionHandling", "exception-handling">; 60 61def HasBulkMemory : 62 Predicate<"Subtarget->hasBulkMemory()">, 63 AssemblerPredicate<"FeatureBulkMemory", "bulk-memory">; 64 65//===----------------------------------------------------------------------===// 66// WebAssembly-specific DAG Node Types. 67//===----------------------------------------------------------------------===// 68 69def SDT_WebAssemblyCallSeqStart : SDCallSeqStart<[SDTCisVT<0, iPTR>, 70 SDTCisVT<1, iPTR>]>; 71def SDT_WebAssemblyCallSeqEnd : 72 SDCallSeqEnd<[SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 73def SDT_WebAssemblyCall0 : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 74def SDT_WebAssemblyCall1 : SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>; 75def SDT_WebAssemblyBrTable : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 76def SDT_WebAssemblyArgument : SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>; 77def SDT_WebAssemblyReturn : SDTypeProfile<0, -1, []>; 78def SDT_WebAssemblyWrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 79 SDTCisPtrTy<0>]>; 80def SDT_WebAssemblyWrapperPIC : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 81 SDTCisPtrTy<0>]>; 82def SDT_WebAssemblyThrow : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; 83 84//===----------------------------------------------------------------------===// 85// WebAssembly-specific DAG Nodes. 86//===----------------------------------------------------------------------===// 87 88def WebAssemblycallseq_start : 89 SDNode<"ISD::CALLSEQ_START", SDT_WebAssemblyCallSeqStart, 90 [SDNPHasChain, SDNPOutGlue]>; 91def WebAssemblycallseq_end : 92 SDNode<"ISD::CALLSEQ_END", SDT_WebAssemblyCallSeqEnd, 93 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 94def WebAssemblycall0 : SDNode<"WebAssemblyISD::CALL0", 95 SDT_WebAssemblyCall0, 96 [SDNPHasChain, SDNPVariadic]>; 97def WebAssemblycall1 : SDNode<"WebAssemblyISD::CALL1", 98 SDT_WebAssemblyCall1, 99 [SDNPHasChain, SDNPVariadic]>; 100def WebAssemblyretcall : SDNode<"WebAssemblyISD::RET_CALL", 101 SDT_WebAssemblyCall0, 102 [SDNPHasChain, SDNPVariadic]>; 103def WebAssemblybr_table : SDNode<"WebAssemblyISD::BR_TABLE", 104 SDT_WebAssemblyBrTable, 105 [SDNPHasChain, SDNPVariadic]>; 106def WebAssemblyargument : SDNode<"WebAssemblyISD::ARGUMENT", 107 SDT_WebAssemblyArgument>; 108def WebAssemblyreturn : SDNode<"WebAssemblyISD::RETURN", 109 SDT_WebAssemblyReturn, 110 [SDNPHasChain, SDNPVariadic]>; 111def WebAssemblywrapper : SDNode<"WebAssemblyISD::Wrapper", 112 SDT_WebAssemblyWrapper>; 113def WebAssemblywrapperPIC : SDNode<"WebAssemblyISD::WrapperPIC", 114 SDT_WebAssemblyWrapperPIC>; 115def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow, 116 [SDNPHasChain, SDNPVariadic]>; 117 118//===----------------------------------------------------------------------===// 119// WebAssembly-specific Operands. 120//===----------------------------------------------------------------------===// 121 122// Default Operand has AsmOperandClass "Imm" which is for integers (and 123// symbols), so specialize one for floats: 124def FPImmAsmOperand : AsmOperandClass { 125 let Name = "FPImm"; 126 let PredicateMethod = "isFPImm"; 127} 128 129class FPOperand<ValueType ty> : Operand<ty> { 130 AsmOperandClass ParserMatchClass = FPImmAsmOperand; 131} 132 133let OperandNamespace = "WebAssembly" in { 134 135let OperandType = "OPERAND_BASIC_BLOCK" in 136def bb_op : Operand<OtherVT>; 137 138let OperandType = "OPERAND_LOCAL" in 139def local_op : Operand<i32>; 140 141let OperandType = "OPERAND_GLOBAL" in 142def global_op : Operand<i32>; 143 144let OperandType = "OPERAND_I32IMM" in 145def i32imm_op : Operand<i32>; 146 147let OperandType = "OPERAND_I64IMM" in 148def i64imm_op : Operand<i64>; 149 150let OperandType = "OPERAND_F32IMM" in 151def f32imm_op : FPOperand<f32>; 152 153let OperandType = "OPERAND_F64IMM" in 154def f64imm_op : FPOperand<f64>; 155 156let OperandType = "OPERAND_VEC_I8IMM" in 157def vec_i8imm_op : Operand<i32>; 158 159let OperandType = "OPERAND_VEC_I16IMM" in 160def vec_i16imm_op : Operand<i32>; 161 162let OperandType = "OPERAND_VEC_I32IMM" in 163def vec_i32imm_op : Operand<i32>; 164 165let OperandType = "OPERAND_VEC_I64IMM" in 166def vec_i64imm_op : Operand<i64>; 167 168let OperandType = "OPERAND_FUNCTION32" in 169def function32_op : Operand<i32>; 170 171let OperandType = "OPERAND_OFFSET32" in 172def offset32_op : Operand<i32>; 173 174let OperandType = "OPERAND_P2ALIGN" in { 175def P2Align : Operand<i32> { 176 let PrintMethod = "printWebAssemblyP2AlignOperand"; 177} 178 179let OperandType = "OPERAND_EVENT" in 180def event_op : Operand<i32>; 181 182} // OperandType = "OPERAND_P2ALIGN" 183 184let OperandType = "OPERAND_SIGNATURE" in 185def Signature : Operand<i32> { 186 let PrintMethod = "printWebAssemblySignatureOperand"; 187} 188 189let OperandType = "OPERAND_TYPEINDEX" in 190def TypeIndex : Operand<i32>; 191 192} // OperandNamespace = "WebAssembly" 193 194//===----------------------------------------------------------------------===// 195// WebAssembly Register to Stack instruction mapping 196//===----------------------------------------------------------------------===// 197 198class StackRel; 199def getStackOpcode : InstrMapping { 200 let FilterClass = "StackRel"; 201 let RowFields = ["BaseName"]; 202 let ColFields = ["StackBased"]; 203 let KeyCol = ["false"]; 204 let ValueCols = [["true"]]; 205} 206 207//===----------------------------------------------------------------------===// 208// WebAssembly Instruction Format Definitions. 209//===----------------------------------------------------------------------===// 210 211include "WebAssemblyInstrFormats.td" 212 213//===----------------------------------------------------------------------===// 214// Additional instructions. 215//===----------------------------------------------------------------------===// 216 217multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> { 218 let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>, 219 Uses = [ARGUMENTS] in 220 defm ARGUMENT_#vt : 221 I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno), 222 [(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>; 223} 224defm "": ARGUMENT<I32, i32>; 225defm "": ARGUMENT<I64, i64>; 226defm "": ARGUMENT<F32, f32>; 227defm "": ARGUMENT<F64, f64>; 228defm "": ARGUMENT<EXNREF, exnref>; 229 230// local.get and local.set are not generated by instruction selection; they 231// are implied by virtual register uses and defs. 232multiclass LOCAL<WebAssemblyRegClass vt> { 233 let hasSideEffects = 0 in { 234 // COPY is not an actual instruction in wasm, but since we allow local.get and 235 // local.set to be implicit during most of codegen, we can have a COPY which 236 // is actually a no-op because all the work is done in the implied local.get 237 // and local.set. COPYs are eliminated (and replaced with 238 // local.get/local.set) in the ExplicitLocals pass. 239 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 240 defm COPY_#vt : I<(outs vt:$res), (ins vt:$src), (outs), (ins), [], 241 "local.copy\t$res, $src", "local.copy">; 242 243 // TEE is similar to COPY, but writes two copies of its result. Typically 244 // this would be used to stackify one result and write the other result to a 245 // local. 246 let isAsCheapAsAMove = 1, isCodeGenOnly = 1 in 247 defm TEE_#vt : I<(outs vt:$res, vt:$also), (ins vt:$src), (outs), (ins), [], 248 "local.tee\t$res, $also, $src", "local.tee">; 249 250 // This is the actual local.get instruction in wasm. These are made explicit 251 // by the ExplicitLocals pass. It has mayLoad because it reads from a wasm 252 // local, which is a side effect not otherwise modeled in LLVM. 253 let mayLoad = 1, isAsCheapAsAMove = 1 in 254 defm LOCAL_GET_#vt : I<(outs vt:$res), (ins local_op:$local), 255 (outs), (ins local_op:$local), [], 256 "local.get\t$res, $local", "local.get\t$local", 0x20>; 257 258 // This is the actual local.set instruction in wasm. These are made explicit 259 // by the ExplicitLocals pass. It has mayStore because it writes to a wasm 260 // local, which is a side effect not otherwise modeled in LLVM. 261 let mayStore = 1, isAsCheapAsAMove = 1 in 262 defm LOCAL_SET_#vt : I<(outs), (ins local_op:$local, vt:$src), 263 (outs), (ins local_op:$local), [], 264 "local.set\t$local, $src", "local.set\t$local", 0x21>; 265 266 // This is the actual local.tee instruction in wasm. TEEs are turned into 267 // LOCAL_TEEs by the ExplicitLocals pass. It has mayStore for the same reason 268 // as LOCAL_SET. 269 let mayStore = 1, isAsCheapAsAMove = 1 in 270 defm LOCAL_TEE_#vt : I<(outs vt:$res), (ins local_op:$local, vt:$src), 271 (outs), (ins local_op:$local), [], 272 "local.tee\t$res, $local, $src", "local.tee\t$local", 273 0x22>; 274 275 // Unused values must be dropped in some contexts. 276 defm DROP_#vt : I<(outs), (ins vt:$src), (outs), (ins), [], 277 "drop\t$src", "drop", 0x1a>; 278 279 let mayLoad = 1 in 280 defm GLOBAL_GET_#vt : I<(outs vt:$res), (ins global_op:$local), 281 (outs), (ins global_op:$local), [], 282 "global.get\t$res, $local", "global.get\t$local", 283 0x23>; 284 285 let mayStore = 1 in 286 defm GLOBAL_SET_#vt : I<(outs), (ins global_op:$local, vt:$src), 287 (outs), (ins global_op:$local), [], 288 "global.set\t$local, $src", "global.set\t$local", 289 0x24>; 290 291} // hasSideEffects = 0 292} 293defm "" : LOCAL<I32>; 294defm "" : LOCAL<I64>; 295defm "" : LOCAL<F32>; 296defm "" : LOCAL<F64>; 297defm "" : LOCAL<V128>, Requires<[HasSIMD128]>; 298defm "" : LOCAL<EXNREF>, Requires<[HasExceptionHandling]>; 299 300let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in { 301defm CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm), 302 (outs), (ins i32imm_op:$imm), 303 [(set I32:$res, imm:$imm)], 304 "i32.const\t$res, $imm", "i32.const\t$imm", 0x41>; 305defm CONST_I64 : I<(outs I64:$res), (ins i64imm_op:$imm), 306 (outs), (ins i64imm_op:$imm), 307 [(set I64:$res, imm:$imm)], 308 "i64.const\t$res, $imm", "i64.const\t$imm", 0x42>; 309defm CONST_F32 : I<(outs F32:$res), (ins f32imm_op:$imm), 310 (outs), (ins f32imm_op:$imm), 311 [(set F32:$res, fpimm:$imm)], 312 "f32.const\t$res, $imm", "f32.const\t$imm", 0x43>; 313defm CONST_F64 : I<(outs F64:$res), (ins f64imm_op:$imm), 314 (outs), (ins f64imm_op:$imm), 315 [(set F64:$res, fpimm:$imm)], 316 "f64.const\t$res, $imm", "f64.const\t$imm", 0x44>; 317} // isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 318 319def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 320 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsNotPIC]>; 321 322def : Pat<(i32 (WebAssemblywrapper tglobaladdr:$addr)), 323 (GLOBAL_GET_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 324 325def : Pat<(i32 (WebAssemblywrapperPIC tglobaladdr:$addr)), 326 (CONST_I32 tglobaladdr:$addr)>, Requires<[IsPIC]>; 327 328def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 329 (GLOBAL_GET_I32 texternalsym:$addr)>, Requires<[IsPIC]>; 330 331def : Pat<(i32 (WebAssemblywrapper texternalsym:$addr)), 332 (CONST_I32 texternalsym:$addr)>, Requires<[IsNotPIC]>; 333 334def : Pat<(i32 (WebAssemblywrapper mcsym:$sym)), (CONST_I32 mcsym:$sym)>; 335def : Pat<(i64 (WebAssemblywrapper mcsym:$sym)), (CONST_I64 mcsym:$sym)>; 336 337//===----------------------------------------------------------------------===// 338// Additional sets of instructions. 339//===----------------------------------------------------------------------===// 340 341include "WebAssemblyInstrMemory.td" 342include "WebAssemblyInstrCall.td" 343include "WebAssemblyInstrControl.td" 344include "WebAssemblyInstrInteger.td" 345include "WebAssemblyInstrConv.td" 346include "WebAssemblyInstrFloat.td" 347include "WebAssemblyInstrAtomics.td" 348include "WebAssemblyInstrSIMD.td" 349include "WebAssemblyInstrRef.td" 350include "WebAssemblyInstrBulkMemory.td" 351