10b57cec5SDimitry Andric //=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=// 20b57cec5SDimitry Andric // 30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric // 70b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric /// 90b57cec5SDimitry Andric /// \file 100b57cec5SDimitry Andric /// This file contains the WebAssembly implementation of the 110b57cec5SDimitry Andric /// TargetInstrInfo class. 120b57cec5SDimitry Andric /// 130b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 160b57cec5SDimitry Andric #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 170b57cec5SDimitry Andric 180b57cec5SDimitry Andric #include "WebAssemblyRegisterInfo.h" 190b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 220b57cec5SDimitry Andric #include "WebAssemblyGenInstrInfo.inc" 230b57cec5SDimitry Andric 240b57cec5SDimitry Andric #define GET_INSTRINFO_OPERAND_ENUM 250b57cec5SDimitry Andric #include "WebAssemblyGenInstrInfo.inc" 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric namespace llvm { 280b57cec5SDimitry Andric 290b57cec5SDimitry Andric namespace WebAssembly { 300b57cec5SDimitry Andric 310b57cec5SDimitry Andric int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 320b57cec5SDimitry Andric 330b57cec5SDimitry Andric } 340b57cec5SDimitry Andric 350b57cec5SDimitry Andric class WebAssemblySubtarget; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andric class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo { 380b57cec5SDimitry Andric const WebAssemblyRegisterInfo RI; 390b57cec5SDimitry Andric 400b57cec5SDimitry Andric public: 410b57cec5SDimitry Andric explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI); 420b57cec5SDimitry Andric 430b57cec5SDimitry Andric const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; } 440b57cec5SDimitry Andric 450b57cec5SDimitry Andric bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 46*8bcb0991SDimitry Andric AAResults *AA) const override; 470b57cec5SDimitry Andric 480b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 490b57cec5SDimitry Andric const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 500b57cec5SDimitry Andric bool KillSrc) const override; 510b57cec5SDimitry Andric MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 520b57cec5SDimitry Andric unsigned OpIdx1, 530b57cec5SDimitry Andric unsigned OpIdx2) const override; 540b57cec5SDimitry Andric 550b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 560b57cec5SDimitry Andric MachineBasicBlock *&FBB, 570b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 580b57cec5SDimitry Andric bool AllowModify = false) const override; 590b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 600b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 610b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 620b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 630b57cec5SDimitry Andric const DebugLoc &DL, 640b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 650b57cec5SDimitry Andric bool 660b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 670b57cec5SDimitry Andric }; 680b57cec5SDimitry Andric 690b57cec5SDimitry Andric } // end namespace llvm 700b57cec5SDimitry Andric 710b57cec5SDimitry Andric #endif 72