1*0b57cec5SDimitry Andric //=- WebAssemblyInstrInfo.h - WebAssembly Instruction Information -*- C++ -*-=// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric /// 9*0b57cec5SDimitry Andric /// \file 10*0b57cec5SDimitry Andric /// This file contains the WebAssembly implementation of the 11*0b57cec5SDimitry Andric /// TargetInstrInfo class. 12*0b57cec5SDimitry Andric /// 13*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 16*0b57cec5SDimitry Andric #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYINSTRINFO_H 17*0b57cec5SDimitry Andric 18*0b57cec5SDimitry Andric #include "WebAssemblyRegisterInfo.h" 19*0b57cec5SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric #define GET_INSTRINFO_HEADER 22*0b57cec5SDimitry Andric #include "WebAssemblyGenInstrInfo.inc" 23*0b57cec5SDimitry Andric 24*0b57cec5SDimitry Andric #define GET_INSTRINFO_OPERAND_ENUM 25*0b57cec5SDimitry Andric #include "WebAssemblyGenInstrInfo.inc" 26*0b57cec5SDimitry Andric 27*0b57cec5SDimitry Andric namespace llvm { 28*0b57cec5SDimitry Andric 29*0b57cec5SDimitry Andric namespace WebAssembly { 30*0b57cec5SDimitry Andric 31*0b57cec5SDimitry Andric int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex); 32*0b57cec5SDimitry Andric 33*0b57cec5SDimitry Andric } 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric class WebAssemblySubtarget; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andric class WebAssemblyInstrInfo final : public WebAssemblyGenInstrInfo { 38*0b57cec5SDimitry Andric const WebAssemblyRegisterInfo RI; 39*0b57cec5SDimitry Andric 40*0b57cec5SDimitry Andric public: 41*0b57cec5SDimitry Andric explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI); 42*0b57cec5SDimitry Andric 43*0b57cec5SDimitry Andric const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; } 44*0b57cec5SDimitry Andric 45*0b57cec5SDimitry Andric bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 46*0b57cec5SDimitry Andric AliasAnalysis *AA) const override; 47*0b57cec5SDimitry Andric 48*0b57cec5SDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 49*0b57cec5SDimitry Andric const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, 50*0b57cec5SDimitry Andric bool KillSrc) const override; 51*0b57cec5SDimitry Andric MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 52*0b57cec5SDimitry Andric unsigned OpIdx1, 53*0b57cec5SDimitry Andric unsigned OpIdx2) const override; 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 56*0b57cec5SDimitry Andric MachineBasicBlock *&FBB, 57*0b57cec5SDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 58*0b57cec5SDimitry Andric bool AllowModify = false) const override; 59*0b57cec5SDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 60*0b57cec5SDimitry Andric int *BytesRemoved = nullptr) const override; 61*0b57cec5SDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 62*0b57cec5SDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 63*0b57cec5SDimitry Andric const DebugLoc &DL, 64*0b57cec5SDimitry Andric int *BytesAdded = nullptr) const override; 65*0b57cec5SDimitry Andric bool 66*0b57cec5SDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 67*0b57cec5SDimitry Andric }; 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric } // end namespace llvm 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andric #endif 72