xref: /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp (revision 0d8fe2373503aeac48492f28073049a8bfa4feb5)
1 //===-- WebAssemblyInstrInfo.cpp - WebAssembly Instruction Information ----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file contains the WebAssembly implementation of the
11 /// TargetInstrInfo class.
12 ///
13 //===----------------------------------------------------------------------===//
14 
15 #include "WebAssemblyInstrInfo.h"
16 #include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
17 #include "WebAssembly.h"
18 #include "WebAssemblyMachineFunctionInfo.h"
19 #include "WebAssemblySubtarget.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 using namespace llvm;
25 
26 #define DEBUG_TYPE "wasm-instr-info"
27 
28 #define GET_INSTRINFO_CTOR_DTOR
29 #include "WebAssemblyGenInstrInfo.inc"
30 
31 // defines WebAssembly::getNamedOperandIdx
32 #define GET_INSTRINFO_NAMED_OPS
33 #include "WebAssemblyGenInstrInfo.inc"
34 
35 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
36     : WebAssemblyGenInstrInfo(WebAssembly::ADJCALLSTACKDOWN,
37                               WebAssembly::ADJCALLSTACKUP,
38                               WebAssembly::CATCHRET),
39       RI(STI.getTargetTriple()) {}
40 
41 bool WebAssemblyInstrInfo::isReallyTriviallyReMaterializable(
42     const MachineInstr &MI, AAResults *AA) const {
43   switch (MI.getOpcode()) {
44   case WebAssembly::CONST_I32:
45   case WebAssembly::CONST_I64:
46   case WebAssembly::CONST_F32:
47   case WebAssembly::CONST_F64:
48     // isReallyTriviallyReMaterializableGeneric misses these because of the
49     // ARGUMENTS implicit def, so we manualy override it here.
50     return true;
51   default:
52     return false;
53   }
54 }
55 
56 void WebAssemblyInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
57                                        MachineBasicBlock::iterator I,
58                                        const DebugLoc &DL, MCRegister DestReg,
59                                        MCRegister SrcReg, bool KillSrc) const {
60   // This method is called by post-RA expansion, which expects only pregs to
61   // exist. However we need to handle both here.
62   auto &MRI = MBB.getParent()->getRegInfo();
63   const TargetRegisterClass *RC =
64       Register::isVirtualRegister(DestReg)
65           ? MRI.getRegClass(DestReg)
66           : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg);
67 
68   unsigned CopyOpcode;
69   if (RC == &WebAssembly::I32RegClass)
70     CopyOpcode = WebAssembly::COPY_I32;
71   else if (RC == &WebAssembly::I64RegClass)
72     CopyOpcode = WebAssembly::COPY_I64;
73   else if (RC == &WebAssembly::F32RegClass)
74     CopyOpcode = WebAssembly::COPY_F32;
75   else if (RC == &WebAssembly::F64RegClass)
76     CopyOpcode = WebAssembly::COPY_F64;
77   else if (RC == &WebAssembly::V128RegClass)
78     CopyOpcode = WebAssembly::COPY_V128;
79   else if (RC == &WebAssembly::FUNCREFRegClass)
80     CopyOpcode = WebAssembly::COPY_FUNCREF;
81   else if (RC == &WebAssembly::EXTERNREFRegClass)
82     CopyOpcode = WebAssembly::COPY_EXTERNREF;
83   else
84     llvm_unreachable("Unexpected register class");
85 
86   BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
87       .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
88 }
89 
90 MachineInstr *WebAssemblyInstrInfo::commuteInstructionImpl(
91     MachineInstr &MI, bool NewMI, unsigned OpIdx1, unsigned OpIdx2) const {
92   // If the operands are stackified, we can't reorder them.
93   WebAssemblyFunctionInfo &MFI =
94       *MI.getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
95   if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
96       MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
97     return nullptr;
98 
99   // Otherwise use the default implementation.
100   return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
101 }
102 
103 // Branch analysis.
104 bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
105                                          MachineBasicBlock *&TBB,
106                                          MachineBasicBlock *&FBB,
107                                          SmallVectorImpl<MachineOperand> &Cond,
108                                          bool /*AllowModify*/) const {
109   const auto &MFI = *MBB.getParent()->getInfo<WebAssemblyFunctionInfo>();
110   // WebAssembly has control flow that doesn't have explicit branches or direct
111   // fallthrough (e.g. try/catch), which can't be modeled by analyzeBranch. It
112   // is created after CFGStackify.
113   if (MFI.isCFGStackified())
114     return true;
115 
116   bool HaveCond = false;
117   for (MachineInstr &MI : MBB.terminators()) {
118     switch (MI.getOpcode()) {
119     default:
120       // Unhandled instruction; bail out.
121       return true;
122     case WebAssembly::BR_IF:
123       if (HaveCond)
124         return true;
125       Cond.push_back(MachineOperand::CreateImm(true));
126       Cond.push_back(MI.getOperand(1));
127       TBB = MI.getOperand(0).getMBB();
128       HaveCond = true;
129       break;
130     case WebAssembly::BR_UNLESS:
131       if (HaveCond)
132         return true;
133       Cond.push_back(MachineOperand::CreateImm(false));
134       Cond.push_back(MI.getOperand(1));
135       TBB = MI.getOperand(0).getMBB();
136       HaveCond = true;
137       break;
138     case WebAssembly::BR:
139       if (!HaveCond)
140         TBB = MI.getOperand(0).getMBB();
141       else
142         FBB = MI.getOperand(0).getMBB();
143       break;
144     }
145     if (MI.isBarrier())
146       break;
147   }
148 
149   return false;
150 }
151 
152 unsigned WebAssemblyInstrInfo::removeBranch(MachineBasicBlock &MBB,
153                                             int *BytesRemoved) const {
154   assert(!BytesRemoved && "code size not handled");
155 
156   MachineBasicBlock::instr_iterator I = MBB.instr_end();
157   unsigned Count = 0;
158 
159   while (I != MBB.instr_begin()) {
160     --I;
161     if (I->isDebugInstr())
162       continue;
163     if (!I->isTerminator())
164       break;
165     // Remove the branch.
166     I->eraseFromParent();
167     I = MBB.instr_end();
168     ++Count;
169   }
170 
171   return Count;
172 }
173 
174 unsigned WebAssemblyInstrInfo::insertBranch(
175     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
176     ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
177   assert(!BytesAdded && "code size not handled");
178 
179   if (Cond.empty()) {
180     if (!TBB)
181       return 0;
182 
183     BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
184     return 1;
185   }
186 
187   assert(Cond.size() == 2 && "Expected a flag and a successor block");
188 
189   if (Cond[0].getImm())
190     BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
191   else
192     BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
193   if (!FBB)
194     return 1;
195 
196   BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
197   return 2;
198 }
199 
200 bool WebAssemblyInstrInfo::reverseBranchCondition(
201     SmallVectorImpl<MachineOperand> &Cond) const {
202   assert(Cond.size() == 2 && "Expected a flag and a condition expression");
203   Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
204   return false;
205 }
206 
207 ArrayRef<std::pair<int, const char *>>
208 WebAssemblyInstrInfo::getSerializableTargetIndices() const {
209   static const std::pair<int, const char *> TargetIndices[] = {
210       {WebAssembly::TI_LOCAL, "wasm-local"},
211       {WebAssembly::TI_GLOBAL_FIXED, "wasm-global-fixed"},
212       {WebAssembly::TI_OPERAND_STACK, "wasm-operand-stack"},
213       {WebAssembly::TI_GLOBAL_RELOC, "wasm-global-reloc"}};
214   return makeArrayRef(TargetIndices);
215 }
216