1//=- WebAssemblyInstrFormats.td - WebAssembly Instr. Formats -*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// 9/// \file 10/// WebAssembly instruction format definitions. 11/// 12//===----------------------------------------------------------------------===// 13 14// WebAssembly Instruction Format. 15// We instantiate 2 of these for every actual instruction (register based 16// and stack based), see below. 17class WebAssemblyInst<bits<32> inst, string asmstr, string stack> : StackRel, 18 Instruction { 19 bits<32> Inst = inst; // Instruction encoding. 20 string StackBased = stack; 21 string BaseName = NAME; 22 let Namespace = "WebAssembly"; 23 let Pattern = []; 24 let AsmString = asmstr; 25 // When there are multiple instructions that map to the same encoding (in 26 // e.g. the disassembler use case) prefer the one where IsCanonical == 1. 27 bit IsCanonical = 0; 28} 29 30// Normal instructions. Default instantiation of a WebAssemblyInst. 31class NI<dag oops, dag iops, list<dag> pattern, string stack, 32 string asmstr = "", bits<32> inst = -1> 33 : WebAssemblyInst<inst, asmstr, stack> { 34 dag OutOperandList = oops; 35 dag InOperandList = iops; 36 let Pattern = pattern; 37 let Defs = [ARGUMENTS]; 38} 39 40// Generates both register and stack based versions of one actual instruction. 41// We have 2 sets of operands (oops & iops) for the register and stack 42// based version of this instruction, as well as the corresponding asmstr. 43// The register versions have virtual-register operands which correspond to wasm 44// locals or stack locations. Each use and def of the register corresponds to an 45// implicit local.get / local.set or access of stack operands in wasm. These 46// instructions are used for ISel and all MI passes. The stack versions of the 47// instructions do not have register operands (they implicitly operate on the 48// stack), and local.gets and local.sets are explicit. The register instructions 49// are converted to their corresponding stack instructions before lowering to 50// MC. 51// Every instruction should want to be based on this multi-class to guarantee 52// there is always an equivalent pair of instructions. 53multiclass I<dag oops_r, dag iops_r, dag oops_s, dag iops_s, 54 list<dag> pattern_r, string asmstr_r = "", string asmstr_s = "", 55 bits<32> inst = -1> { 56 let isCodeGenOnly = 1 in 57 def "" : NI<oops_r, iops_r, pattern_r, "false", asmstr_r, inst>; 58 let BaseName = NAME in 59 def _S : NI<oops_s, iops_s, [], "true", asmstr_s, inst>; 60} 61 62// For instructions that have no register ops, so both sets are the same. 63multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "", 64 bits<32> inst = -1> { 65 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>; 66} 67