10b57cec5SDimitry Andric//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric/// 90b57cec5SDimitry Andric/// \file 100b57cec5SDimitry Andric/// This is a target description file for the WebAssembly architecture, 110b57cec5SDimitry Andric/// which is also known as "wasm". 120b57cec5SDimitry Andric/// 130b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 140b57cec5SDimitry Andric 150b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 160b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 170b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 180b57cec5SDimitry Andric 190b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 200b57cec5SDimitry Andric 210b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 220b57cec5SDimitry Andric// WebAssembly Subtarget features. 230b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 240b57cec5SDimitry Andric 250b57cec5SDimitry Andricdef FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128", 260b57cec5SDimitry Andric "Enable 128-bit SIMD">; 270b57cec5SDimitry Andric 280b57cec5SDimitry Andricdef FeatureUnimplementedSIMD128 : 290b57cec5SDimitry Andric SubtargetFeature<"unimplemented-simd128", 300b57cec5SDimitry Andric "SIMDLevel", "UnimplementedSIMD128", 310b57cec5SDimitry Andric "Enable 128-bit SIMD not yet implemented in engines", 320b57cec5SDimitry Andric [FeatureSIMD128]>; 330b57cec5SDimitry Andric 340b57cec5SDimitry Andricdef FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", 350b57cec5SDimitry Andric "Enable Atomics">; 360b57cec5SDimitry Andric 370b57cec5SDimitry Andricdef FeatureNontrappingFPToInt : 380b57cec5SDimitry Andric SubtargetFeature<"nontrapping-fptoint", 390b57cec5SDimitry Andric "HasNontrappingFPToInt", "true", 400b57cec5SDimitry Andric "Enable non-trapping float-to-int conversion operators">; 410b57cec5SDimitry Andric 420b57cec5SDimitry Andricdef FeatureSignExt : 430b57cec5SDimitry Andric SubtargetFeature<"sign-ext", 440b57cec5SDimitry Andric "HasSignExt", "true", 450b57cec5SDimitry Andric "Enable sign extension operators">; 460b57cec5SDimitry Andric 470b57cec5SDimitry Andricdef FeatureTailCall : 480b57cec5SDimitry Andric SubtargetFeature<"tail-call", 490b57cec5SDimitry Andric "HasTailCall", "true", 500b57cec5SDimitry Andric "Enable tail call instructions">; 510b57cec5SDimitry Andric 520b57cec5SDimitry Andricdef FeatureExceptionHandling : 530b57cec5SDimitry Andric SubtargetFeature<"exception-handling", "HasExceptionHandling", "true", 540b57cec5SDimitry Andric "Enable Wasm exception handling">; 550b57cec5SDimitry Andric 560b57cec5SDimitry Andricdef FeatureBulkMemory : 570b57cec5SDimitry Andric SubtargetFeature<"bulk-memory", "HasBulkMemory", "true", 580b57cec5SDimitry Andric "Enable bulk memory operations">; 590b57cec5SDimitry Andric 600b57cec5SDimitry Andricdef FeatureMultivalue : 610b57cec5SDimitry Andric SubtargetFeature<"multivalue", 620b57cec5SDimitry Andric "HasMultivalue", "true", 630b57cec5SDimitry Andric "Enable multivalue blocks, instructions, and functions">; 640b57cec5SDimitry Andric 650b57cec5SDimitry Andricdef FeatureMutableGlobals : 660b57cec5SDimitry Andric SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true", 670b57cec5SDimitry Andric "Enable mutable globals">; 680b57cec5SDimitry Andric 69*5ffd83dbSDimitry Andricdef FeatureReferenceTypes : 70*5ffd83dbSDimitry Andric SubtargetFeature<"reference-types", "HasReferenceTypes", "true", 71*5ffd83dbSDimitry Andric "Enable reference types">; 72*5ffd83dbSDimitry Andric 730b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 740b57cec5SDimitry Andric// Architectures. 750b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 760b57cec5SDimitry Andric 770b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 780b57cec5SDimitry Andric// Register File Description 790b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 800b57cec5SDimitry Andric 810b57cec5SDimitry Andricinclude "WebAssemblyRegisterInfo.td" 820b57cec5SDimitry Andric 830b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 840b57cec5SDimitry Andric// Instruction Descriptions 850b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 860b57cec5SDimitry Andric 870b57cec5SDimitry Andricinclude "WebAssemblyInstrInfo.td" 880b57cec5SDimitry Andric 890b57cec5SDimitry Andricdef WebAssemblyInstrInfo : InstrInfo; 900b57cec5SDimitry Andric 910b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 920b57cec5SDimitry Andric// WebAssembly Processors supported. 930b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 940b57cec5SDimitry Andric 950b57cec5SDimitry Andric// Minimal Viable Product. 960b57cec5SDimitry Andricdef : ProcessorModel<"mvp", NoSchedModel, []>; 970b57cec5SDimitry Andric 980b57cec5SDimitry Andric// Generic processor: latest stable version. 990b57cec5SDimitry Andricdef : ProcessorModel<"generic", NoSchedModel, []>; 1000b57cec5SDimitry Andric 1010b57cec5SDimitry Andric// Latest and greatest experimental version of WebAssembly. Bugs included! 1020b57cec5SDimitry Andricdef : ProcessorModel<"bleeding-edge", NoSchedModel, 1030b57cec5SDimitry Andric [FeatureSIMD128, FeatureAtomics, 1040b57cec5SDimitry Andric FeatureNontrappingFPToInt, FeatureSignExt, 105*5ffd83dbSDimitry Andric FeatureMutableGlobals, FeatureBulkMemory, 106*5ffd83dbSDimitry Andric FeatureTailCall]>; 1070b57cec5SDimitry Andric 1080b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1090b57cec5SDimitry Andric// Target Declaration 1100b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 1110b57cec5SDimitry Andric 1120b57cec5SDimitry Andricdef WebAssemblyAsmParser : AsmParser { 1130b57cec5SDimitry Andric // The physical register names are not in the binary format or asm text 1140b57cec5SDimitry Andric let ShouldEmitMatchRegisterName = 0; 1150b57cec5SDimitry Andric} 1160b57cec5SDimitry Andric 1170b57cec5SDimitry Andricdef WebAssemblyAsmWriter : AsmWriter { 1180b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 1190b57cec5SDimitry Andric int PassSubtarget = 0; 1200b57cec5SDimitry Andric int Variant = 0; 1210b57cec5SDimitry Andric bit isMCAsmWriter = 1; 1220b57cec5SDimitry Andric} 1230b57cec5SDimitry Andric 1240b57cec5SDimitry Andricdef WebAssembly : Target { 1250b57cec5SDimitry Andric let InstructionSet = WebAssemblyInstrInfo; 1260b57cec5SDimitry Andric let AssemblyParsers = [WebAssemblyAsmParser]; 1270b57cec5SDimitry Andric let AssemblyWriters = [WebAssemblyAsmWriter]; 1280b57cec5SDimitry Andric} 129