1*0b57cec5SDimitry Andric//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric/// 9*0b57cec5SDimitry Andric/// \file 10*0b57cec5SDimitry Andric/// This is a target description file for the WebAssembly architecture, 11*0b57cec5SDimitry Andric/// which is also known as "wasm". 12*0b57cec5SDimitry Andric/// 13*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 16*0b57cec5SDimitry Andric// Target-independent interfaces which we are implementing 17*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 18*0b57cec5SDimitry Andric 19*0b57cec5SDimitry Andricinclude "llvm/Target/Target.td" 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 22*0b57cec5SDimitry Andric// WebAssembly Subtarget features. 23*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 24*0b57cec5SDimitry Andric 25*0b57cec5SDimitry Andricdef FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128", 26*0b57cec5SDimitry Andric "Enable 128-bit SIMD">; 27*0b57cec5SDimitry Andric 28*0b57cec5SDimitry Andricdef FeatureUnimplementedSIMD128 : 29*0b57cec5SDimitry Andric SubtargetFeature<"unimplemented-simd128", 30*0b57cec5SDimitry Andric "SIMDLevel", "UnimplementedSIMD128", 31*0b57cec5SDimitry Andric "Enable 128-bit SIMD not yet implemented in engines", 32*0b57cec5SDimitry Andric [FeatureSIMD128]>; 33*0b57cec5SDimitry Andric 34*0b57cec5SDimitry Andricdef FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", 35*0b57cec5SDimitry Andric "Enable Atomics">; 36*0b57cec5SDimitry Andric 37*0b57cec5SDimitry Andricdef FeatureNontrappingFPToInt : 38*0b57cec5SDimitry Andric SubtargetFeature<"nontrapping-fptoint", 39*0b57cec5SDimitry Andric "HasNontrappingFPToInt", "true", 40*0b57cec5SDimitry Andric "Enable non-trapping float-to-int conversion operators">; 41*0b57cec5SDimitry Andric 42*0b57cec5SDimitry Andricdef FeatureSignExt : 43*0b57cec5SDimitry Andric SubtargetFeature<"sign-ext", 44*0b57cec5SDimitry Andric "HasSignExt", "true", 45*0b57cec5SDimitry Andric "Enable sign extension operators">; 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andricdef FeatureTailCall : 48*0b57cec5SDimitry Andric SubtargetFeature<"tail-call", 49*0b57cec5SDimitry Andric "HasTailCall", "true", 50*0b57cec5SDimitry Andric "Enable tail call instructions">; 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andricdef FeatureExceptionHandling : 53*0b57cec5SDimitry Andric SubtargetFeature<"exception-handling", "HasExceptionHandling", "true", 54*0b57cec5SDimitry Andric "Enable Wasm exception handling">; 55*0b57cec5SDimitry Andric 56*0b57cec5SDimitry Andricdef FeatureBulkMemory : 57*0b57cec5SDimitry Andric SubtargetFeature<"bulk-memory", "HasBulkMemory", "true", 58*0b57cec5SDimitry Andric "Enable bulk memory operations">; 59*0b57cec5SDimitry Andric 60*0b57cec5SDimitry Andricdef FeatureMultivalue : 61*0b57cec5SDimitry Andric SubtargetFeature<"multivalue", 62*0b57cec5SDimitry Andric "HasMultivalue", "true", 63*0b57cec5SDimitry Andric "Enable multivalue blocks, instructions, and functions">; 64*0b57cec5SDimitry Andric 65*0b57cec5SDimitry Andricdef FeatureMutableGlobals : 66*0b57cec5SDimitry Andric SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true", 67*0b57cec5SDimitry Andric "Enable mutable globals">; 68*0b57cec5SDimitry Andric 69*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 70*0b57cec5SDimitry Andric// Architectures. 71*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 72*0b57cec5SDimitry Andric 73*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 74*0b57cec5SDimitry Andric// Register File Description 75*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 76*0b57cec5SDimitry Andric 77*0b57cec5SDimitry Andricinclude "WebAssemblyRegisterInfo.td" 78*0b57cec5SDimitry Andric 79*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80*0b57cec5SDimitry Andric// Instruction Descriptions 81*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andricinclude "WebAssemblyInstrInfo.td" 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andricdef WebAssemblyInstrInfo : InstrInfo; 86*0b57cec5SDimitry Andric 87*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 88*0b57cec5SDimitry Andric// WebAssembly Processors supported. 89*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 90*0b57cec5SDimitry Andric 91*0b57cec5SDimitry Andric// Minimal Viable Product. 92*0b57cec5SDimitry Andricdef : ProcessorModel<"mvp", NoSchedModel, []>; 93*0b57cec5SDimitry Andric 94*0b57cec5SDimitry Andric// Generic processor: latest stable version. 95*0b57cec5SDimitry Andricdef : ProcessorModel<"generic", NoSchedModel, []>; 96*0b57cec5SDimitry Andric 97*0b57cec5SDimitry Andric// Latest and greatest experimental version of WebAssembly. Bugs included! 98*0b57cec5SDimitry Andricdef : ProcessorModel<"bleeding-edge", NoSchedModel, 99*0b57cec5SDimitry Andric [FeatureSIMD128, FeatureAtomics, 100*0b57cec5SDimitry Andric FeatureNontrappingFPToInt, FeatureSignExt, 101*0b57cec5SDimitry Andric FeatureMutableGlobals]>; 102*0b57cec5SDimitry Andric 103*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 104*0b57cec5SDimitry Andric// Target Declaration 105*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 106*0b57cec5SDimitry Andric 107*0b57cec5SDimitry Andricdef WebAssemblyAsmParser : AsmParser { 108*0b57cec5SDimitry Andric // The physical register names are not in the binary format or asm text 109*0b57cec5SDimitry Andric let ShouldEmitMatchRegisterName = 0; 110*0b57cec5SDimitry Andric} 111*0b57cec5SDimitry Andric 112*0b57cec5SDimitry Andricdef WebAssemblyAsmWriter : AsmWriter { 113*0b57cec5SDimitry Andric string AsmWriterClassName = "InstPrinter"; 114*0b57cec5SDimitry Andric int PassSubtarget = 0; 115*0b57cec5SDimitry Andric int Variant = 0; 116*0b57cec5SDimitry Andric bit isMCAsmWriter = 1; 117*0b57cec5SDimitry Andric} 118*0b57cec5SDimitry Andric 119*0b57cec5SDimitry Andricdef WebAssembly : Target { 120*0b57cec5SDimitry Andric let InstructionSet = WebAssemblyInstrInfo; 121*0b57cec5SDimitry Andric let AssemblyParsers = [WebAssemblyAsmParser]; 122*0b57cec5SDimitry Andric let AssemblyWriters = [WebAssemblyAsmWriter]; 123*0b57cec5SDimitry Andric} 124