1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// 9 /// \file 10 /// This file provides WebAssembly-specific target descriptions. 11 /// 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H 16 17 #include "../WebAssemblySubtarget.h" 18 #include "llvm/BinaryFormat/Wasm.h" 19 #include "llvm/MC/MCInstrDesc.h" 20 #include "llvm/Support/DataTypes.h" 21 #include <memory> 22 23 namespace llvm { 24 25 class MCAsmBackend; 26 class MCCodeEmitter; 27 class MCInstrInfo; 28 class MCObjectTargetWriter; 29 class MVT; 30 class Triple; 31 32 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII); 33 34 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT); 35 36 std::unique_ptr<MCObjectTargetWriter> 37 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten); 38 39 namespace WebAssembly { 40 enum OperandType { 41 /// Basic block label in a branch construct. 42 OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET, 43 /// Local index. 44 OPERAND_LOCAL, 45 /// Global index. 46 OPERAND_GLOBAL, 47 /// 32-bit integer immediates. 48 OPERAND_I32IMM, 49 /// 64-bit integer immediates. 50 OPERAND_I64IMM, 51 /// 32-bit floating-point immediates. 52 OPERAND_F32IMM, 53 /// 64-bit floating-point immediates. 54 OPERAND_F64IMM, 55 /// 8-bit vector lane immediate 56 OPERAND_VEC_I8IMM, 57 /// 16-bit vector lane immediate 58 OPERAND_VEC_I16IMM, 59 /// 32-bit vector lane immediate 60 OPERAND_VEC_I32IMM, 61 /// 64-bit vector lane immediate 62 OPERAND_VEC_I64IMM, 63 /// 32-bit unsigned function indices. 64 OPERAND_FUNCTION32, 65 /// 32-bit unsigned memory offsets. 66 OPERAND_OFFSET32, 67 /// 64-bit unsigned memory offsets. 68 OPERAND_OFFSET64, 69 /// p2align immediate for load and store address alignment. 70 OPERAND_P2ALIGN, 71 /// signature immediate for block/loop. 72 OPERAND_SIGNATURE, 73 /// type signature immediate for call_indirect. 74 OPERAND_TYPEINDEX, 75 /// Tag index. 76 OPERAND_TAG, 77 /// A list of branch targets for br_list. 78 OPERAND_BRLIST, 79 /// 32-bit unsigned table number. 80 OPERAND_TABLE, 81 /// heap type immediate for ref.null. 82 OPERAND_HEAPTYPE, 83 }; 84 } // end namespace WebAssembly 85 86 namespace WebAssemblyII { 87 88 /// Target Operand Flag enum. 89 enum TOF { 90 MO_NO_FLAG = 0, 91 92 // On a symbol operand this indicates that the immediate is a wasm global 93 // index. The value of the wasm global will be set to the symbol address at 94 // runtime. This adds a level of indirection similar to the GOT on native 95 // platforms. 96 MO_GOT, 97 98 // Same as MO_GOT but the address stored in the global is a TLS address. 99 MO_GOT_TLS, 100 101 // On a symbol operand this indicates that the immediate is the symbol 102 // address relative the __memory_base wasm global. 103 // Only applicable to data symbols. 104 MO_MEMORY_BASE_REL, 105 106 // On a symbol operand this indicates that the immediate is the symbol 107 // address relative the __tls_base wasm global. 108 // Only applicable to data symbols. 109 MO_TLS_BASE_REL, 110 111 // On a symbol operand this indicates that the immediate is the symbol 112 // address relative the __table_base wasm global. 113 // Only applicable to function symbols. 114 MO_TABLE_BASE_REL, 115 }; 116 117 } // end namespace WebAssemblyII 118 119 } // end namespace llvm 120 121 // Defines symbolic names for WebAssembly registers. This defines a mapping from 122 // register name to register number. 123 // 124 #define GET_REGINFO_ENUM 125 #include "WebAssemblyGenRegisterInfo.inc" 126 127 // Defines symbolic names for the WebAssembly instructions. 128 // 129 #define GET_INSTRINFO_ENUM 130 #include "WebAssemblyGenInstrInfo.inc" 131 132 namespace llvm { 133 namespace WebAssembly { 134 135 /// Instruction opcodes emitted via means other than CodeGen. 136 static const unsigned Nop = 0x01; 137 static const unsigned End = 0x0b; 138 139 /// Return the default p2align value for a load or store with the given opcode. 140 inline unsigned GetDefaultP2AlignAny(unsigned Opc) { 141 switch (Opc) { 142 #define WASM_LOAD_STORE(NAME) \ 143 case WebAssembly::NAME##_A32: \ 144 case WebAssembly::NAME##_A64: \ 145 case WebAssembly::NAME##_A32_S: \ 146 case WebAssembly::NAME##_A64_S: 147 WASM_LOAD_STORE(LOAD8_S_I32) 148 WASM_LOAD_STORE(LOAD8_U_I32) 149 WASM_LOAD_STORE(LOAD8_S_I64) 150 WASM_LOAD_STORE(LOAD8_U_I64) 151 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32) 152 WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64) 153 WASM_LOAD_STORE(STORE8_I32) 154 WASM_LOAD_STORE(STORE8_I64) 155 WASM_LOAD_STORE(ATOMIC_STORE8_I32) 156 WASM_LOAD_STORE(ATOMIC_STORE8_I64) 157 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32) 158 WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64) 159 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32) 160 WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64) 161 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32) 162 WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64) 163 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32) 164 WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64) 165 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32) 166 WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64) 167 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32) 168 WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64) 169 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32) 170 WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64) 171 WASM_LOAD_STORE(LOAD8_SPLAT) 172 WASM_LOAD_STORE(LOAD_LANE_I8x16) 173 WASM_LOAD_STORE(STORE_LANE_I8x16) 174 return 0; 175 WASM_LOAD_STORE(LOAD16_S_I32) 176 WASM_LOAD_STORE(LOAD16_U_I32) 177 WASM_LOAD_STORE(LOAD16_S_I64) 178 WASM_LOAD_STORE(LOAD16_U_I64) 179 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32) 180 WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64) 181 WASM_LOAD_STORE(STORE16_I32) 182 WASM_LOAD_STORE(STORE16_I64) 183 WASM_LOAD_STORE(ATOMIC_STORE16_I32) 184 WASM_LOAD_STORE(ATOMIC_STORE16_I64) 185 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32) 186 WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64) 187 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32) 188 WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64) 189 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32) 190 WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64) 191 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32) 192 WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64) 193 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32) 194 WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64) 195 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32) 196 WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64) 197 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32) 198 WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64) 199 WASM_LOAD_STORE(LOAD16_SPLAT) 200 WASM_LOAD_STORE(LOAD_LANE_I16x8) 201 WASM_LOAD_STORE(STORE_LANE_I16x8) 202 return 1; 203 WASM_LOAD_STORE(LOAD_I32) 204 WASM_LOAD_STORE(LOAD_F32) 205 WASM_LOAD_STORE(STORE_I32) 206 WASM_LOAD_STORE(STORE_F32) 207 WASM_LOAD_STORE(LOAD32_S_I64) 208 WASM_LOAD_STORE(LOAD32_U_I64) 209 WASM_LOAD_STORE(STORE32_I64) 210 WASM_LOAD_STORE(ATOMIC_LOAD_I32) 211 WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64) 212 WASM_LOAD_STORE(ATOMIC_STORE_I32) 213 WASM_LOAD_STORE(ATOMIC_STORE32_I64) 214 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32) 215 WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64) 216 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32) 217 WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64) 218 WASM_LOAD_STORE(ATOMIC_RMW_AND_I32) 219 WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64) 220 WASM_LOAD_STORE(ATOMIC_RMW_OR_I32) 221 WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64) 222 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32) 223 WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64) 224 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32) 225 WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64) 226 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32) 227 WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64) 228 WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY) 229 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32) 230 WASM_LOAD_STORE(LOAD32_SPLAT) 231 WASM_LOAD_STORE(LOAD_ZERO_I32x4) 232 WASM_LOAD_STORE(LOAD_LANE_I32x4) 233 WASM_LOAD_STORE(STORE_LANE_I32x4) 234 return 2; 235 WASM_LOAD_STORE(LOAD_I64) 236 WASM_LOAD_STORE(LOAD_F64) 237 WASM_LOAD_STORE(STORE_I64) 238 WASM_LOAD_STORE(STORE_F64) 239 WASM_LOAD_STORE(ATOMIC_LOAD_I64) 240 WASM_LOAD_STORE(ATOMIC_STORE_I64) 241 WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64) 242 WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64) 243 WASM_LOAD_STORE(ATOMIC_RMW_AND_I64) 244 WASM_LOAD_STORE(ATOMIC_RMW_OR_I64) 245 WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64) 246 WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64) 247 WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64) 248 WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64) 249 WASM_LOAD_STORE(LOAD64_SPLAT) 250 WASM_LOAD_STORE(LOAD_EXTEND_S_I16x8) 251 WASM_LOAD_STORE(LOAD_EXTEND_U_I16x8) 252 WASM_LOAD_STORE(LOAD_EXTEND_S_I32x4) 253 WASM_LOAD_STORE(LOAD_EXTEND_U_I32x4) 254 WASM_LOAD_STORE(LOAD_EXTEND_S_I64x2) 255 WASM_LOAD_STORE(LOAD_EXTEND_U_I64x2) 256 WASM_LOAD_STORE(LOAD_ZERO_I64x2) 257 WASM_LOAD_STORE(LOAD_LANE_I64x2) 258 WASM_LOAD_STORE(STORE_LANE_I64x2) 259 return 3; 260 WASM_LOAD_STORE(LOAD_V128) 261 WASM_LOAD_STORE(STORE_V128) 262 return 4; 263 default: 264 return -1; 265 } 266 #undef WASM_LOAD_STORE 267 } 268 269 inline unsigned GetDefaultP2Align(unsigned Opc) { 270 auto Align = GetDefaultP2AlignAny(Opc); 271 if (Align == -1U) { 272 llvm_unreachable("Only loads and stores have p2align values"); 273 } 274 return Align; 275 } 276 277 inline bool isArgument(unsigned Opc) { 278 switch (Opc) { 279 case WebAssembly::ARGUMENT_i32: 280 case WebAssembly::ARGUMENT_i32_S: 281 case WebAssembly::ARGUMENT_i64: 282 case WebAssembly::ARGUMENT_i64_S: 283 case WebAssembly::ARGUMENT_f32: 284 case WebAssembly::ARGUMENT_f32_S: 285 case WebAssembly::ARGUMENT_f64: 286 case WebAssembly::ARGUMENT_f64_S: 287 case WebAssembly::ARGUMENT_v16i8: 288 case WebAssembly::ARGUMENT_v16i8_S: 289 case WebAssembly::ARGUMENT_v8i16: 290 case WebAssembly::ARGUMENT_v8i16_S: 291 case WebAssembly::ARGUMENT_v4i32: 292 case WebAssembly::ARGUMENT_v4i32_S: 293 case WebAssembly::ARGUMENT_v2i64: 294 case WebAssembly::ARGUMENT_v2i64_S: 295 case WebAssembly::ARGUMENT_v4f32: 296 case WebAssembly::ARGUMENT_v4f32_S: 297 case WebAssembly::ARGUMENT_v2f64: 298 case WebAssembly::ARGUMENT_v2f64_S: 299 case WebAssembly::ARGUMENT_funcref: 300 case WebAssembly::ARGUMENT_funcref_S: 301 case WebAssembly::ARGUMENT_externref: 302 case WebAssembly::ARGUMENT_externref_S: 303 return true; 304 default: 305 return false; 306 } 307 } 308 309 inline bool isCopy(unsigned Opc) { 310 switch (Opc) { 311 case WebAssembly::COPY_I32: 312 case WebAssembly::COPY_I32_S: 313 case WebAssembly::COPY_I64: 314 case WebAssembly::COPY_I64_S: 315 case WebAssembly::COPY_F32: 316 case WebAssembly::COPY_F32_S: 317 case WebAssembly::COPY_F64: 318 case WebAssembly::COPY_F64_S: 319 case WebAssembly::COPY_V128: 320 case WebAssembly::COPY_V128_S: 321 case WebAssembly::COPY_FUNCREF: 322 case WebAssembly::COPY_FUNCREF_S: 323 case WebAssembly::COPY_EXTERNREF: 324 case WebAssembly::COPY_EXTERNREF_S: 325 return true; 326 default: 327 return false; 328 } 329 } 330 331 inline bool isTee(unsigned Opc) { 332 switch (Opc) { 333 case WebAssembly::TEE_I32: 334 case WebAssembly::TEE_I32_S: 335 case WebAssembly::TEE_I64: 336 case WebAssembly::TEE_I64_S: 337 case WebAssembly::TEE_F32: 338 case WebAssembly::TEE_F32_S: 339 case WebAssembly::TEE_F64: 340 case WebAssembly::TEE_F64_S: 341 case WebAssembly::TEE_V128: 342 case WebAssembly::TEE_V128_S: 343 case WebAssembly::TEE_FUNCREF: 344 case WebAssembly::TEE_FUNCREF_S: 345 case WebAssembly::TEE_EXTERNREF: 346 case WebAssembly::TEE_EXTERNREF_S: 347 return true; 348 default: 349 return false; 350 } 351 } 352 353 inline bool isCallDirect(unsigned Opc) { 354 switch (Opc) { 355 case WebAssembly::CALL: 356 case WebAssembly::CALL_S: 357 case WebAssembly::RET_CALL: 358 case WebAssembly::RET_CALL_S: 359 return true; 360 default: 361 return false; 362 } 363 } 364 365 inline bool isCallIndirect(unsigned Opc) { 366 switch (Opc) { 367 case WebAssembly::CALL_INDIRECT: 368 case WebAssembly::CALL_INDIRECT_S: 369 case WebAssembly::RET_CALL_INDIRECT: 370 case WebAssembly::RET_CALL_INDIRECT_S: 371 return true; 372 default: 373 return false; 374 } 375 } 376 377 inline bool isBrTable(const MachineInstr &MI) { 378 switch (MI.getOpcode()) { 379 case WebAssembly::BR_TABLE_I32: 380 case WebAssembly::BR_TABLE_I32_S: 381 case WebAssembly::BR_TABLE_I64: 382 case WebAssembly::BR_TABLE_I64_S: 383 return true; 384 default: 385 return false; 386 } 387 } 388 389 inline bool isMarker(unsigned Opc) { 390 switch (Opc) { 391 case WebAssembly::BLOCK: 392 case WebAssembly::BLOCK_S: 393 case WebAssembly::END_BLOCK: 394 case WebAssembly::END_BLOCK_S: 395 case WebAssembly::LOOP: 396 case WebAssembly::LOOP_S: 397 case WebAssembly::END_LOOP: 398 case WebAssembly::END_LOOP_S: 399 case WebAssembly::TRY: 400 case WebAssembly::TRY_S: 401 case WebAssembly::END_TRY: 402 case WebAssembly::END_TRY_S: 403 return true; 404 default: 405 return false; 406 } 407 } 408 409 inline bool isCatch(unsigned Opc) { 410 switch (Opc) { 411 case WebAssembly::CATCH: 412 case WebAssembly::CATCH_S: 413 case WebAssembly::CATCH_ALL: 414 case WebAssembly::CATCH_ALL_S: 415 return true; 416 default: 417 return false; 418 } 419 } 420 421 } // end namespace WebAssembly 422 } // end namespace llvm 423 424 #endif 425