1e8d8bef9SDimitry Andric//===----------- VVPInstrPatternsVec.td - VVP_* SDNode patterns -----------===// 2e8d8bef9SDimitry Andric// 3e8d8bef9SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4e8d8bef9SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5e8d8bef9SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6e8d8bef9SDimitry Andric// 7e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 8e8d8bef9SDimitry Andric// 9e8d8bef9SDimitry Andric// This file describes how VVP_* SDNodes are lowered to machine instructions. 10e8d8bef9SDimitry Andric// 11e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 12e8d8bef9SDimitry Andric 13e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 14e8d8bef9SDimitry Andric// 15e8d8bef9SDimitry Andric// VVP SDNode definitions. 16e8d8bef9SDimitry Andric// 17e8d8bef9SDimitry Andric//===----------------------------------------------------------------------===// 18e8d8bef9SDimitry Andricinclude "VVPInstrInfo.td" 19e8d8bef9SDimitry Andric 20e8d8bef9SDimitry Andricmulticlass VectorBinaryArith< 21e8d8bef9SDimitry Andric SDPatternOperator OpNode, 22e8d8bef9SDimitry Andric ValueType ScalarVT, ValueType DataVT, ValueType MaskVT, 23*349cc55cSDimitry Andric string OpBaseName> { 24e8d8bef9SDimitry Andric // No mask. 25e8d8bef9SDimitry Andric def : Pat<(OpNode 26e8d8bef9SDimitry Andric (any_broadcast ScalarVT:$sx), 27e8d8bef9SDimitry Andric DataVT:$vy, (MaskVT true_mask), i32:$avl), 28e8d8bef9SDimitry Andric (!cast<Instruction>(OpBaseName#"rvl") 29e8d8bef9SDimitry Andric ScalarVT:$sx, $vy, $avl)>; 30e8d8bef9SDimitry Andric def : Pat<(OpNode DataVT:$vx, DataVT:$vy, (MaskVT true_mask), i32:$avl), 31e8d8bef9SDimitry Andric (!cast<Instruction>(OpBaseName#"vvl") 32e8d8bef9SDimitry Andric $vx, $vy, $avl)>; 33e8d8bef9SDimitry Andric 34e8d8bef9SDimitry Andric // Mask. 35e8d8bef9SDimitry Andric def : Pat<(OpNode 36e8d8bef9SDimitry Andric (any_broadcast ScalarVT:$sx), 37e8d8bef9SDimitry Andric DataVT:$vy, MaskVT:$mask, i32:$avl), 38e8d8bef9SDimitry Andric (!cast<Instruction>(OpBaseName#"rvml") 39e8d8bef9SDimitry Andric ScalarVT:$sx, $vy, $mask, $avl)>; 40e8d8bef9SDimitry Andric def : Pat<(OpNode DataVT:$vx, DataVT:$vy, MaskVT:$mask, i32:$avl), 41e8d8bef9SDimitry Andric (!cast<Instruction>(OpBaseName#"vvml") 42e8d8bef9SDimitry Andric $vx, $vy, $mask, $avl)>; 43e8d8bef9SDimitry Andric 44e8d8bef9SDimitry Andric // TODO We do not specify patterns for the immediate variants here. There 45e8d8bef9SDimitry Andric // will be an immediate folding pass that takes care of switching to the 46e8d8bef9SDimitry Andric // immediate variant where applicable. 47e8d8bef9SDimitry Andric 48e8d8bef9SDimitry Andric // TODO Fold vvp_select into passthru. 49e8d8bef9SDimitry Andric} 50e8d8bef9SDimitry Andric 51e8d8bef9SDimitry Andric// Expand both 64bit and 32 bit variant (256 elements) 52e8d8bef9SDimitry Andricmulticlass VectorBinaryArith_ShortLong< 53e8d8bef9SDimitry Andric SDPatternOperator OpNode, 54e8d8bef9SDimitry Andric ValueType LongScalarVT, ValueType LongDataVT, string LongOpBaseName, 55e8d8bef9SDimitry Andric ValueType ShortScalarVT, ValueType ShortDataVT, string ShortOpBaseName> { 56e8d8bef9SDimitry Andric defm : VectorBinaryArith<OpNode, 57e8d8bef9SDimitry Andric LongScalarVT, LongDataVT, v256i1, 58*349cc55cSDimitry Andric LongOpBaseName>; 59e8d8bef9SDimitry Andric defm : VectorBinaryArith<OpNode, 60e8d8bef9SDimitry Andric ShortScalarVT, ShortDataVT, v256i1, 61*349cc55cSDimitry Andric ShortOpBaseName>; 62e8d8bef9SDimitry Andric} 63e8d8bef9SDimitry Andric 64e8d8bef9SDimitry Andric 65e8d8bef9SDimitry Andricdefm : VectorBinaryArith_ShortLong<c_vvp_add, 66e8d8bef9SDimitry Andric i64, v256i64, "VADDSL", 67e8d8bef9SDimitry Andric i32, v256i32, "VADDSWSX">; 68e8d8bef9SDimitry Andricdefm : VectorBinaryArith_ShortLong<c_vvp_and, 69e8d8bef9SDimitry Andric i64, v256i64, "VAND", 70e8d8bef9SDimitry Andric i32, v256i32, "PVANDLO">; 71