xref: /freebsd/contrib/llvm-project/llvm/lib/Target/VE/VETargetTransformInfo.h (revision bc5304a006238115291e7568583632889dffbab9)
1 //===- VETargetTransformInfo.h - VE specific TTI ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// VE target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
18 
19 #include "VE.h"
20 #include "VETargetMachine.h"
21 #include "llvm/Analysis/TargetTransformInfo.h"
22 #include "llvm/CodeGen/BasicTTIImpl.h"
23 
24 namespace llvm {
25 
26 class VETTIImpl : public BasicTTIImplBase<VETTIImpl> {
27   using BaseT = BasicTTIImplBase<VETTIImpl>;
28   friend BaseT;
29 
30   const VESubtarget *ST;
31   const VETargetLowering *TLI;
32 
33   const VESubtarget *getST() const { return ST; }
34   const VETargetLowering *getTLI() const { return TLI; }
35 
36   bool enableVPU() const { return getST()->enableVPU(); }
37 
38 public:
39   explicit VETTIImpl(const VETargetMachine *TM, const Function &F)
40       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
41         TLI(ST->getTargetLowering()) {}
42 
43   unsigned getNumberOfRegisters(unsigned ClassID) const {
44     bool VectorRegs = (ClassID == 1);
45     if (VectorRegs) {
46       // TODO report vregs once vector isel is stable.
47       return 0;
48     }
49 
50     return 64;
51   }
52 
53   unsigned getRegisterBitWidth(bool Vector) const {
54     if (Vector) {
55       // TODO report vregs once vector isel is stable.
56       return 0;
57     }
58     return 64;
59   }
60 
61   unsigned getMinVectorRegisterBitWidth() const {
62     // TODO report vregs once vector isel is stable.
63     return 0;
64   }
65 };
66 
67 } // namespace llvm
68 
69 #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H
70