1//===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the VE register file 11//===----------------------------------------------------------------------===// 12 13class VEReg<bits<7> enc, string n, list<Register> subregs = [], 14 list<string> altNames = [], list<Register> aliases = []> 15 : Register<n, altNames> { 16 let HWEncoding{15-7} = 0; 17 let HWEncoding{6-0} = enc; 18 let Namespace = "VE"; 19 let SubRegs = subregs; 20 let Aliases = aliases; 21} 22 23class VEMiscReg<bits<6> enc, string n>: Register<n> { 24 let HWEncoding{15-6} = 0; 25 let HWEncoding{5-0} = enc; 26 let Namespace = "VE"; 27} 28 29class VEVecReg<bits<8> enc, string n, list<Register> subregs = [], 30 list<string> altNames = [], list<Register> aliases = []> 31 : Register<n, altNames> { 32 let HWEncoding{15-8} = 0; 33 let HWEncoding{7-0} = enc; 34 let Namespace = "VE"; 35 let SubRegs = subregs; 36 let Aliases = aliases; 37} 38 39class VEMaskReg<bits<4> enc, string n, list<Register> subregs = [], 40 list<string> altNames = [], list<Register> aliases = []> 41 : Register<n, altNames> { 42 let HWEncoding{15-4} = 0; 43 let HWEncoding{3-0} = enc; 44 let Namespace = "VE"; 45 let SubRegs = subregs; 46 let Aliases = aliases; 47} 48 49let Namespace = "VE" in { 50 def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) 51 def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) 52 def sub_even : SubRegIndex<64>; // High 64 bit (0..63) 53 def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127) 54 def sub_vm_even : SubRegIndex<256>; // High 256 bit (0..255) 55 def sub_vm_odd : SubRegIndex<256, 256>; // Low 256 bit (256..511) 56 def AsmName : RegAltNameIndex; 57} 58 59//----------------------------------------------------------------------------- 60// Miscellaneous Registers 61//----------------------------------------------------------------------------- 62 63def USRCC : VEMiscReg<0, "usrcc">; // User clock counter 64def PSW : VEMiscReg<1, "psw">; // Program status word 65def SAR : VEMiscReg<2, "sar">; // Store address register 66def PMMR : VEMiscReg<7, "pmmr">; // Performance monitor mode register 67 68// Performance monitor configuration registers 69foreach I = 0-3 in 70 def PMCR#I : VEMiscReg<!add(8,I), "pmcr"#I>; 71 72// Performance monitor counter 73foreach I = 0-14 in 74 def PMC#I : VEMiscReg<!add(16,I), "pmc"#I>; 75 76// Register classes. 77def MISC : RegisterClass<"VE", [i64], 64, 78 (add USRCC, PSW, SAR, PMMR, 79 (sequence "PMCR%u", 0, 3), 80 (sequence "PMC%u", 0, 14))>; 81 82//----------------------------------------------------------------------------- 83// Instruction Counter Register 84//----------------------------------------------------------------------------- 85 86def IC : VEMiscReg<62, "ic">; 87 88//----------------------------------------------------------------------------- 89// Vector Length Register 90//----------------------------------------------------------------------------- 91 92def VL : VEMiscReg<63, "vl">; 93 94// Register classes. 95def VLS : RegisterClass<"VE", [i32], 64, (add VL)>; 96 97//----------------------------------------------------------------------------- 98// Generic Registers 99//----------------------------------------------------------------------------- 100 101let RegAltNameIndices = [AsmName] in { 102 103// Generic integer registers - 32 bits wide 104foreach I = 0-63 in 105 def SW#I : VEReg<I, "sw"#I, [], ["s"#I]>, DwarfRegNum<[I]>; 106 107// Generic floating point registers - 32 bits wide 108// NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation 109// problem. 110foreach I = 0-63 in 111 def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>, 112 DwarfRegNum<[I]>; 113 114// Generic integer registers - 64 bits wide 115let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in { 116 // Several registers have specific names, so add them to one of aliases. 117 def SX8 : VEReg<8, "s8", [SW8, SF8], ["s8", "sl"]>, DwarfRegNum<[8]>; 118 def SX9 : VEReg<9, "s9", [SW9, SF9], ["s9", "fp"]>, DwarfRegNum<[9]>; 119 def SX10 : VEReg<10, "s10", [SW10, SF10], ["s10", "lr"]>, DwarfRegNum<[10]>; 120 def SX11 : VEReg<11, "s11", [SW11, SF11], ["s11", "sp"]>, DwarfRegNum<[11]>; 121 def SX14 : VEReg<14, "s14", [SW14, SF14], ["s14", "tp"]>, DwarfRegNum<[14]>; 122 def SX15 : VEReg<15, "s15", [SW15, SF15], ["s15", "got"]>, DwarfRegNum<[15]>; 123 def SX16 : VEReg<16, "s16", [SW16, SF16], ["s16", "plt"]>, DwarfRegNum<[16]>; 124 125 // Other generic registers. 126 foreach I = { 0-7, 12-13, 17-63 } in 127 def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)], 128 ["s"#I]>, DwarfRegNum<[I]>; 129} 130 131// Aliases of the S* registers used to hold 128-bit for values (long doubles). 132// Following foreach represents something like: 133// def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>; 134// def Q1 : VEReg<2, "q2", [SX2, SX3], ["s2"]>; 135// ... 136let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in 137foreach I = 0-31 in 138 def Q#I : VEReg<!shl(I,1), "q"#I, 139 [!cast<VEReg>("SX"#!shl(I,1)), 140 !cast<VEReg>("SX"#!add(!shl(I,1),1))], 141 ["s"#!shl(I,1)]>; 142 143// Vector registers - 64 bits wide 256 elements 144foreach I = 0-63 in 145 def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>; 146 147// Vector Index Register 148def VIX : VEVecReg<255, "vix", [], ["vix"]>; 149 150// Vector mask registers - 256 bits wide 151let isConstant = true in 152def VM0 : VEMaskReg<0, "vm0", [], ["vm0"]>, DwarfRegNum<[128]>; 153foreach I = 1-15 in 154 def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>; 155 156// Aliases of VMs to use as a pair of two VM for packed instructions 157let isConstant = true in 158def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>; 159 160let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in 161foreach I = 1-7 in 162 def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I, 163 [!cast<VEMaskReg>("VM"#!shl(I,1)), 164 !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))], 165 ["vm"#!shl(I,1)]>; 166 167} // RegAltNameIndices = [AsmName] 168 169// Register classes. 170// 171// The register order is defined in terms of the preferred 172// allocation order. 173def I32 : RegisterClass<"VE", [i32], 32, 174 (add (sequence "SW%u", 0, 7), 175 (sequence "SW%u", 34, 63), 176 (sequence "SW%u", 8, 33))>; 177def I64 : RegisterClass<"VE", [i64, f64], 64, 178 (add (sequence "SX%u", 0, 7), 179 (sequence "SX%u", 34, 63), 180 (sequence "SX%u", 8, 33))>; 181def F32 : RegisterClass<"VE", [f32], 32, 182 (add (sequence "SF%u", 0, 7), 183 (sequence "SF%u", 34, 63), 184 (sequence "SF%u", 8, 33))>; 185def F128 : RegisterClass<"VE", [f128], 128, 186 (add (sequence "Q%u", 0, 3), 187 (sequence "Q%u", 17, 31), 188 (sequence "Q%u", 4, 16))>; 189 190def V64 : RegisterClass<"VE", 191 [v256f64, // default type for vector registers 192 v512i32, v512f32, 193 v256i64, v256i32, v256f32, /* v256f64, */], 64, 194 (add (sequence "V%u", 0, 63), 195 VIX)>; 196 197// vm0 is reserved for always true 198def VM : RegisterClass<"VE", [v256i1], 64, (sequence "VM%u", 0, 15)>; 199def VM512 : RegisterClass<"VE", [v512i1], 64, (sequence "VMP%u", 0, 7)>; 200