1//===----------------------------------------------------------------------===// 2// Vector Instructions 3//===----------------------------------------------------------------------===// 4 5// Pseudo instructions for VM/VM512 spill/restore 6// 7// These pseudo instructions are used for only spill/restore since 8// InlineSpiller assumes storeRegToStackSlot/loadRegFromStackSlot 9// functions emit only single instruction. Those functions emit a 10// single store/load instruction or one of these pseudo store/load 11// instructions. 12// 13// Specifies hasSideEffects = 0 to disable UnmodeledSideEffects. 14 15let mayLoad = 1, hasSideEffects = 0 in { 16def LDVMrii : Pseudo< 17 (outs VM:$vmx), (ins MEMrii:$addr), 18 "# pseudo ldvm $vmx, $addr", []>; 19def LDVM512rii : Pseudo< 20 (outs VM512:$vmx), (ins MEMrii:$addr), 21 "# pseudo ldvm512 $vmx, $addr", []>; 22} 23let mayStore = 1, hasSideEffects = 0 in { 24def STVMrii : Pseudo< 25 (outs), (ins MEMrii:$addr, VM:$vmx), 26 "# pseudo stvm $addr, $vmx", []>; 27def STVM512rii : Pseudo< 28 (outs), (ins MEMrii:$addr, VM512:$vmx), 29 "# pseudo stvm512 $addr, $vmx", []>; 30} 31 32//===----------------------------------------------------------------------===// 33// Pseudo instructions for VM512 modifications 34//===----------------------------------------------------------------------===// 35 36// LVM/SVM instructions using VM512 37let hasSideEffects = 0, isCodeGenOnly = 1 in { 38 let Constraints = "$vx = $vd", DisableEncoding = "$vd" in { 39 def LVMyir_y : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz, VM512:$vd), 40 "# pseudo LVM $vx, $sy, $sz, $vd">; 41 def LVMyim_y : Pseudo<(outs VM512:$vx), 42 (ins uimm3:$sy, mimm:$sz, VM512:$vd), 43 "# pseudo LVM $vx, $sy, $sz, $vd">; 44 } 45 def LVMyir : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, I64:$sz), 46 "# pseudo LVM $vx, $sy, $sz">; 47 def LVMyim : Pseudo<(outs VM512:$vx), (ins uimm3:$sy, mimm:$sz), 48 "# pseudo LVM $vx, $sy, $sz">; 49 def SVMyi : Pseudo<(outs I64:$sx), (ins VM512:$vz, uimm3:$sy), 50 "# pseudo SVM $sx, $vz, $sy">; 51} 52 53// VFMK/VFMKW/VFMKS instructions using VM512 54let hasSideEffects = 0, isCodeGenOnly = 1, DisableEncoding = "$vl" in { 55 def VFMKyal : Pseudo<(outs VM512:$vmx), (ins I32:$vl), 56 "# pseudo-vfmk.at $vmx">; 57 def VFMKynal : Pseudo<(outs VM512:$vmx), (ins I32:$vl), 58 "# pseudo-vfmk.af $vmx">; 59 def VFMKWyvl : Pseudo<(outs VM512:$vmx), 60 (ins CCOp:$cf, V64:$vz, I32:$vl), 61 "# pseudo-vfmk.w.$cf $vmx, $vz">; 62 def VFMKWyvyl : Pseudo<(outs VM512:$vmx), 63 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl), 64 "# pseudo-vfmk.w.$cf $vmx, $vz, $vm">; 65 def VFMKSyvl : Pseudo<(outs VM512:$vmx), 66 (ins CCOp:$cf, V64:$vz, I32:$vl), 67 "# pseudo-vfmk.s.$cf $vmx, $vz">; 68 def VFMKSyvyl : Pseudo<(outs VM512:$vmx), 69 (ins CCOp:$cf, V64:$vz, VM512:$vm, I32:$vl), 70 "# pseudo-vfmk.s.$cf $vmx, $vz, $vm">; 71} 72 73// ANDM/ORM/XORM/EQVM/NNDM/NEGM instructions using VM512 74let hasSideEffects = 0, isCodeGenOnly = 1 in { 75 def ANDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz), 76 "# andm $vmx, $vmy, $vmz">; 77 def ORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz), 78 "# orm $vmx, $vmy, $vmz">; 79 def XORMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz), 80 "# xorm $vmx, $vmy, $vmz">; 81 def EQVMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz), 82 "# eqvm $vmx, $vmy, $vmz">; 83 def NNDMyy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy, VM512:$vmz), 84 "# nndm $vmx, $vmy, $vmz">; 85 def NEGMy : Pseudo<(outs VM512:$vmx), (ins VM512:$vmy), 86 "# negm $vmx, $vmy">; 87} 88 89//===----------------------------------------------------------------------===// 90// Instructions 91// 92// Define all vector instructions defined in SX-Aurora TSUBASA Architecture 93// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine 94// Assembly Language Reference Manual. 95// 96// Some instructions can update existing data by following instructions 97// sequence. 98// 99// lea %s0, 256 100// lea %s1, 128 101// lvl %s0 102// vbrd %v0, 2 # v0 = { 2, 2, 2, ..., 2, 2, 2 } 103// lvl %s1 104// vbrd %v0, 3 # v0 = { 3, 3, 3, ..., 3, 2, 2, 2, ..., 2, 2, 2 } 105// 106// In order to represent above with a virtual register, we defines instructions 107// with an additional base register and `_v` suffiex in mnemonic. 108// 109// lea t0, 256 110// lea t1, 128 111// lea t0 112// vbrd tv0, 2 113// lvl t1 114// vbrd_v tv1, 2, tv0 115// 116// We also have some instructions uses VL register with an pseudo VL value 117// with following suffixes in mnemonic. 118// 119// l: have an additional I32 register to represent the VL value. 120// L: have an additional VL register to represent the VL value. 121//===----------------------------------------------------------------------===// 122 123//----------------------------------------------------------------------------- 124// Section 8.9 - Vector Load/Store and Move Instructions 125//----------------------------------------------------------------------------- 126 127// Multiclass for VLD instructions 128let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in 129multiclass VLDbm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in, 130 string disEnc = ""> { 131 let DisableEncoding = disEnc in 132 def "" : RVM<opc, (outs RC:$vx), dag_in, 133 !strconcat(opcStr, " $vx, $sy, $sz")>; 134 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base", 135 isCodeGenOnly = 1 in 136 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 137 !strconcat(opcStr, " $vx, $sy, $sz")>; 138} 139multiclass VLDlm<string opcStr, bits<8>opc, RegisterClass RC, dag dag_in> { 140 defm "" : VLDbm<opcStr, opc, RC, dag_in>; 141 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 142 defm l : VLDbm<opcStr, opc, RC, !con(dag_in, (ins I32:$vl)), "$vl,">; 143 defm L : VLDbm<opcStr, opc, RC, !con(dag_in, (ins VLS:$vl)), "$vl,">; 144 } 145} 146let VE_VLIndex = 3 in 147multiclass VLDtgm<string opcStr, bits<8>opc, RegisterClass RC> { 148 defm rr : VLDlm<opcStr, opc, RC, (ins I64:$sy, I64:$sz)>; 149 let cy = 0 in 150 defm ir : VLDlm<opcStr, opc, RC, (ins simm7:$sy, I64:$sz)>; 151 let cz = 0 in 152 defm rz : VLDlm<opcStr, opc, RC, (ins I64:$sy, zero:$sz)>; 153 let cy = 0, cz = 0 in 154 defm iz : VLDlm<opcStr, opc, RC, (ins simm7:$sy, zero:$sz)>; 155} 156multiclass VLDm<string opcStr, bits<8>opc, RegisterClass RC> { 157 let vc = 1 in defm "" : VLDtgm<opcStr, opc, RC>; 158 let vc = 0 in defm NC : VLDtgm<opcStr#".nc", opc, RC>; 159} 160 161// Section 8.9.1 - VLD (Vector Load) 162defm VLD : VLDm<"vld", 0x81, V64>; 163 164// Section 8.9.2 - VLDU (Vector Load Upper) 165defm VLDU : VLDm<"vldu", 0x82, V64>; 166 167// Section 8.9.3 - VLDL (Vector Load Lower) 168defm VLDLSX : VLDm<"vldl.sx", 0x83, V64>; 169let cx = 1 in defm VLDLZX : VLDm<"vldl.zx", 0x83, V64>; 170 171// Section 8.9.4 - VLD2D (Vector Load 2D) 172defm VLD2D : VLDm<"vld2d", 0xc1, V64>; 173 174// Section 8.9.5 - VLDU2D (Vector Load Upper 2D) 175defm VLDU2D : VLDm<"vldu2d", 0xc2, V64>; 176 177// Section 8.9.6 - VLDL2D (Vector Load Lower 2D) 178defm VLDL2DSX : VLDm<"vldl2d.sx", 0xc3, V64>; 179let cx = 1 in defm VLDL2DZX : VLDm<"vldl2d.zx", 0xc3, V64>; 180 181// Multiclass for VST instructions 182let mayStore = 1, hasSideEffects = 0, Uses = [VL] in 183multiclass VSTbm<string opcStr, string argStr, bits<8>opc, dag dag_in> { 184 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>; 185 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in { 186 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)), 187 !strconcat(opcStr, argStr)>; 188 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)), 189 !strconcat(opcStr, argStr)>; 190 } 191} 192multiclass VSTmm<string opcStr, bits<8>opc, dag dag_in> { 193 defm "" : VSTbm<opcStr, " $vx, $sy, $sz", opc, dag_in>; 194 let m = ?, VE_VLWithMask = 1 in 195 defm m : VSTbm<opcStr, " $vx, $sy, $sz, $m", opc, !con(dag_in, (ins VM:$m))>; 196} 197let VE_VLIndex = 3 in 198multiclass VSTtgm<string opcStr, bits<8>opc, RegisterClass RC> { 199 defm rrv : VSTmm<opcStr, opc, (ins I64:$sy, I64:$sz, RC:$vx)>; 200 let cy = 0 in 201 defm irv : VSTmm<opcStr, opc, (ins simm7:$sy, I64:$sz, RC:$vx)>; 202 let cz = 0 in 203 defm rzv : VSTmm<opcStr, opc, (ins I64:$sy, zero:$sz, RC:$vx)>; 204 let cy = 0, cz = 0 in 205 defm izv : VSTmm<opcStr, opc, (ins simm7:$sy, zero:$sz, RC:$vx)>; 206} 207multiclass VSTm<string opcStr, bits<8>opc, RegisterClass RC> { 208 let vc = 1, cx = 0 in defm "" : VSTtgm<opcStr, opc, RC>; 209 let vc = 0, cx = 0 in defm NC : VSTtgm<opcStr#".nc", opc, RC>; 210 let vc = 1, cx = 1 in defm OT : VSTtgm<opcStr#".ot", opc, RC>; 211 let vc = 0, cx = 1 in defm NCOT : VSTtgm<opcStr#".nc.ot", opc, RC>; 212} 213 214// Section 8.9.7 - VST (Vector Store) 215defm VST : VSTm<"vst", 0x91, V64>; 216 217// Section 8.9.8 - VST (Vector Store Upper) 218defm VSTU : VSTm<"vstu", 0x92, V64>; 219 220// Section 8.9.9 - VSTL (Vector Store Lower) 221defm VSTL : VSTm<"vstl", 0x93, V64>; 222 223// Section 8.9.10 - VST2D (Vector Store 2D) 224defm VST2D : VSTm<"vst2d", 0xd1, V64>; 225 226// Section 8.9.11 - VSTU2D (Vector Store Upper 2D) 227defm VSTU2D : VSTm<"vstu2d", 0xd2, V64>; 228 229// Section 8.9.12 - VSTL2D (Vector Store Lower 2D) 230defm VSTL2D : VSTm<"vstl2d", 0xd3, V64>; 231 232// Multiclass for VGT instructions 233let mayLoad = 1, hasSideEffects = 0, Uses = [VL] in 234multiclass VGTbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 235 dag dag_in, string disEnc = ""> { 236 let DisableEncoding = disEnc in 237 def "" : RVM<opc, (outs RC:$vx), dag_in, 238 !strconcat(opcStr, " $vx, ", argStr)>; 239 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base", 240 isCodeGenOnly = 1 in 241 def _v : RVM<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 242 !strconcat(opcStr, " $vx, ", argStr)>; 243} 244multiclass VGTlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 245 dag dag_in> { 246 defm "" : VGTbm<opcStr, argStr, opc, RC, dag_in>; 247 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 248 defm l : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)), 249 "$vl,">; 250 defm L : VGTbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)), 251 "$vl,">; 252 } 253} 254multiclass VGTmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 255 dag dag_in> { 256 defm "" : VGTlm<opcStr, argStr, opc, RC, dag_in>; 257 let m = ?, VE_VLWithMask = 1 in 258 defm m : VGTlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins VM:$m))>; 259} 260let VE_VLIndex = 4 in 261multiclass VGTlhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 262 dag dag_in> { 263 defm rr : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC, 264 !con(dag_in, (ins I64:$sy, I64:$sz))>; 265 let cy = 0 in 266 defm ir : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC, 267 !con(dag_in, (ins simm7:$sy, I64:$sz))>; 268 let cz = 0 in 269 defm rz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC, 270 !con(dag_in, (ins I64:$sy, zero:$sz))>; 271 let cy = 0, cz = 0 in 272 defm iz : VGTmm<opcStr, argStr#", $sy, $sz", opc, RC, 273 !con(dag_in, (ins simm7:$sy, zero:$sz))>; 274} 275multiclass VGTtgm<string opcStr, bits<8>opc, RegisterClass RC> { 276 let vy = ? in defm v : VGTlhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>; 277 let cs = 1, sw = ? in defm s : VGTlhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>; 278} 279multiclass VGTm<string opcStr, bits<8>opc, RegisterClass RC> { 280 let vc = 1 in defm "" : VGTtgm<opcStr, opc, RC>; 281 let vc = 0 in defm NC : VGTtgm<opcStr#".nc", opc, RC>; 282} 283 284// Section 8.9.13 - VGT (Vector Gather) 285defm VGT : VGTm<"vgt", 0xa1, V64>; 286 287// Section 8.9.14 - VGTU (Vector Gather Upper) 288defm VGTU : VGTm<"vgtu", 0xa2, V64>; 289 290// Section 8.9.15 - VGTL (Vector Gather Lower) 291defm VGTLSX : VGTm<"vgtl.sx", 0xa3, V64>; 292let cx = 1 in defm VGTLZX : VGTm<"vgtl.zx", 0xa3, V64>; 293def : MnemonicAlias<"vgtl", "vgtl.zx">; 294def : MnemonicAlias<"vgtl.nc", "vgtl.zx.nc">; 295 296// Multiclass for VSC instructions 297let mayStore = 1, hasSideEffects = 0, Uses = [VL] in 298multiclass VSCbm<string opcStr, string argStr, bits<8>opc, dag dag_in> { 299 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>; 300 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in { 301 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)), 302 !strconcat(opcStr, argStr)>; 303 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)), 304 !strconcat(opcStr, argStr)>; 305 } 306} 307multiclass VSCmm<string opcStr, string argStr, bits<8>opc, dag dag_in> { 308 defm "" : VSCbm<opcStr, argStr, opc, dag_in>; 309 let m = ?, VE_VLWithMask = 1 in 310 defm m : VSCbm<opcStr, argStr#", $m", opc, !con(dag_in, (ins VM:$m))>; 311} 312let VE_VLIndex = 4 in 313multiclass VSClhm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 314 dag dag_in> { 315 defm rrv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc, 316 !con(dag_in, (ins I64:$sy, I64:$sz, RC:$vx))>; 317 let cy = 0 in 318 defm irv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc, 319 !con(dag_in, (ins simm7:$sy, I64:$sz, RC:$vx))>; 320 let cz = 0 in 321 defm rzv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc, 322 !con(dag_in, (ins I64:$sy, zero:$sz, RC:$vx))>; 323 let cy = 0, cz = 0 in 324 defm izv : VSCmm<opcStr, " $vx, "#argStr#", $sy, $sz", opc, 325 !con(dag_in, (ins simm7:$sy, zero:$sz, RC:$vx))>; 326} 327multiclass VSCtgm<string opcStr, bits<8>opc, RegisterClass RC> { 328 let vy = ? in defm v : VSClhm<opcStr, "$vy", opc, RC, (ins V64:$vy)>; 329 let cs = 1, sw = ? in defm s : VSClhm<opcStr, "$sw", opc, RC, (ins I64:$sw)>; 330} 331multiclass VSCm<string opcStr, bits<8>opc, RegisterClass RC> { 332 let vc = 1, cx = 0 in defm "" : VSCtgm<opcStr, opc, RC>; 333 let vc = 0, cx = 0 in defm NC : VSCtgm<opcStr#".nc", opc, RC>; 334 let vc = 1, cx = 1 in defm OT : VSCtgm<opcStr#".ot", opc, RC>; 335 let vc = 0, cx = 1 in defm NCOT : VSCtgm<opcStr#".nc.ot", opc, RC>; 336} 337 338// Section 8.9.16 - VSC (Vector Scatter) 339defm VSC : VSCm<"vsc", 0xb1, V64>; 340 341// Section 8.9.17 - VSCU (Vector Scatter Upper) 342defm VSCU : VSCm<"vscu", 0xb2, V64>; 343 344// Section 8.9.18 - VSCL (Vector Scatter Lower) 345defm VSCL : VSCm<"vscl", 0xb3, V64>; 346 347// Section 8.9.19 - PFCHV (Prefetch Vector) 348let Uses = [VL] in 349multiclass PFCHVbm<string opcStr, string argStr, bits<8>opc, dag dag_in> { 350 def "" : RVM<opc, (outs), dag_in, !strconcat(opcStr, argStr)>; 351 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in { 352 def l : RVM<opc, (outs), !con(dag_in, (ins I32:$vl)), 353 !strconcat(opcStr, argStr)>; 354 def L : RVM<opc, (outs), !con(dag_in, (ins VLS:$vl)), 355 !strconcat(opcStr, argStr)>; 356 } 357} 358let VE_VLIndex = 2 in 359multiclass PFCHVm<string opcStr, bits<8>opc> { 360 defm rr : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, I64:$sz)>; 361 let cy = 0 in 362 defm ir : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, I64:$sz)>; 363 let cz = 0 in 364 defm rz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins I64:$sy, zero:$sz)>; 365 let cy = 0, cz = 0 in 366 defm iz : PFCHVbm<opcStr, " $sy, $sz", opc, (ins simm7:$sy, zero:$sz)>; 367} 368let vc = 1, vx = 0 in defm PFCHV : PFCHVm<"pfchv", 0x80>; 369let vc = 0, vx = 0 in defm PFCHVNC : PFCHVm<"pfchv.nc", 0x80>; 370 371// Section 8.9.20 - LSV (Load S to V) 372let sx = 0, vx = ?, hasSideEffects = 0 in 373multiclass LSVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 374 dag dag_in> { 375 def "" : RR<opc, (outs RC:$vx), dag_in, !strconcat(opcStr, " ${vx}", argStr)>; 376 let Constraints = "$vx = $base", DisableEncoding = "$base", 377 isCodeGenOnly = 1 in 378 def _v : RR<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 379 !strconcat(opcStr, " ${vx}", argStr)>; 380} 381multiclass LSVm<string opcStr, bits<8>opc, RegisterClass RC> { 382 defm rr : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, I64:$sz)>; 383 let cy = 0 in 384 defm ir : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, I64:$sz)>; 385 let cz = 0 in 386 defm rm : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins I64:$sy, mimm:$sz)>; 387 let cy = 0, cz = 0 in 388 defm im : LSVbm<opcStr, "(${sy}), $sz", opc, RC, (ins uimm7:$sy, mimm:$sz)>; 389} 390defm LSV : LSVm<"lsv", 0x8e, V64>; 391 392// Section 8.9.21 - LVS (Load V to S) 393let cz = 0, sz = 0, vx = ?, hasSideEffects = 0 in 394multiclass LVSm<string opcStr, bits<8>opc, RegisterClass RC> { 395 def vr : RR<opc, (outs I64:$sx), (ins RC:$vx, I64:$sy), 396 opcStr#" $sx, ${vx}(${sy})">; 397 let cy = 0 in 398 def vi : RR<opc, (outs I64:$sx), (ins RC:$vx, uimm7:$sy), 399 opcStr#" $sx, ${vx}(${sy})">; 400} 401defm LVS : LVSm<"lvs", 0x9e, V64>; 402 403// Section 8.9.22 - LVM (Load VM) 404let sx = 0, vx = ?, hasSideEffects = 0 in 405multiclass LVMbm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM, 406 dag dag_in> { 407 def "" : RR<opc, (outs RCM:$vx), dag_in, 408 !strconcat(opcStr, " $vx, ", argStr)>; 409 let Constraints = "$vx = $base", DisableEncoding = "$base", 410 isCodeGenOnly = 1 in { 411 def _m : RR<opc, (outs RCM:$vx), !con(dag_in, (ins RCM:$base)), 412 !strconcat(opcStr, " $vx, ", argStr)>; 413 } 414} 415multiclass LVMom<string opcStr, bits<8>opc, RegisterClass RCM> { 416 defm rr : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, I64:$sz)>; 417 let cy = 0 in 418 defm ir : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, I64:$sz)>; 419 let cz = 0 in 420 defm rm : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins I64:$sy, mimm:$sz)>; 421 let cy = 0, cz = 0 in 422 defm im : LVMbm<opcStr, "$sy, $sz", opc, RCM, (ins uimm2:$sy, mimm:$sz)>; 423} 424multiclass LVMm<string opcStr, bits<8>opc, RegisterClass RCM> { 425 defm "" : LVMom<opcStr, opc, RCM>; 426} 427defm LVM : LVMm<"lvm", 0xb7, VM>; 428 429// Section 8.9.23 - SVM (Save VM) 430let cz = 0, sz = 0, vz = ?, hasSideEffects = 0 in 431multiclass SVMm<string opcStr, bits<8>opc, RegisterClass RCM> { 432 def mr : RR<opc, (outs I64:$sx), (ins RCM:$vz, I64:$sy), 433 opcStr#" $sx, $vz, $sy">; 434 let cy = 0 in 435 def mi : RR<opc, (outs I64:$sx), (ins RCM:$vz, uimm2:$sy), 436 opcStr#" $sx, $vz, $sy">; 437} 438defm SVM : SVMm<"svm", 0xa7, VM>; 439 440// Section 8.9.24 - VBRD (Vector Broadcast) 441let vx = ?, hasSideEffects = 0, Uses = [VL] in 442multiclass VBRDbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 443 dag dag_in, string disEnc = ""> { 444 let DisableEncoding = disEnc in 445 def "" : RV<opc, (outs RC:$vx), dag_in, 446 !strconcat(opcStr, " $vx, ", argStr)>; 447 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base", 448 isCodeGenOnly = 1 in 449 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 450 !strconcat(opcStr, " $vx, ", argStr)>; 451} 452multiclass VBRDlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 453 dag dag_in> { 454 defm "" : VBRDbm<opcStr, argStr, opc, RC, dag_in>; 455 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 456 defm l : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)), 457 "$vl,">; 458 defm L : VBRDbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)), 459 "$vl,">; 460 } 461} 462multiclass VBRDmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 463 RegisterClass RCM, dag dag_in> { 464 defm "" : VBRDlm<opcStr, argStr, opc, RC, dag_in>; 465 let m = ?, VE_VLWithMask = 1 in 466 defm m : VBRDlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>; 467} 468let VE_VLIndex = 2 in 469multiclass VBRDm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC, 470 RegisterClass RCM> { 471 defm r : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins RC:$sy)>; 472 let cy = 0 in 473 defm i : VBRDmm<opcStr, "$sy", opc, VRC, RCM, (ins simm7:$sy)>; 474} 475let cx = 0, cx2 = 0 in 476defm VBRD : VBRDm<"vbrd", 0x8c, V64, I64, VM>; 477let cx = 0, cx2 = 1 in 478defm VBRDL : VBRDm<"vbrdl", 0x8c, V64, I32, VM>; 479let cx = 1, cx2 = 0 in 480defm VBRDU : VBRDm<"vbrdu", 0x8c, V64, F32, VM>; 481let cx = 1, cx2 = 1 in 482defm PVBRD : VBRDm<"pvbrd", 0x8c, V64, I64, VM512>; 483 484// Section 8.9.25 - VMV (Vector Move) 485let vx = ?, vz = ?, hasSideEffects = 0, Uses = [VL] in 486multiclass VMVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 487 dag dag_in, string disEnc = ""> { 488 let DisableEncoding = disEnc in 489 def "" : RV<opc, (outs RC:$vx), dag_in, 490 !strconcat(opcStr, " $vx, ", argStr)>; 491 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base", 492 isCodeGenOnly = 1 in 493 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 494 !strconcat(opcStr, " $vx, ", argStr)>; 495} 496multiclass VMVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 497 dag dag_in> { 498 defm "" : VMVbm<opcStr, argStr, opc, RC, dag_in>; 499 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 500 defm l : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)), 501 "$vl,">; 502 defm L : VMVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)), 503 "$vl,">; 504 } 505} 506multiclass VMVmm<string opcStr, bits<8>opc, RegisterClass RC, 507 RegisterClass RCM, dag dag_in> { 508 defm "" : VMVlm<opcStr, "$sy, $vz", opc, RC, dag_in>; 509 let m = ?, VE_VLWithMask = 1 in 510 defm m : VMVlm<opcStr, "$sy, $vz, $m", opc, RC, !con(dag_in, (ins RCM:$m))>; 511} 512let VE_VLIndex = 3 in 513multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC, 514 RegisterClass RCM> { 515 defm rv : VMVmm<opcStr, opc, RC, RCM, (ins I64:$sy, RC:$vz)>; 516 let cy = 0 in 517 defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>; 518} 519defm VMV : VMVm<"vmv", 0x9c, V64, VM>; 520 521//----------------------------------------------------------------------------- 522// Section 8.10 - Vector Fixed-Point Arithmetic Instructions 523//----------------------------------------------------------------------------- 524 525// Multiclass for generic vector calculation 526let vx = ?, hasSideEffects = 0, Uses = [VL] in 527multiclass RVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 528 dag dag_in, string disEnc = ""> { 529 let DisableEncoding = disEnc in 530 def "" : RV<opc, (outs RC:$vx), dag_in, 531 !strconcat(opcStr, " $vx", argStr)>; 532 let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base", 533 isCodeGenOnly = 1 in 534 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 535 !strconcat(opcStr, " $vx", argStr)>; 536} 537multiclass RVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 538 dag dag_in> { 539 defm "" : RVbm<opcStr, argStr, opc, RC, dag_in>; 540 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 541 defm l : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)), 542 "$vl,">; 543 defm L : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)), 544 "$vl,">; 545 } 546} 547multiclass RVmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 548 RegisterClass RCM, dag dag_in> { 549 defm "" : RVlm<opcStr, argStr, opc, RC, dag_in>; 550 let m = ?, VE_VLWithMask = 1 in 551 defm m : RVlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>; 552} 553// Generic RV multiclass with 2 arguments. 554// e.g. VADD, VSUB, VMPY, and etc. 555let VE_VLIndex = 3 in 556multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC, 557 RegisterClass RCM, Operand SIMM = simm7> { 558 let cy = 0, sy = 0, vy = ?, vz = ? in 559 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>; 560 let cs = 1, vz = ? in 561 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>; 562 let cs = 1, cy = 0, vz = ? in 563 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>; 564} 565// Special RV multiclass with 2 arguments using cs2. 566// e.g. VDIV, VDVS, and VDVX. 567let VE_VLIndex = 3 in 568multiclass RVDIVm<string opcStr, bits<8>opc, RegisterClass VRC, 569 RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> { 570 let cy = 0, sy = 0, vy = ?, vz = ? in 571 defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>; 572 let cs2 = 1, vy = ? in 573 defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>; 574 let cs2 = 1, cy = 0, vy = ? in 575 defm vi : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, SIMM:$sy)>; 576 let cs = 1, vz = ? in 577 defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>; 578 let cs = 1, cy = 0, vz = ? in 579 defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>; 580} 581// Generic RV multiclass with 2 arguments for logical operations. 582// e.g. VAND, VOR, VXOR, and etc. 583let VE_VLIndex = 3 in 584multiclass RVLm<string opcStr, bits<8>opc, RegisterClass ScaRC, 585 RegisterClass RC, RegisterClass RCM> { 586 let cy = 0, sy = 0, vy = ?, vz = ? in 587 defm vv : RVmm<opcStr, ", $vy, $vz", opc, RC, RCM, (ins RC:$vy, RC:$vz)>; 588 let cs = 1, vz = ? in 589 defm rv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins ScaRC:$sy, RC:$vz)>; 590 let cs = 1, cy = 0, vz = ? in 591 defm mv : RVmm<opcStr, ", $sy, $vz", opc, RC, RCM, (ins mimm:$sy, RC:$vz)>; 592} 593// Generic RV multiclass with 1 argument. 594// e.g. VLDZ, VPCNT, and VBRV. 595let VE_VLIndex = 2 in 596multiclass RV1m<string opcStr, bits<8>opc, RegisterClass RC, 597 RegisterClass RCM> { 598 let cy = 0, sy = 0, vz = ? in 599 defm v : RVmm<opcStr, ", $vz", opc, RC, RCM, (ins RC:$vz)>; 600} 601// Generic RV multiclass with no argument. 602// e.g. VSEQ. 603let VE_VLIndex = 1 in 604multiclass RV0m<string opcStr, bits<8>opc, RegisterClass RC, 605 RegisterClass RCM> { 606 let cy = 0, sy = 0 in 607 defm "" : RVmm<opcStr, "", opc, RC, RCM, (ins)>; 608} 609// Generic RV multiclass with 2 arguments for shift operations. 610// e.g. VSLL, VSRL, VSLA, and etc. 611let VE_VLIndex = 3 in 612multiclass RVSm<string opcStr, bits<8>opc, RegisterClass ScaRC, 613 RegisterClass RC, RegisterClass RCM> { 614 let cy = 0, sy = 0, vy = ?, vz = ? in 615 defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>; 616 let cs = 1, vz = ? in 617 defm vr : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, ScaRC:$sy)>; 618 let cs = 1, cy = 0, vz = ? in 619 defm vi : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, uimm7:$sy)>; 620} 621// Generic RV multiclass with 3 arguments for shift operations. 622// e.g. VSLD and VSRD. 623let VE_VLIndex = 4 in 624multiclass RVSDm<string opcStr, bits<8>opc, RegisterClass RC, 625 RegisterClass RCM> { 626 let vy = ?, vz = ? in 627 defm vvr : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM, 628 (ins RC:$vy, RC:$vz, I64:$sy)>; 629 let cy = 0, vy = ?, vz = ? in 630 defm vvi : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM, 631 (ins RC:$vy, RC:$vz, uimm7:$sy)>; 632} 633// Special RV multiclass with 3 arguments. 634// e.g. VSFA 635let VE_VLIndex = 4 in 636multiclass RVSAm<string opcStr, bits<8>opc, RegisterClass RC, 637 RegisterClass RCM> { 638 let cz = 1, sz = ?, vz = ? in 639 defm vrr : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM, 640 (ins RC:$vz, I64:$sy, I64:$sz)>; 641 let cz = 0, sz = ?, vz = ? in 642 defm vrm : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM, 643 (ins RC:$vz, I64:$sy, mimm:$sz)>; 644 let cy = 0, cz = 1, sz = ?, vz = ? in 645 defm vir : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM, 646 (ins RC:$vz, uimm3:$sy, I64:$sz)>; 647 let cy = 0, cz = 0, sz = ?, vz = ? in 648 defm vim : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM, 649 (ins RC:$vz, uimm3:$sy, mimm:$sz)>; 650} 651// Generic RV multiclass with 1 argument using vy field. 652// e.g. VFSQRT, VRCP, and VRSQRT. 653let VE_VLIndex = 2 in 654multiclass RVF1m<string opcStr, bits<8>opc, RegisterClass RC, 655 RegisterClass RCM> { 656 let cy = 0, sy = 0, vy = ? in 657 defm v : RVmm<opcStr, ", $vy", opc, RC, RCM, (ins RC:$vy)>; 658} 659// Special RV multiclass with 3 arguments using cs2. 660// e.g. VFMAD, VFMSB, VFNMAD, and etc. 661let VE_VLIndex = 4 in 662multiclass RVMm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC, 663 RegisterClass RCM, Operand SIMM = simm7> { 664 let cy = 0, sy = 0, vy = ?, vz = ?, vw = ? in 665 defm vvv : RVmm<opcStr, ", $vy, $vz, $vw", opc, VRC, RCM, 666 (ins VRC:$vy, VRC:$vz, VRC:$vw)>; 667 let cs2 = 1, vy = ?, vw = ? in 668 defm vrv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM, 669 (ins VRC:$vy, RC:$sy, VRC:$vw)>; 670 let cs2 = 1, cy = 0, vy = ?, vw = ? in 671 defm viv : RVmm<opcStr, ", $vy, $sy, $vw", opc, VRC, RCM, 672 (ins VRC:$vy, SIMM:$sy, VRC:$vw)>; 673 let cs = 1, vz = ?, vw = ? in 674 defm rvv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM, 675 (ins RC:$sy, VRC:$vz, VRC:$vw)>; 676 let cs = 1, cy = 0, vz = ?, vw = ? in 677 defm ivv : RVmm<opcStr, ", $sy, $vz, $vw", opc, VRC, RCM, 678 (ins SIMM:$sy, VRC:$vz, VRC:$vw)>; 679} 680// Special RV multiclass with 2 arguments for floating point conversions. 681// e.g. VFIX and VFIXX 682let hasSideEffects = 0, VE_VLIndex = 3 in 683multiclass RVFIXm<string opcStr, bits<8> opc, RegisterClass RC, 684 RegisterClass RCM> { 685 let cy = 0, sy = 0, vy = ?, vz = ? in 686 defm v : RVmm<opcStr#"$vz", ", $vy", opc, RC, RCM, (ins RDOp:$vz, RC:$vy)>; 687} 688// Multiclass for generic iterative vector calculation 689let vx = ?, hasSideEffects = 0, Uses = [VL] in 690multiclass RVIbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 691 dag dag_in, string disEnc = ""> { 692 let DisableEncoding = disEnc in 693 def "" : RV<opc, (outs RC:$vx), dag_in, 694 !strconcat(opcStr, " $vx", argStr)>; 695 let isCodeGenOnly = 1, Constraints = "$vx = $base", DisableEncoding = disEnc#"$base" in 696 def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)), 697 !strconcat(opcStr, " $vx", argStr)>; 698} 699multiclass RVIlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC, 700 dag dag_in> { 701 defm "" : RVIbm<opcStr, argStr, opc, RC, dag_in>; 702 let isCodeGenOnly = 1, VE_VLInUse = 1 in { 703 defm l : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)), 704 "$vl,">; 705 defm L : RVIbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)), 706 "$vl,">; 707 } 708} 709// Generic RV multiclass for iterative operation with 2 argument. 710// e.g. VFIA, VFIS, and VFIM 711let VE_VLIndex = 3 in 712multiclass RVI2m<string opcStr, bits<8>opc, RegisterClass VRC, 713 RegisterClass RC> { 714 let vy = ? in 715 defm vr : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, RC:$sy)>; 716 let cy = 0, vy = ? in 717 defm vi : RVIlm<opcStr, ", $vy, $sy", opc, VRC, (ins VRC:$vy, simm7fp:$sy)>; 718} 719// Generic RV multiclass for iterative operation with 3 argument. 720// e.g. VFIAM, VFISM, VFIMA, and etc. 721let VE_VLIndex = 4 in 722multiclass RVI3m<string opcStr, bits<8>opc, RegisterClass VRC, 723 RegisterClass RC> { 724 let vy = ?, vz = ? in 725 defm vvr : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC, 726 (ins VRC:$vy, VRC:$vz, RC:$sy)>; 727 let cy = 0, vy = ?, vz = ? in 728 defm vvi : RVIlm<opcStr, ", $vy, $vz, $sy", opc, VRC, 729 (ins VRC:$vy, VRC:$vz, simm7fp:$sy)>; 730} 731// special RV multiclass with 3 arguments for VSHF. 732// e.g. VSHF 733let vy = ?, vz = ?, VE_VLIndex = 4 in 734multiclass RVSHFm<string opcStr, bits<8>opc, RegisterClass RC, 735 Operand SIMM = uimm4> { 736 defm vvr : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC, 737 (ins RC:$vy, RC:$vz, I64:$sy)>; 738 let cy = 0 in defm vvi : RVlm<opcStr, ", $vy, $vz, $sy", opc, RC, 739 (ins RC:$vy, RC:$vz, SIMM:$sy)>; 740} 741// Multiclass for generic mask calculation 742let vx = ?, hasSideEffects = 0, Uses = [VL] in 743multiclass RVMKbm<string opcStr, string argStr, bits<8>opc, dag dag_out, 744 dag dag_in> { 745 def "" : RV<opc, dag_out, dag_in, !strconcat(opcStr, argStr)>; 746 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in { 747 def l : RV<opc, dag_out, !con(dag_in, (ins I32:$vl)), 748 !strconcat(opcStr, argStr)>; 749 def L : RV<opc, dag_out, !con(dag_in, (ins VLS:$vl)), 750 !strconcat(opcStr, argStr)>; 751 } 752} 753multiclass RVMKlm<string opcStr, string argStr, bits<8>opc, RegisterClass RCM, 754 dag dag_in> { 755 defm "" : RVMKbm<opcStr, " $vx"#argStr, opc, (outs RCM:$vx), dag_in>; 756 let m = ?, VE_VLWithMask = 1 in 757 defm m : RVMKbm<opcStr, " $vx"#argStr#", $m", opc, (outs RCM:$vx), 758 !con(dag_in, (ins RCM:$m))>; 759} 760// Generic RV multiclass for mask calculation with a condition. 761// e.g. VFMK, VFMS, and VFMF 762let cy = 0, sy = 0 in 763multiclass RVMKom<string opcStr, bits<8> opc, RegisterClass RC, 764 RegisterClass RCM> { 765 let vy = ?, vz = ?, VE_VLIndex = 3 in 766 defm v : RVMKlm<opcStr#"$vy", ", $vz", opc, RCM, (ins CCOp:$vy, RC:$vz)>; 767 let vy = 15 /* AT */, VE_VLIndex = 1 in 768 defm a : RVMKlm<opcStr#"at", "", opc, RCM, (ins)>; 769 let vy = 0 /* AF */, VE_VLIndex = 1 in 770 defm na : RVMKlm<opcStr#"af", "", opc, RCM, (ins)>; 771} 772multiclass RVMKm<string opcStr, bits<8> opc, RegisterClass RC, 773 RegisterClass RCM> { 774 defm "" : RVMKom<opcStr, opc, RC, RCM>; 775} 776// Generic RV multiclass for mask calculation with 2 arguments. 777// e.g. ANDM, ORM, XORM, and etc. 778let cy = 0, sy = 0, vx = ?, vy = ?, vz = ?, hasSideEffects = 0 in 779multiclass RVM2m<string opcStr, bits<8> opc, RegisterClass RCM> { 780 def mm : RV<opc, (outs RCM:$vx), (ins RCM:$vy, RCM:$vz), 781 !strconcat(opcStr, " $vx, $vy, $vz")>; 782} 783// Generic RV multiclass for mask calculation with 1 argument. 784// e.g. NEGM 785let cy = 0, sy = 0, vx = ?, vy = ?, hasSideEffects = 0 in 786multiclass RVM1m<string opcStr, bits<8> opc, RegisterClass RCM> { 787 def m : RV<opc, (outs RCM:$vx), (ins RCM:$vy), 788 !strconcat(opcStr, " $vx, $vy")>; 789} 790// Generic RV multiclass for mask calculation with 1 argument. 791// e.g. PCVM, LZVM, and TOVM 792let cy = 0, sy = 0, vy = ?, hasSideEffects = 0, Uses = [VL] in 793multiclass RVMSbm<string opcStr, string argStr, bits<8>opc, dag dag_in> { 794 def "" : RV<opc, (outs I64:$sx), dag_in, 795 !strconcat(opcStr, " $sx,", argStr)> { 796 bits<7> sx; 797 let Inst{54-48} = sx; 798 } 799 let DisableEncoding = "$vl", isCodeGenOnly = 1, VE_VLInUse = 1 in { 800 def l : RV<opc, (outs I64:$sx), !con(dag_in, (ins I32:$vl)), 801 !strconcat(opcStr, " $sx,", argStr)> { 802 bits<7> sx; 803 let Inst{54-48} = sx; 804 } 805 def L : RV<opc, (outs I64:$sx), !con(dag_in, (ins VLS:$vl)), 806 !strconcat(opcStr, " $sx,", argStr)> { 807 bits<7> sx; 808 let Inst{54-48} = sx; 809 } 810 } 811} 812let VE_VLIndex = 2 in 813multiclass RVMSm<string opcStr, bits<8> opc, RegisterClass RCM> { 814 defm m : RVMSbm<opcStr, " $vy", opc, (ins RCM:$vy)>; 815} 816 817// Section 8.10.1 - VADD (Vector Add) 818let cx = 0, cx2 = 0 in 819defm VADDUL : RVm<"vaddu.l", 0xc8, V64, I64, VM>; 820let cx = 0, cx2 = 1 in { 821 defm PVADDULO : RVm<"pvaddu.lo", 0xc8, V64, I32, VM>; 822 let isCodeGenOnly = 1 in 823 defm VADDUW : RVm<"vaddu.w", 0xc8, V64, I32, VM>; 824} 825let cx = 1, cx2 = 0 in 826defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>; 827let cx = 1, cx2 = 1 in 828defm PVADDU : RVm<"pvaddu", 0xc8, V64, I64, VM512>; 829def : MnemonicAlias<"vaddu.w", "pvaddu.lo">; 830 831// Section 8.10.2 - VADS (Vector Add Single) 832let cx = 0, cx2 = 0 in 833defm VADDSWSX : RVm<"vadds.w.sx", 0xca, V64, I32, VM>; 834let cx = 0, cx2 = 1 in { 835 defm PVADDSLO : RVm<"pvadds.lo", 0xca, V64, I32, VM>; 836 let isCodeGenOnly = 1 in 837 defm VADDSWZX : RVm<"vadds.w.zx", 0xca, V64, I32, VM>; 838} 839let cx = 1, cx2 = 0 in 840defm PVADDSUP : RVm<"pvadds.up", 0xca, V64, I64, VM>; 841let cx = 1, cx2 = 1 in 842defm PVADDS : RVm<"pvadds", 0xca, V64, I64, VM512>; 843def : MnemonicAlias<"pvadds.lo.sx", "vadds.w.sx">; 844def : MnemonicAlias<"vadds.w.zx", "pvadds.lo">; 845def : MnemonicAlias<"vadds.w", "pvadds.lo">; 846def : MnemonicAlias<"pvadds.lo.zx", "pvadds.lo">; 847 848// Section 8.10.3 - VADX (Vector Add) 849defm VADDSL : RVm<"vadds.l", 0x8b, V64, I64, VM>; 850 851// Section 8.10.4 - VSUB (Vector Subtract) 852let cx = 0, cx2 = 0 in 853defm VSUBUL : RVm<"vsubu.l", 0xd8, V64, I64, VM>; 854let cx = 0, cx2 = 1 in { 855 defm PVSUBULO : RVm<"pvsubu.lo", 0xd8, V64, I32, VM>; 856 let isCodeGenOnly = 1 in 857 defm VSUBUW : RVm<"vsubu.w", 0xd8, V64, I32, VM>; 858} 859let cx = 1, cx2 = 0 in 860defm PVSUBUUP : RVm<"pvsubu.up", 0xd8, V64, I64, VM>; 861let cx = 1, cx2 = 1 in 862defm PVSUBU : RVm<"pvsubu", 0xd8, V64, I64, VM512>; 863def : MnemonicAlias<"vsubu.w", "pvsubu.lo">; 864 865// Section 8.10.5 - VSBS (Vector Subtract Single) 866let cx = 0, cx2 = 0 in 867defm VSUBSWSX : RVm<"vsubs.w.sx", 0xda, V64, I32, VM>; 868let cx = 0, cx2 = 1 in { 869 defm PVSUBSLO : RVm<"pvsubs.lo", 0xda, V64, I32, VM>; 870 let isCodeGenOnly = 1 in 871 defm VSUBSWZX : RVm<"vsubs.w.zx", 0xda, V64, I32, VM>; 872} 873let cx = 1, cx2 = 0 in 874defm PVSUBSUP : RVm<"pvsubs.up", 0xda, V64, I64, VM>; 875let cx = 1, cx2 = 1 in 876defm PVSUBS : RVm<"pvsubs", 0xda, V64, I64, VM512>; 877def : MnemonicAlias<"pvsubs.lo.sx", "vsubs.w.sx">; 878def : MnemonicAlias<"vsubs.w.zx", "pvsubs.lo">; 879def : MnemonicAlias<"vsubs.w", "pvsubs.lo">; 880def : MnemonicAlias<"pvsubs.lo.zx", "pvsubs.lo">; 881 882// Section 8.10.6 - VSBX (Vector Subtract) 883defm VSUBSL : RVm<"vsubs.l", 0x9b, V64, I64, VM>; 884 885// Section 8.10.7 - VMPY (Vector Multiply) 886let cx2 = 0 in 887defm VMULUL : RVm<"vmulu.l", 0xc9, V64, I64, VM>; 888let cx2 = 1 in 889defm VMULUW : RVm<"vmulu.w", 0xc9, V64, I32, VM>; 890 891// Section 8.10.8 - VMPS (Vector Multiply Single) 892let cx2 = 0 in 893defm VMULSWSX : RVm<"vmuls.w.sx", 0xcb, V64, I32, VM>; 894let cx2 = 1 in 895defm VMULSWZX : RVm<"vmuls.w.zx", 0xcb, V64, I32, VM>; 896def : MnemonicAlias<"vmuls.w", "vmuls.w.zx">; 897 898// Section 8.10.9 - VMPX (Vector Multiply) 899defm VMULSL : RVm<"vmuls.l", 0xdb, V64, I64, VM>; 900 901// Section 8.10.10 - VMPD (Vector Multiply) 902defm VMULSLW : RVm<"vmuls.l.w", 0xd9, V64, I32, VM>; 903 904// Section 8.10.11 - VDIV (Vector Divide) 905let cx2 = 0 in 906defm VDIVUL : RVDIVm<"vdivu.l", 0xe9, V64, I64, VM>; 907let cx2 = 1 in 908defm VDIVUW : RVDIVm<"vdivu.w", 0xe9, V64, I32, VM>; 909 910// Section 8.10.12 - VDVS (Vector Divide Single) 911let cx2 = 0 in 912defm VDIVSWSX : RVDIVm<"vdivs.w.sx", 0xeb, V64, I32, VM>; 913let cx2 = 1 in 914defm VDIVSWZX : RVDIVm<"vdivs.w.zx", 0xeb, V64, I32, VM>; 915def : MnemonicAlias<"vdivs.w", "vdivs.w.zx">; 916 917// Section 8.10.13 - VDVX (Vector Divide) 918defm VDIVSL : RVDIVm<"vdivs.l", 0xfb, V64, I64, VM>; 919 920// Section 8.10.14 - VCMP (Vector Compare) 921let cx = 0, cx2 = 0 in 922defm VCMPUL : RVm<"vcmpu.l", 0xb9, V64, I64, VM>; 923let cx = 0, cx2 = 1 in { 924 defm PVCMPULO : RVm<"pvcmpu.lo", 0xb9, V64, I32, VM>; 925 let isCodeGenOnly = 1 in 926 defm VCMPUW : RVm<"vcmpu.w", 0xb9, V64, I32, VM>; 927} 928let cx = 1, cx2 = 0 in 929defm PVCMPUUP : RVm<"pvcmpu.up", 0xb9, V64, I64, VM>; 930let cx = 1, cx2 = 1 in 931defm PVCMPU : RVm<"pvcmpu", 0xb9, V64, I64, VM512>; 932def : MnemonicAlias<"vcmpu.w", "pvcmpu.lo">; 933 934// Section 8.10.15 - VCPS (Vector Compare Single) 935let cx = 0, cx2 = 0 in 936defm VCMPSWSX : RVm<"vcmps.w.sx", 0xfa, V64, I32, VM>; 937let cx = 0, cx2 = 1 in { 938 defm PVCMPSLO : RVm<"pvcmps.lo", 0xfa, V64, I32, VM>; 939 let isCodeGenOnly = 1 in 940 defm VCMPSWZX : RVm<"vcmps.w.zx", 0xfa, V64, I32, VM>; 941} 942let cx = 1, cx2 = 0 in 943defm PVCMPSUP : RVm<"pvcmps.up", 0xfa, V64, I64, VM>; 944let cx = 1, cx2 = 1 in 945defm PVCMPS : RVm<"pvcmps", 0xfa, V64, I64, VM512>; 946def : MnemonicAlias<"pvcmps.lo.sx", "vcmps.w.sx">; 947def : MnemonicAlias<"vcmps.w.zx", "pvcmps.lo">; 948def : MnemonicAlias<"vcmps.w", "pvcmps.lo">; 949def : MnemonicAlias<"pvcmps.lo.zx", "pvcmps.lo">; 950 951// Section 8.10.16 - VCPX (Vector Compare) 952defm VCMPSL : RVm<"vcmps.l", 0xba, V64, I64, VM>; 953 954// Section 8.10.17 - VCMS (Vector Compare and Select Maximum/Minimum Single) 955let cx = 0, cx2 = 0 in 956defm VMAXSWSX : RVm<"vmaxs.w.sx", 0x8a, V64, I32, VM>; 957let cx = 0, cx2 = 1 in { 958 defm PVMAXSLO : RVm<"pvmaxs.lo", 0x8a, V64, I32, VM>; 959 let isCodeGenOnly = 1 in 960 defm VMAXSWZX : RVm<"vmaxs.w.zx", 0x8a, V64, I32, VM>; 961} 962let cx = 1, cx2 = 0 in 963defm PVMAXSUP : RVm<"pvmaxs.up", 0x8a, V64, I64, VM>; 964let cx = 1, cx2 = 1 in 965defm PVMAXS : RVm<"pvmaxs", 0x8a, V64, I64, VM512>; 966let cs2 = 1 in { 967 let cx = 0, cx2 = 0 in 968 defm VMINSWSX : RVm<"vmins.w.sx", 0x8a, V64, I32, VM>; 969 let cx = 0, cx2 = 1 in { 970 defm PVMINSLO : RVm<"pvmins.lo", 0x8a, V64, I32, VM>; 971 let isCodeGenOnly = 1 in 972 defm VMINSWZX : RVm<"vmins.w.zx", 0x8a, V64, I32, VM>; 973 } 974 let cx = 1, cx2 = 0 in 975 defm PVMINSUP : RVm<"pvmins.up", 0x8a, V64, I64, VM>; 976 let cx = 1, cx2 = 1 in 977 defm PVMINS : RVm<"pvmins", 0x8a, V64, I64, VM512>; 978} 979def : MnemonicAlias<"pvmaxs.lo.sx", "vmaxs.w.sx">; 980def : MnemonicAlias<"vmaxs.w.zx", "pvmaxs.lo">; 981def : MnemonicAlias<"vmaxs.w", "pvmaxs.lo">; 982def : MnemonicAlias<"pvmaxs.lo.zx", "pvmaxs.lo">; 983def : MnemonicAlias<"pvmins.lo.sx", "vmins.w.sx">; 984def : MnemonicAlias<"vmins.w.zx", "pvmins.lo">; 985def : MnemonicAlias<"vmins.w", "pvmins.lo">; 986def : MnemonicAlias<"pvmins.lo.zx", "pvmins.lo">; 987 988// Section 8.10.18 - VCMX (Vector Compare and Select Maximum/Minimum) 989defm VMAXSL : RVm<"vmaxs.l", 0x9a, V64, I64, VM>; 990let cs2 = 1 in 991defm VMINSL : RVm<"vmins.l", 0x9a, V64, I64, VM>; 992 993//----------------------------------------------------------------------------- 994// Section 8.11 - Vector Logical Operation Instructions 995//----------------------------------------------------------------------------- 996 997// Section 8.11.1 - VAND (Vector And) 998let cx = 0, cx2 = 0 in defm VAND : RVLm<"vand", 0xc4, I64, V64, VM>; 999let cx = 0, cx2 = 1 in defm PVANDLO : RVLm<"pvand.lo", 0xc4, I32, V64, VM>; 1000let cx = 1, cx2 = 0 in defm PVANDUP : RVLm<"pvand.up", 0xc4, F32, V64, VM>; 1001let cx = 1, cx2 = 1 in defm PVAND : RVLm<"pvand", 0xc4, I64, V64, VM512>; 1002 1003// Section 8.11.2 - VOR (Vector Or) 1004let cx = 0, cx2 = 0 in defm VOR : RVLm<"vor", 0xc5, I64, V64, VM>; 1005let cx = 0, cx2 = 1 in defm PVORLO : RVLm<"pvor.lo", 0xc5, I32, V64, VM>; 1006let cx = 1, cx2 = 0 in defm PVORUP : RVLm<"pvor.up", 0xc5, F32, V64, VM>; 1007let cx = 1, cx2 = 1 in defm PVOR : RVLm<"pvor", 0xc5, I64, V64, VM512>; 1008 1009// Section 8.11.3 - VXOR (Vector Exclusive Or) 1010let cx = 0, cx2 = 0 in defm VXOR : RVLm<"vxor", 0xc6, I64, V64, VM>; 1011let cx = 0, cx2 = 1 in defm PVXORLO : RVLm<"pvxor.lo", 0xc6, I32, V64, VM>; 1012let cx = 1, cx2 = 0 in defm PVXORUP : RVLm<"pvxor.up", 0xc6, F32, V64, VM>; 1013let cx = 1, cx2 = 1 in defm PVXOR : RVLm<"pvxor", 0xc6, I64, V64, VM512>; 1014 1015// Section 8.11.4 - VEQV (Vector Equivalence) 1016let cx = 0, cx2 = 0 in defm VEQV : RVLm<"veqv", 0xc7, I64, V64, VM>; 1017let cx = 0, cx2 = 1 in defm PVEQVLO : RVLm<"pveqv.lo", 0xc7, I32, V64, VM>; 1018let cx = 1, cx2 = 0 in defm PVEQVUP : RVLm<"pveqv.up", 0xc7, F32, V64, VM>; 1019let cx = 1, cx2 = 1 in defm PVEQV : RVLm<"pveqv", 0xc7, I64, V64, VM512>; 1020 1021// Section 8.11.5 - VLDZ (Vector Leading Zero Count) 1022let cx = 0, cx2 = 0 in defm VLDZ : RV1m<"vldz", 0xe7, V64, VM>; 1023let cx = 0, cx2 = 1 in defm PVLDZLO : RV1m<"pvldz.lo", 0xe7, V64, VM>; 1024let cx = 1, cx2 = 0 in defm PVLDZUP : RV1m<"pvldz.up", 0xe7, V64, VM>; 1025let cx = 1, cx2 = 1 in defm PVLDZ : RV1m<"pvldz", 0xe7, V64, VM512>; 1026 1027// Section 8.11.6 - VPCNT (Vector Population Count) 1028let cx = 0, cx2 = 0 in defm VPCNT : RV1m<"vpcnt", 0xac, V64, VM>; 1029let cx = 0, cx2 = 1 in defm PVPCNTLO : RV1m<"pvpcnt.lo", 0xac, V64, VM>; 1030let cx = 1, cx2 = 0 in defm PVPCNTUP : RV1m<"pvpcnt.up", 0xac, V64, VM>; 1031let cx = 1, cx2 = 1 in defm PVPCNT : RV1m<"pvpcnt", 0xac, V64, VM512>; 1032 1033// Section 8.11.7 - VBRV (Vector Bit Reverse) 1034let cx = 0, cx2 = 0 in defm VBRV : RV1m<"vbrv", 0xf7, V64, VM>; 1035let cx = 0, cx2 = 1 in defm PVBRVLO : RV1m<"pvbrv.lo", 0xf7, V64, VM>; 1036let cx = 1, cx2 = 0 in defm PVBRVUP : RV1m<"pvbrv.up", 0xf7, V64, VM>; 1037let cx = 1, cx2 = 1 in defm PVBRV : RV1m<"pvbrv", 0xf7, V64, VM512>; 1038 1039// Section 8.11.8 - VSEQ (Vector Sequential Number) 1040let cx = 0, cx2 = 0 in defm VSEQ : RV0m<"vseq", 0x99, V64, VM>; 1041let cx = 0, cx2 = 1 in defm PVSEQLO : RV0m<"pvseq.lo", 0x99, V64, VM>; 1042let cx = 1, cx2 = 0 in defm PVSEQUP : RV0m<"pvseq.up", 0x99, V64, VM>; 1043let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512>; 1044 1045//----------------------------------------------------------------------------- 1046// Section 8.12 - Vector Shift Operation Instructions 1047//----------------------------------------------------------------------------- 1048 1049// Section 8.12.1 - VSLL (Vector Shift Left Logical) 1050let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM>; 1051let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM>; 1052let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>; 1053let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512>; 1054 1055// Section 8.12.2 - VSLD (Vector Shift Left Double) 1056defm VSLD : RVSDm<"vsld", 0xe4, V64, VM>; 1057 1058// Section 8.12.3 - VSRL (Vector Shift Right Logical) 1059let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>; 1060let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM>; 1061let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>; 1062let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512>; 1063 1064// Section 8.12.4 - VSRD (Vector Shift Right Double) 1065defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>; 1066 1067// Section 8.12.5 - VSLA (Vector Shift Left Arithmetic) 1068let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>; 1069let cx = 0, cx2 = 1 in { 1070 defm PVSLALO : RVSm<"pvsla.lo", 0xe6, I32, V64, VM>; 1071 let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM>; 1072} 1073let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>; 1074let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512>; 1075def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">; 1076def : MnemonicAlias<"vsla.w.zx", "pvsla.lo">; 1077def : MnemonicAlias<"vsla.w", "pvsla.lo">; 1078def : MnemonicAlias<"pvsla.lo.zx", "pvsla.lo">; 1079 1080// Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic) 1081defm VSLAL : RVSm<"vsla.l", 0xd4, I64, V64, VM>; 1082 1083// Section 8.12.7 - VSRA (Vector Shift Right Arithmetic) 1084let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>; 1085let cx = 0, cx2 = 1 in { 1086 defm PVSRALO : RVSm<"pvsra.lo", 0xf6, I32, V64, VM>; 1087 let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM>; 1088} 1089let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>; 1090let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512>; 1091def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">; 1092def : MnemonicAlias<"vsra.w.zx", "pvsra.lo">; 1093def : MnemonicAlias<"vsra.w", "pvsra.lo">; 1094def : MnemonicAlias<"pvsra.lo.zx", "pvsra.lo">; 1095 1096// Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic) 1097defm VSRAL : RVSm<"vsra.l", 0xd5, I64, V64, VM>; 1098 1099// Section 8.12.9 - VSFA (Vector Shift Left and Add) 1100defm VSFA : RVSAm<"vsfa", 0xd7, V64, VM>; 1101 1102//----------------------------------------------------------------------------- 1103// Section 8.13 - Vector Floating-Point Arithmetic Instructions 1104//----------------------------------------------------------------------------- 1105 1106// Section 8.13.1 - VFAD (Vector Floating Add) 1107let cx = 0, cx2 = 0 in 1108defm VFADDD : RVm<"vfadd.d", 0xcc, V64, I64, VM, simm7fp>; 1109let cx = 0, cx2 = 1 in 1110defm PVFADDLO : RVm<"pvfadd.lo", 0xcc, V64, I64, VM, simm7fp>; 1111let cx = 1, cx2 = 0 in { 1112 defm PVFADDUP : RVm<"pvfadd.up", 0xcc, V64, F32, VM, simm7fp>; 1113 let isCodeGenOnly = 1 in 1114 defm VFADDS : RVm<"vfadd.s", 0xcc, V64, F32, VM, simm7fp>; 1115} 1116let cx = 1, cx2 = 1 in 1117defm PVFADD : RVm<"pvfadd", 0xcc, V64, I64, VM512, simm7fp>; 1118def : MnemonicAlias<"vfadd.s", "pvfadd.up">; 1119 1120// Section 8.13.2 - VFSB (Vector Floating Subtract) 1121let cx = 0, cx2 = 0 in 1122defm VFSUBD : RVm<"vfsub.d", 0xdc, V64, I64, VM, simm7fp>; 1123let cx = 0, cx2 = 1 in 1124defm PVFSUBLO : RVm<"pvfsub.lo", 0xdc, V64, I64, VM, simm7fp>; 1125let cx = 1, cx2 = 0 in { 1126 defm PVFSUBUP : RVm<"pvfsub.up", 0xdc, V64, F32, VM, simm7fp>; 1127 let isCodeGenOnly = 1 in 1128 defm VFSUBS : RVm<"vfsub.s", 0xdc, V64, F32, VM, simm7fp>; 1129} 1130let cx = 1, cx2 = 1 in 1131defm PVFSUB : RVm<"pvfsub", 0xdc, V64, I64, VM512, simm7fp>; 1132def : MnemonicAlias<"vfsub.s", "pvfsub.up">; 1133 1134// Section 8.13.3 - VFMP (Vector Floating Multiply) 1135let cx = 0, cx2 = 0 in 1136defm VFMULD : RVm<"vfmul.d", 0xcd, V64, I64, VM, simm7fp>; 1137let cx = 0, cx2 = 1 in 1138defm PVFMULLO : RVm<"pvfmul.lo", 0xcd, V64, I64, VM, simm7fp>; 1139let cx = 1, cx2 = 0 in { 1140 defm PVFMULUP : RVm<"pvfmul.up", 0xcd, V64, F32, VM, simm7fp>; 1141 let isCodeGenOnly = 1 in 1142 defm VFMULS : RVm<"vfmul.s", 0xcd, V64, F32, VM, simm7fp>; 1143} 1144let cx = 1, cx2 = 1 in 1145defm PVFMUL : RVm<"pvfmul", 0xcd, V64, I64, VM512, simm7fp>; 1146def : MnemonicAlias<"vfmul.s", "pvfmul.up">; 1147 1148// Section 8.13.4 - VFDV (Vector Floating Divide) 1149defm VFDIVD : RVDIVm<"vfdiv.d", 0xdd, V64, I64, VM, simm7fp>; 1150let cx = 1 in 1151defm VFDIVS : RVDIVm<"vfdiv.s", 0xdd, V64, F32, VM, simm7fp>; 1152 1153// Section 8.13.5 - VFSQRT (Vector Floating Square Root) 1154defm VFSQRTD : RVF1m<"vfsqrt.d", 0xed, V64, VM>; 1155let cx = 1 in 1156defm VFSQRTS : RVF1m<"vfsqrt.s", 0xed, V64, VM>; 1157 1158// Section 8.13.6 - VFCP (Vector Floating Compare) 1159let cx = 0, cx2 = 0 in 1160defm VFCMPD : RVm<"vfcmp.d", 0xfc, V64, I64, VM, simm7fp>; 1161let cx = 0, cx2 = 1 in 1162defm PVFCMPLO : RVm<"pvfcmp.lo", 0xfc, V64, I64, VM, simm7fp>; 1163let cx = 1, cx2 = 0 in { 1164 defm PVFCMPUP : RVm<"pvfcmp.up", 0xfc, V64, F32, VM, simm7fp>; 1165 let isCodeGenOnly = 1 in 1166 defm VFCMPS : RVm<"vfcmp.s", 0xfc, V64, F32, VM, simm7fp>; 1167} 1168let cx = 1, cx2 = 1 in 1169defm PVFCMP : RVm<"pvfcmp", 0xfc, V64, I64, VM512, simm7fp>; 1170def : MnemonicAlias<"vfcmp.s", "pvfcmp.up">; 1171 1172// Section 8.13.7 - VFCM (Vector Floating Compare and Select Maximum/Minimum) 1173let cx = 0, cx2 = 0 in 1174defm VFMAXD : RVm<"vfmax.d", 0xbd, V64, I64, VM, simm7fp>; 1175let cx = 0, cx2 = 1 in 1176defm PVFMAXLO : RVm<"pvfmax.lo", 0xbd, V64, I64, VM, simm7fp>; 1177let cx = 1, cx2 = 0 in { 1178 defm PVFMAXUP : RVm<"pvfmax.up", 0xbd, V64, F32, VM, simm7fp>; 1179 let isCodeGenOnly = 1 in 1180 defm VFMAXS : RVm<"vfmax.s", 0xbd, V64, F32, VM, simm7fp>; 1181} 1182let cx = 1, cx2 = 1 in 1183defm PVFMAX : RVm<"pvfmax", 0xbd, V64, I64, VM512, simm7fp>; 1184let cs2 = 1 in { 1185 let cx = 0, cx2 = 0 in 1186 defm VFMIND : RVm<"vfmin.d", 0xbd, V64, I64, VM, simm7fp>; 1187 let cx = 0, cx2 = 1 in 1188 defm PVFMINLO : RVm<"pvfmin.lo", 0xbd, V64, I64, VM, simm7fp>; 1189 let cx = 1, cx2 = 0 in { 1190 defm PVFMINUP : RVm<"pvfmin.up", 0xbd, V64, F32, VM, simm7fp>; 1191 let isCodeGenOnly = 1 in 1192 defm VFMINS : RVm<"vfmin.s", 0xbd, V64, F32, VM, simm7fp>; 1193 } 1194 let cx = 1, cx2 = 1 in 1195 defm PVFMIN : RVm<"pvfmin", 0xbd, V64, I64, VM512, simm7fp>; 1196} 1197def : MnemonicAlias<"vfmax.s", "pvfmax.up">; 1198def : MnemonicAlias<"vfmin.s", "pvfmin.up">; 1199 1200// Section 8.13.8 - VFMAD (Vector Floating Fused Multiply Add) 1201let cx = 0, cx2 = 0 in 1202defm VFMADD : RVMm<"vfmad.d", 0xe2, V64, I64, VM, simm7fp>; 1203let cx = 0, cx2 = 1 in 1204defm PVFMADLO : RVMm<"pvfmad.lo", 0xe2, V64, I64, VM, simm7fp>; 1205let cx = 1, cx2 = 0 in { 1206 defm PVFMADUP : RVMm<"pvfmad.up", 0xe2, V64, F32, VM, simm7fp>; 1207 let isCodeGenOnly = 1 in 1208 defm VFMADS : RVMm<"vfmad.s", 0xe2, V64, F32, VM, simm7fp>; 1209} 1210let cx = 1, cx2 = 1 in 1211defm PVFMAD : RVMm<"pvfmad", 0xe2, V64, I64, VM512, simm7fp>; 1212def : MnemonicAlias<"vfmad.s", "pvfmad.up">; 1213 1214// Section 8.13.9 - VFMSB (Vector Floating Fused Multiply Subtract) 1215let cx = 0, cx2 = 0 in 1216defm VFMSBD : RVMm<"vfmsb.d", 0xf2, V64, I64, VM, simm7fp>; 1217let cx = 0, cx2 = 1 in 1218defm PVFMSBLO : RVMm<"pvfmsb.lo", 0xf2, V64, I64, VM, simm7fp>; 1219let cx = 1, cx2 = 0 in { 1220 defm PVFMSBUP : RVMm<"pvfmsb.up", 0xf2, V64, F32, VM, simm7fp>; 1221 let isCodeGenOnly = 1 in 1222 defm VFMSBS : RVMm<"vfmsb.s", 0xf2, V64, F32, VM, simm7fp>; 1223} 1224let cx = 1, cx2 = 1 in 1225defm PVFMSB : RVMm<"pvfmsb", 0xf2, V64, I64, VM512, simm7fp>; 1226def : MnemonicAlias<"vfmsb.s", "pvfmsb.up">; 1227 1228// Section 8.13.10 - VFNMAD (Vector Floating Fused Negative Multiply Add) 1229let cx = 0, cx2 = 0 in 1230defm VFNMADD : RVMm<"vfnmad.d", 0xe3, V64, I64, VM, simm7fp>; 1231let cx = 0, cx2 = 1 in 1232defm PVFNMADLO : RVMm<"pvfnmad.lo", 0xe3, V64, I64, VM, simm7fp>; 1233let cx = 1, cx2 = 0 in { 1234 defm PVFNMADUP : RVMm<"pvfnmad.up", 0xe3, V64, F32, VM, simm7fp>; 1235 let isCodeGenOnly = 1 in 1236 defm VFNMADS : RVMm<"vfnmad.s", 0xe3, V64, F32, VM, simm7fp>; 1237} 1238let cx = 1, cx2 = 1 in 1239defm PVFNMAD : RVMm<"pvfnmad", 0xe3, V64, I64, VM512, simm7fp>; 1240def : MnemonicAlias<"vfnmad.s", "pvfnmad.up">; 1241 1242// Section 8.13.11 - VFNMSB (Vector Floating Fused Negative Multiply Subtract) 1243let cx = 0, cx2 = 0 in 1244defm VFNMSBD : RVMm<"vfnmsb.d", 0xf3, V64, I64, VM, simm7fp>; 1245let cx = 0, cx2 = 1 in 1246defm PVFNMSBLO : RVMm<"pvfnmsb.lo", 0xf3, V64, I64, VM, simm7fp>; 1247let cx = 1, cx2 = 0 in { 1248 defm PVFNMSBUP : RVMm<"pvfnmsb.up", 0xf3, V64, F32, VM, simm7fp>; 1249 let isCodeGenOnly = 1 in 1250 defm VFNMSBS : RVMm<"vfnmsb.s", 0xf3, V64, F32, VM, simm7fp>; 1251} 1252let cx = 1, cx2 = 1 in 1253defm PVFNMSB : RVMm<"pvfnmsb", 0xf3, V64, I64, VM512, simm7fp>; 1254def : MnemonicAlias<"vfnmsb.s", "pvfnmsb.up">; 1255 1256// Section 8.13.12 - VRCP (Vector Floating Reciprocal) 1257let cx = 0, cx2 = 0 in defm VRCPD : RVF1m<"vrcp.d", 0xe1, V64, VM>; 1258let cx = 0, cx2 = 1 in defm PVRCPLO : RVF1m<"pvrcp.lo", 0xe1, V64, VM>; 1259let cx = 1, cx2 = 0 in { 1260 defm PVRCPUP : RVF1m<"pvrcp.up", 0xe1, V64, VM>; 1261 let isCodeGenOnly = 1 in defm VRCPS : RVF1m<"vrcp.s", 0xe1, V64, VM>; 1262} 1263let cx = 1, cx2 = 1 in defm PVRCP : RVF1m<"pvrcp", 0xe1, V64, VM512>; 1264def : MnemonicAlias<"vrcp.s", "pvrcp.up">; 1265 1266// Section 8.13.13 - VRSQRT (Vector Floating Reciprocal Square Root) 1267let cx = 0, cx2 = 0 in defm VRSQRTD : RVF1m<"vrsqrt.d", 0xf1, V64, VM>; 1268let cx = 0, cx2 = 1 in defm PVRSQRTLO : RVF1m<"pvrsqrt.lo", 0xf1, V64, VM>; 1269let cx = 1, cx2 = 0 in { 1270 defm PVRSQRTUP : RVF1m<"pvrsqrt.up", 0xf1, V64, VM>; 1271 let isCodeGenOnly = 1 in 1272 defm VRSQRTS : RVF1m<"vrsqrt.s", 0xf1, V64, VM>; 1273} 1274let cx = 1, cx2 = 1 in 1275defm PVRSQRT : RVF1m<"pvrsqrt", 0xf1, V64, VM512>; 1276let cs2 = 1 in { 1277 let cx = 0, cx2 = 0 in 1278 defm VRSQRTDNEX : RVF1m<"vrsqrt.d.nex", 0xf1, V64, VM>; 1279 let cx = 0, cx2 = 1 in 1280 defm PVRSQRTLONEX : RVF1m<"pvrsqrt.lo.nex", 0xf1, V64, VM>; 1281 let cx = 1, cx2 = 0 in { 1282 defm PVRSQRTUPNEX : RVF1m<"pvrsqrt.up.nex", 0xf1, V64, VM>; 1283 let isCodeGenOnly = 1 in 1284 defm VRSQRTSNEX : RVF1m<"vrsqrt.s.nex", 0xf1, V64, VM>; 1285 } 1286 let cx = 1, cx2 = 1 in 1287 defm PVRSQRTNEX : RVF1m<"pvrsqrt.nex", 0xf1, V64, VM512>; 1288} 1289def : MnemonicAlias<"vrsqrt.s", "pvrsqrt.up">; 1290def : MnemonicAlias<"vrsqrt.s.nex", "pvrsqrt.up.nex">; 1291 1292// Section 8.13.14 - VFIX (Vector Convert to Fixed Pointer) 1293let cx = 0, cx2 = 0, cs2 = 0 in 1294defm VCVTWDSX : RVFIXm<"vcvt.w.d.sx", 0xe8, V64, VM>; 1295let cx = 0, cx2 = 1, cs2 = 0 in 1296defm VCVTWDZX : RVFIXm<"vcvt.w.d.zx", 0xe8, V64, VM>; 1297let cx = 1, cx2 = 0, cs2 = 0 in 1298defm VCVTWSSX : RVFIXm<"vcvt.w.s.sx", 0xe8, V64, VM>; 1299let cx = 1, cx2 = 1, cs2 = 0 in 1300defm VCVTWSZX : RVFIXm<"vcvt.w.s.zx", 0xe8, V64, VM>; 1301let cx = 0, cx2 = 1, cs2 = 1 in 1302defm PVCVTWSLO : RVFIXm<"pvcvt.w.s.lo", 0xe8, V64, VM>; 1303let cx = 1, cx2 = 0, cs2 = 1 in 1304defm PVCVTWSUP : RVFIXm<"pvcvt.w.s.up", 0xe8, V64, VM>; 1305let cx = 1, cx2 = 1, cs2 = 1 in 1306defm PVCVTWS : RVFIXm<"pvcvt.w.s", 0xe8, V64, VM512>; 1307 1308// Section 8.13.15 - VFIXX (Vector Convert to Fixed Pointer) 1309defm VCVTLD : RVFIXm<"vcvt.l.d", 0xa8, V64, VM>; 1310 1311// Section 8.13.16 - VFLT (Vector Convert to Floating Pointer) 1312let cx = 0, cx2 = 0, cs2 = 0 in 1313defm VCVTDW : RVF1m<"vcvt.d.w", 0xf8, V64, VM>; 1314let cx = 1, cx2 = 0, cs2 = 0 in 1315defm VCVTSW : RVF1m<"vcvt.s.w", 0xf8, V64, VM>; 1316let cx = 0, cx2 = 1, cs2 = 1 in 1317defm PVCVTSWLO : RVF1m<"pvcvt.s.w.lo", 0xf8, V64, VM>; 1318let cx = 1, cx2 = 0, cs2 = 1 in 1319defm PVCVTSWUP : RVF1m<"pvcvt.s.w.up", 0xf8, V64, VM>; 1320let cx = 1, cx2 = 1, cs2 = 1 in 1321defm PVCVTSW : RVF1m<"pvcvt.s.w", 0xf8, V64, VM512>; 1322 1323// Section 8.13.17 - VFLTX (Vector Convert to Floating Pointer) 1324defm VCVTDL : RVF1m<"vcvt.d.l", 0xb8, V64, VM>; 1325 1326// Section 8.13.18 - VCVS (Vector Convert to Single-format) 1327defm VCVTSD : RVF1m<"vcvt.s.d", 0x9f, V64, VM>; 1328 1329// Section 8.13.19 - VCVD (Vector Convert to Double-format) 1330defm VCVTDS : RVF1m<"vcvt.d.s", 0x8f, V64, VM>; 1331 1332//----------------------------------------------------------------------------- 1333// Section 8.14 - Vector Reduction Instructions 1334//----------------------------------------------------------------------------- 1335 1336// Section 8.14.1 - VSUMS (Vector Sum Single) 1337defm VSUMWSX : RVF1m<"vsum.w.sx", 0xea, V64, VM>; 1338let cx2 = 1 in defm VSUMWZX : RVF1m<"vsum.w.zx", 0xea, V64, VM>; 1339 1340// Section 8.14.2 - VSUMX (Vector Sum) 1341defm VSUML : RVF1m<"vsum.l", 0xaa, V64, VM>; 1342 1343// Section 8.14.3 - VFSUM (Vector Floating Sum) 1344defm VFSUMD : RVF1m<"vfsum.d", 0xec, V64, VM>; 1345let cx = 1 in defm VFSUMS : RVF1m<"vfsum.s", 0xec, V64, VM>; 1346 1347// Section 8.14.4 - VMAXS (Vector Maximum/Minimum Single) 1348let cx2 = 0 in defm VRMAXSWFSTSX : RVF1m<"vrmaxs.w.fst.sx", 0xbb, V64, VM>; 1349let cx2 = 1 in defm VRMAXSWFSTZX : RVF1m<"vrmaxs.w.fst.zx", 0xbb, V64, VM>; 1350let cs = 1 in { 1351 let cx2 = 0 in 1352 defm VRMAXSWLSTSX : RVF1m<"vrmaxs.w.lst.sx", 0xbb, V64, VM>; 1353 let cx2 = 1 in 1354 defm VRMAXSWLSTZX : RVF1m<"vrmaxs.w.lst.zx", 0xbb, V64, VM>; 1355} 1356let cs2 = 1 in { 1357 let cx2 = 0 in 1358 defm VRMINSWFSTSX : RVF1m<"vrmins.w.fst.sx", 0xbb, V64, VM>; 1359 let cx2 = 1 in 1360 defm VRMINSWFSTZX : RVF1m<"vrmins.w.fst.zx", 0xbb, V64, VM>; 1361 let cs = 1 in { 1362 let cx2 = 0 in 1363 defm VRMINSWLSTSX : RVF1m<"vrmins.w.lst.sx", 0xbb, V64, VM>; 1364 let cx2 = 1 in 1365 defm VRMINSWLSTZX : RVF1m<"vrmins.w.lst.zx", 0xbb, V64, VM>; 1366 } 1367} 1368 1369// Section 8.14.5 - VMAXX (Vector Maximum/Minimum) 1370let cs = 0 in defm VRMAXSLFST : RVF1m<"vrmaxs.l.fst", 0xab, V64, VM>; 1371let cs = 1 in defm VRMAXSLLST : RVF1m<"vrmaxs.l.lst", 0xab, V64, VM>; 1372let cs2 = 1 in { 1373 let cs = 0 in defm VRMINSLFST : RVF1m<"vrmins.l.fst", 0xab, V64, VM>; 1374 let cs = 1 in defm VRMINSLLST : RVF1m<"vrmins.l.lst", 0xab, V64, VM>; 1375} 1376 1377// Section 8.14.6 - VFMAX (Vector Floating Maximum/Minimum) 1378let cs = 0 in defm VFRMAXDFST : RVF1m<"vfrmax.d.fst", 0xad, V64, VM>; 1379let cs = 1 in defm VFRMAXDLST : RVF1m<"vfrmax.d.lst", 0xad, V64, VM>; 1380let cs2 = 1 in { 1381 let cs = 0 in defm VFRMINDFST : RVF1m<"vfrmin.d.fst", 0xad, V64, VM>; 1382 let cs = 1 in defm VFRMINDLST : RVF1m<"vfrmin.d.lst", 0xad, V64, VM>; 1383} 1384let cx = 1 in { 1385 let cs = 0 in defm VFRMAXSFST : RVF1m<"vfrmax.s.fst", 0xad, V64, VM>; 1386 let cs = 1 in defm VFRMAXSLST : RVF1m<"vfrmax.s.lst", 0xad, V64, VM>; 1387 let cs2 = 1 in { 1388 let cs = 0 in defm VFRMINSFST : RVF1m<"vfrmin.s.fst", 0xad, V64, VM>; 1389 let cs = 1 in defm VFRMINSLST : RVF1m<"vfrmin.s.lst", 0xad, V64, VM>; 1390 } 1391} 1392 1393// Section 8.14.7 - VRAND (Vector Reduction And) 1394defm VRAND : RVF1m<"vrand", 0x88, V64, VM>; 1395 1396// Section 8.14.8 - VROR (Vector Reduction Or) 1397defm VROR : RVF1m<"vror", 0x98, V64, VM>; 1398 1399// Section 8.14.9 - VRXOR (Vector Reduction Exclusive Or) 1400defm VRXOR : RVF1m<"vrxor", 0x89, V64, VM>; 1401 1402//----------------------------------------------------------------------------- 1403// Section 8.15 - Vector Iterative Operation Instructions 1404//----------------------------------------------------------------------------- 1405 1406// Section 8.15.1 - VFIA (Vector Floating Iteration Add) 1407let cx = 0 in defm VFIAD : RVI2m<"vfia.d", 0xce, V64, I64>; 1408let cx = 1 in defm VFIAS : RVI2m<"vfia.s", 0xce, V64, F32>; 1409 1410// Section 8.15.2 - VFIS (Vector Floating Iteration Subtract) 1411let cx = 0 in defm VFISD : RVI2m<"vfis.d", 0xde, V64, I64>; 1412let cx = 1 in defm VFISS : RVI2m<"vfis.s", 0xde, V64, F32>; 1413 1414// Section 8.15.3 - VFIM (Vector Floating Iteration Multiply) 1415let cx = 0 in defm VFIMD : RVI2m<"vfim.d", 0xcf, V64, I64>; 1416let cx = 1 in defm VFIMS : RVI2m<"vfim.s", 0xcf, V64, F32>; 1417 1418// Section 8.15.4 - VFIAM (Vector Floating Iteration Add and Multiply) 1419let cx = 0 in defm VFIAMD : RVI3m<"vfiam.d", 0xee, V64, I64>; 1420let cx = 1 in defm VFIAMS : RVI3m<"vfiam.s", 0xee, V64, F32>; 1421 1422// Section 8.15.5 - VFISM (Vector Floating Iteration Subtract and Multiply) 1423let cx = 0 in defm VFISMD : RVI3m<"vfism.d", 0xfe, V64, I64>; 1424let cx = 1 in defm VFISMS : RVI3m<"vfism.s", 0xfe, V64, F32>; 1425 1426// Section 8.15.6 - VFIMA (Vector Floating Iteration Multiply and Add) 1427let cx = 0 in defm VFIMAD : RVI3m<"vfima.d", 0xef, V64, I64>; 1428let cx = 1 in defm VFIMAS : RVI3m<"vfima.s", 0xef, V64, F32>; 1429 1430// Section 8.15.7 - VFIMS (Vector Floating Iteration Multiply and Subtract) 1431let cx = 0 in defm VFIMSD : RVI3m<"vfims.d", 0xff, V64, I64>; 1432let cx = 1 in defm VFIMSS : RVI3m<"vfims.s", 0xff, V64, F32>; 1433 1434//----------------------------------------------------------------------------- 1435// Section 8.16 - Vector Merger Operation Instructions 1436//----------------------------------------------------------------------------- 1437 1438// Section 8.16.1 - VMRG (Vector Merge) 1439let cx = 0 in defm VMRG : RVm<"vmrg", 0xd6, V64, I64, VM>; 1440// FIXME: vmrg.w should be called as pvmrg, but following assembly manual. 1441let cx = 1 in defm VMRGW : RVm<"vmrg.w", 0xd6, V64, I64, VM512>; 1442def : MnemonicAlias<"vmrg.l", "vmrg">; 1443 1444// Section 8.16.2 - VSHF (Vector Shuffle) 1445defm VSHF : RVSHFm<"vshf", 0xbc, V64>; 1446 1447// Section 8.16.3 - VCP (Vector Compress) 1448defm VCP : RV1m<"vcp", 0x8d, V64, VM>; 1449 1450// Section 8.16.4 - VEX (Vector Expand) 1451defm VEX : RV1m<"vex", 0x9d, V64, VM>; 1452 1453//----------------------------------------------------------------------------- 1454// Section 8.17 - Vector Mask Operation Instructions 1455//----------------------------------------------------------------------------- 1456 1457// Section 8.17.1 - VFMK (Vector Form Mask) 1458defm VFMKL : RVMKm<"vfmk.l.", 0xb4, V64, VM>; 1459def : MnemonicAlias<"vfmk.l", "vfmk.l.at">; 1460 1461// Section 8.17.2 - VFMS (Vector Form Mask Single) 1462defm VFMKW : RVMKm<"vfmk.w.", 0xb5, V64, VM>; 1463let isCodeGenOnly = 1 in defm PVFMKWLO : RVMKm<"vfmk.w.", 0xb5, V64, VM>; 1464let cx = 1 in defm PVFMKWUP : RVMKm<"pvfmk.w.up.", 0xb5, V64, VM>; 1465def : MnemonicAlias<"vfmk.w", "vfmk.w.at">; 1466def : MnemonicAlias<"pvfmk.w.up", "pvfmk.w.up.at">; 1467def : MnemonicAlias<"pvfmk.w.lo", "vfmk.w.at">; 1468foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at" ] in { 1469 def : MnemonicAlias<"pvfmk.w.lo."#CC, "vfmk.w."#CC>; 1470} 1471 1472// Section 8.17.3 - VFMF (Vector Form Mask Floating Point) 1473defm VFMKD : RVMKm<"vfmk.d.", 0xb6, V64, VM>; 1474let cx2 = 1 in defm PVFMKSLO : RVMKm<"pvfmk.s.lo.", 0xb6, V64, VM>; 1475let cx = 1 in { 1476 defm PVFMKSUP : RVMKm<"pvfmk.s.up.", 0xb6, V64, VM>; 1477 let isCodeGenOnly = 1 in defm VFMKS : RVMKm<"vfmk.s.", 0xb6, V64, VM>; 1478} 1479def : MnemonicAlias<"vfmk.d", "vfmk.d.at">; 1480def : MnemonicAlias<"pvfmk.s.lo", "pvfmk.s.lo.at">; 1481def : MnemonicAlias<"pvfmk.s.up", "pvfmk.s.up.at">; 1482def : MnemonicAlias<"vfmk.s", "pvfmk.s.up.at">; 1483foreach CC = [ "af", "gt", "lt", "ne", "eq", "ge", "le", "at", "num", "nan", 1484 "gtnan", "ltnan", "nenan", "eqnan", "genan", "lenan" ] in { 1485 def : MnemonicAlias<"vfmk.s."#CC, "pvfmk.s.up."#CC>; 1486} 1487 1488// Section 8.17.4 - ANDM (And VM) 1489defm ANDM : RVM2m<"andm", 0x84, VM>; 1490 1491// Section 8.17.5 - ORM (Or VM) 1492defm ORM : RVM2m<"orm", 0x85, VM>; 1493 1494// Section 8.17.6 - XORM (Exclusive Or VM) 1495defm XORM : RVM2m<"xorm", 0x86, VM>; 1496 1497// Section 8.17.7 - EQVM (Equivalence VM) 1498defm EQVM : RVM2m<"eqvm", 0x87, VM>; 1499 1500// Section 8.17.8 - NNDM (Negate And VM) 1501defm NNDM : RVM2m<"nndm", 0x94, VM>; 1502 1503// Section 8.17.9 - NEGM (Negate VM) 1504defm NEGM : RVM1m<"negm", 0x95, VM>; 1505 1506// Section 8.17.10 - PCVM (Population Count of VM) 1507defm PCVM : RVMSm<"pcvm", 0xa4, VM>; 1508 1509// Section 8.17.11 - LZVM (Leading Zero of VM) 1510defm LZVM : RVMSm<"lzvm", 0xa5, VM>; 1511 1512// Section 8.17.12 - TOVM (Trailing One of VM) 1513defm TOVM : RVMSm<"tovm", 0xa6, VM>; 1514 1515//----------------------------------------------------------------------------- 1516// Section 8.18 - Vector Control Instructions 1517//----------------------------------------------------------------------------- 1518 1519// Section 8.18.1 - LVL (Load VL) 1520let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VL] in { 1521 def LVLr : RR<0xbf, (outs), (ins I64:$sy), "lvl $sy">; 1522 let cy = 0 in def LVLi : RR<0xbf, (outs), (ins simm7:$sy), "lvl $sy">; 1523} 1524 1525// Section 8.18.2 - SVL (Save VL) 1526let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0, Uses = [VL] in 1527def SVL : RR<0x2f, (outs I64:$sx), (ins), "svl $sx">; 1528 1529// Section 8.18.3 - SMVL (Save Maximum Vector Length) 1530let cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 0 in 1531def SMVL : RR<0x2e, (outs I64:$sx), (ins), "smvl $sx">; 1532 1533// Section 8.18.4 - LVIX (Load Vector Data Index) 1534let sx = 0, cz = 0, sz = 0, hasSideEffects = 0, Defs = [VIX] in { 1535 def LVIXr : RR<0xaf, (outs), (ins I64:$sy), "lvix $sy">; 1536 let cy = 0 in def LVIXi : RR<0xaf, (outs), (ins uimm6:$sy), "lvix $sy">; 1537} 1538