1/// Pattern Matchings for VEL intrinsic instructions. 2 3/// Intrinsic patterns written by hand. 4 5// SVOB pattern. 6def : Pat<(int_ve_vl_svob), (SVOB)>; 7 8// Pack patterns. 9def : Pat<(i64 (int_ve_vl_pack_f32p ADDRrii:$addr0, ADDRrii:$addr1)), 10 (ORrr (f2l (LDUrii MEMrii:$addr0)), 11 (i2l (LDLZXrii MEMrii:$addr1)))>; 12 13def : Pat<(i64 (int_ve_vl_pack_f32a ADDRrii:$addr)), 14 (MULULrr 15 (i2l (LDLZXrii MEMrii:$addr)), 16 (LEASLrii (ANDrm (LEAzii 0, 0, (LO32 (i64 0x0000000100000001))), 17 !add(32, 64)), 0, 18 (HI32 (i64 0x0000000100000001))))>; 19 20// The extract/insert patterns. 21def : Pat<(v256i1 (int_ve_vl_extract_vm512u v512i1:$vm)), 22 (EXTRACT_SUBREG v512i1:$vm, sub_vm_even)>; 23 24def : Pat<(v256i1 (int_ve_vl_extract_vm512l v512i1:$vm)), 25 (EXTRACT_SUBREG v512i1:$vm, sub_vm_odd)>; 26 27def : Pat<(v512i1 (int_ve_vl_insert_vm512u v512i1:$vmx, v256i1:$vmy)), 28 (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_even)>; 29 30def : Pat<(v512i1 (int_ve_vl_insert_vm512l v512i1:$vmx, v256i1:$vmy)), 31 (INSERT_SUBREG v512i1:$vmx, v256i1:$vmy, sub_vm_odd)>; 32 33// VMRG patterns. 34def : Pat<(int_ve_vl_vmrgw_vsvMl i32:$sy, v256f64:$vz, v512i1:$vm, i32:$vl), 35 (VMRGWrvml (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl)>; 36def : Pat<(int_ve_vl_vmrgw_vsvMvl i32:$sy, v256f64:$vz, v512i1:$vm, 37 v256f64:$pt, i32:$vl), 38 (VMRGWrvml_v (i2l i32:$sy), v256f64:$vz, v512i1:$vm, i32:$vl, 39 v256f64:$pt)>; 40 41// VMV patterns. 42def : Pat<(int_ve_vl_vmv_vsvl i32:$sy, v256f64:$vz, i32:$vl), 43 (VMVrvl (i2l i32:$sy), v256f64:$vz, i32:$vl)>; 44def : Pat<(int_ve_vl_vmv_vsvvl i32:$sy, v256f64:$vz, v256f64:$pt, i32:$vl), 45 (VMVrvl_v (i2l i32:$sy), v256f64:$vz, i32:$vl, v256f64:$pt)>; 46def : Pat<(int_ve_vl_vmv_vsvmvl i32:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt, 47 i32:$vl), 48 (VMVrvml_v (i2l i32:$sy), v256f64:$vz, v256i1:$vm, i32:$vl, 49 v256f64:$pt)>; 50 51// LSV patterns. 52def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz), 53 (LSVrr_v (i2l i32:$sy), i64:$sz, v256f64:$pt)>; 54 55// LVS patterns. 56def : Pat<(int_ve_vl_lvsl_svs v256f64:$vx, i32:$sy), 57 (LVSvr v256f64:$vx, (i2l i32:$sy))>; 58def : Pat<(int_ve_vl_lvsd_svs v256f64:$vx, i32:$sy), 59 (LVSvr v256f64:$vx, (i2l i32:$sy))>; 60def : Pat<(int_ve_vl_lvss_svs v256f64:$vx, i32:$sy), 61 (l2f (LVSvr v256f64:$vx, (i2l i32:$sy)))>; 62 63/// Intrinsic patterns automatically generated. 64include "VEInstrIntrinsicVL.gen.td" 65