1 //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H 14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H 15 16 #include "VERegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "VEGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class VESubtarget; 25 26 class VEInstrInfo : public VEGenInstrInfo { 27 const VERegisterInfo RI; 28 virtual void anchor(); 29 30 public: 31 explicit VEInstrInfo(VESubtarget &ST); 32 33 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 34 /// such, whenever a client has an instance of instruction info, it should 35 /// always be able to get register info as well (through this method). 36 /// 37 const VERegisterInfo &getRegisterInfo() const { return RI; } 38 39 /// Branch Analysis & Modification { 40 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 41 MachineBasicBlock *&FBB, 42 SmallVectorImpl<MachineOperand> &Cond, 43 bool AllowModify = false) const override; 44 45 unsigned removeBranch(MachineBasicBlock &MBB, 46 int *BytesRemoved = nullptr) const override; 47 48 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 49 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 50 const DebugLoc &DL, 51 int *BytesAdded = nullptr) const override; 52 53 bool 54 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 55 /// } Branch Analysis & Modification 56 57 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 58 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 59 bool KillSrc) const override; 60 61 /// Stack Spill & Reload { 62 unsigned isLoadFromStackSlot(const MachineInstr &MI, 63 int &FrameIndex) const override; 64 unsigned isStoreToStackSlot(const MachineInstr &MI, 65 int &FrameIndex) const override; 66 void storeRegToStackSlot(MachineBasicBlock &MBB, 67 MachineBasicBlock::iterator MBBI, Register SrcReg, 68 bool isKill, int FrameIndex, 69 const TargetRegisterClass *RC, 70 const TargetRegisterInfo *TRI) const override; 71 72 void loadRegFromStackSlot(MachineBasicBlock &MBB, 73 MachineBasicBlock::iterator MBBI, Register DestReg, 74 int FrameIndex, const TargetRegisterClass *RC, 75 const TargetRegisterInfo *TRI) const override; 76 /// } Stack Spill & Reload 77 78 Register getGlobalBaseReg(MachineFunction *MF) const; 79 80 // Lower pseudo instructions after register allocation. 81 bool expandPostRAPseudo(MachineInstr &MI) const override; 82 83 bool expandExtendStackPseudo(MachineInstr &MI) const; 84 bool expandGetStackTopPseudo(MachineInstr &MI) const; 85 }; 86 87 } // namespace llvm 88 89 #endif 90