1480093f4SDimitry Andric //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===// 2480093f4SDimitry Andric // 3480093f4SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4480093f4SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5480093f4SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6480093f4SDimitry Andric // 7480093f4SDimitry Andric //===----------------------------------------------------------------------===// 8480093f4SDimitry Andric // 9480093f4SDimitry Andric // This file contains the VE implementation of the TargetInstrInfo class. 10480093f4SDimitry Andric // 11480093f4SDimitry Andric //===----------------------------------------------------------------------===// 12480093f4SDimitry Andric 13480093f4SDimitry Andric #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H 14480093f4SDimitry Andric #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H 15480093f4SDimitry Andric 16480093f4SDimitry Andric #include "VERegisterInfo.h" 17480093f4SDimitry Andric #include "llvm/CodeGen/TargetInstrInfo.h" 18480093f4SDimitry Andric 19480093f4SDimitry Andric #define GET_INSTRINFO_HEADER 20480093f4SDimitry Andric #include "VEGenInstrInfo.inc" 21480093f4SDimitry Andric 22480093f4SDimitry Andric namespace llvm { 23480093f4SDimitry Andric 24480093f4SDimitry Andric class VESubtarget; 25480093f4SDimitry Andric 26480093f4SDimitry Andric class VEInstrInfo : public VEGenInstrInfo { 27480093f4SDimitry Andric const VERegisterInfo RI; 28480093f4SDimitry Andric virtual void anchor(); 29480093f4SDimitry Andric 30480093f4SDimitry Andric public: 31480093f4SDimitry Andric explicit VEInstrInfo(VESubtarget &ST); 32480093f4SDimitry Andric 33480093f4SDimitry Andric /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 34480093f4SDimitry Andric /// such, whenever a client has an instance of instruction info, it should 35480093f4SDimitry Andric /// always be able to get register info as well (through this method). 36480093f4SDimitry Andric /// 37480093f4SDimitry Andric const VERegisterInfo &getRegisterInfo() const { return RI; } 38480093f4SDimitry Andric 39*5ffd83dbSDimitry Andric /// Branch Analysis & Modification { 40*5ffd83dbSDimitry Andric bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 41*5ffd83dbSDimitry Andric MachineBasicBlock *&FBB, 42*5ffd83dbSDimitry Andric SmallVectorImpl<MachineOperand> &Cond, 43*5ffd83dbSDimitry Andric bool AllowModify = false) const override; 44*5ffd83dbSDimitry Andric 45*5ffd83dbSDimitry Andric unsigned removeBranch(MachineBasicBlock &MBB, 46*5ffd83dbSDimitry Andric int *BytesRemoved = nullptr) const override; 47*5ffd83dbSDimitry Andric 48*5ffd83dbSDimitry Andric unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 49*5ffd83dbSDimitry Andric MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 50*5ffd83dbSDimitry Andric const DebugLoc &DL, 51*5ffd83dbSDimitry Andric int *BytesAdded = nullptr) const override; 52*5ffd83dbSDimitry Andric 53*5ffd83dbSDimitry Andric bool 54*5ffd83dbSDimitry Andric reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 55*5ffd83dbSDimitry Andric /// } Branch Analysis & Modification 56*5ffd83dbSDimitry Andric 57*5ffd83dbSDimitry Andric void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 58*5ffd83dbSDimitry Andric const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 59*5ffd83dbSDimitry Andric bool KillSrc) const override; 60*5ffd83dbSDimitry Andric 61*5ffd83dbSDimitry Andric /// Stack Spill & Reload { 62*5ffd83dbSDimitry Andric unsigned isLoadFromStackSlot(const MachineInstr &MI, 63*5ffd83dbSDimitry Andric int &FrameIndex) const override; 64*5ffd83dbSDimitry Andric unsigned isStoreToStackSlot(const MachineInstr &MI, 65*5ffd83dbSDimitry Andric int &FrameIndex) const override; 66*5ffd83dbSDimitry Andric void storeRegToStackSlot(MachineBasicBlock &MBB, 67*5ffd83dbSDimitry Andric MachineBasicBlock::iterator MBBI, Register SrcReg, 68*5ffd83dbSDimitry Andric bool isKill, int FrameIndex, 69*5ffd83dbSDimitry Andric const TargetRegisterClass *RC, 70*5ffd83dbSDimitry Andric const TargetRegisterInfo *TRI) const override; 71*5ffd83dbSDimitry Andric 72*5ffd83dbSDimitry Andric void loadRegFromStackSlot(MachineBasicBlock &MBB, 73*5ffd83dbSDimitry Andric MachineBasicBlock::iterator MBBI, Register DestReg, 74*5ffd83dbSDimitry Andric int FrameIndex, const TargetRegisterClass *RC, 75*5ffd83dbSDimitry Andric const TargetRegisterInfo *TRI) const override; 76*5ffd83dbSDimitry Andric /// } Stack Spill & Reload 77*5ffd83dbSDimitry Andric 78*5ffd83dbSDimitry Andric Register getGlobalBaseReg(MachineFunction *MF) const; 79*5ffd83dbSDimitry Andric 80480093f4SDimitry Andric // Lower pseudo instructions after register allocation. 81480093f4SDimitry Andric bool expandPostRAPseudo(MachineInstr &MI) const override; 82480093f4SDimitry Andric 83480093f4SDimitry Andric bool expandExtendStackPseudo(MachineInstr &MI) const; 84*5ffd83dbSDimitry Andric bool expandGetStackTopPseudo(MachineInstr &MI) const; 85480093f4SDimitry Andric }; 86480093f4SDimitry Andric 87480093f4SDimitry Andric } // namespace llvm 88480093f4SDimitry Andric 89480093f4SDimitry Andric #endif 90