1 //===-- VEInstrInfo.cpp - VE Instruction Information ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "VEInstrInfo.h" 14 #include "VE.h" 15 #include "VEMachineFunctionInfo.h" 16 #include "VESubtarget.h" 17 #include "llvm/ADT/STLExtras.h" 18 #include "llvm/ADT/SmallVector.h" 19 #include "llvm/CodeGen/MachineFrameInfo.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineMemOperand.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/MC/TargetRegistry.h" 24 #include "llvm/Support/CommandLine.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/ErrorHandling.h" 27 28 #define DEBUG_TYPE "ve-instr-info" 29 30 using namespace llvm; 31 32 #define GET_INSTRINFO_CTOR_DTOR 33 #include "VEGenInstrInfo.inc" 34 35 // Pin the vtable to this file. 36 void VEInstrInfo::anchor() {} 37 38 VEInstrInfo::VEInstrInfo(VESubtarget &ST) 39 : VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI() {} 40 41 static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); } 42 43 static VECC::CondCode GetOppositeBranchCondition(VECC::CondCode CC) { 44 switch (CC) { 45 case VECC::CC_IG: 46 return VECC::CC_ILE; 47 case VECC::CC_IL: 48 return VECC::CC_IGE; 49 case VECC::CC_INE: 50 return VECC::CC_IEQ; 51 case VECC::CC_IEQ: 52 return VECC::CC_INE; 53 case VECC::CC_IGE: 54 return VECC::CC_IL; 55 case VECC::CC_ILE: 56 return VECC::CC_IG; 57 case VECC::CC_AF: 58 return VECC::CC_AT; 59 case VECC::CC_G: 60 return VECC::CC_LENAN; 61 case VECC::CC_L: 62 return VECC::CC_GENAN; 63 case VECC::CC_NE: 64 return VECC::CC_EQNAN; 65 case VECC::CC_EQ: 66 return VECC::CC_NENAN; 67 case VECC::CC_GE: 68 return VECC::CC_LNAN; 69 case VECC::CC_LE: 70 return VECC::CC_GNAN; 71 case VECC::CC_NUM: 72 return VECC::CC_NAN; 73 case VECC::CC_NAN: 74 return VECC::CC_NUM; 75 case VECC::CC_GNAN: 76 return VECC::CC_LE; 77 case VECC::CC_LNAN: 78 return VECC::CC_GE; 79 case VECC::CC_NENAN: 80 return VECC::CC_EQ; 81 case VECC::CC_EQNAN: 82 return VECC::CC_NE; 83 case VECC::CC_GENAN: 84 return VECC::CC_L; 85 case VECC::CC_LENAN: 86 return VECC::CC_G; 87 case VECC::CC_AT: 88 return VECC::CC_AF; 89 case VECC::UNKNOWN: 90 return VECC::UNKNOWN; 91 } 92 llvm_unreachable("Invalid cond code"); 93 } 94 95 // Treat a branch relative long always instruction as unconditional branch. 96 // For example, br.l.t and br.l. 97 static bool isUncondBranchOpcode(int Opc) { 98 using namespace llvm::VE; 99 100 #define BRKIND(NAME) (Opc == NAME##a || Opc == NAME##a_nt || Opc == NAME##a_t) 101 // VE has other branch relative always instructions for word/double/float, 102 // but we use only long branches in our lower. So, check it here. 103 assert(!BRKIND(BRCFW) && !BRKIND(BRCFD) && !BRKIND(BRCFS) && 104 "Branch relative word/double/float always instructions should not be " 105 "used!"); 106 return BRKIND(BRCFL); 107 #undef BRKIND 108 } 109 110 // Treat branch relative conditional as conditional branch instructions. 111 // For example, brgt.l.t and brle.s.nt. 112 static bool isCondBranchOpcode(int Opc) { 113 using namespace llvm::VE; 114 115 #define BRKIND(NAME) \ 116 (Opc == NAME##rr || Opc == NAME##rr_nt || Opc == NAME##rr_t || \ 117 Opc == NAME##ir || Opc == NAME##ir_nt || Opc == NAME##ir_t) 118 return BRKIND(BRCFL) || BRKIND(BRCFW) || BRKIND(BRCFD) || BRKIND(BRCFS); 119 #undef BRKIND 120 } 121 122 // Treat branch long always instructions as indirect branch. 123 // For example, b.l.t and b.l. 124 static bool isIndirectBranchOpcode(int Opc) { 125 using namespace llvm::VE; 126 127 #define BRKIND(NAME) \ 128 (Opc == NAME##ari || Opc == NAME##ari_nt || Opc == NAME##ari_t) 129 // VE has other branch always instructions for word/double/float, but 130 // we use only long branches in our lower. So, check it here. 131 assert(!BRKIND(BCFW) && !BRKIND(BCFD) && !BRKIND(BCFS) && 132 "Branch word/double/float always instructions should not be used!"); 133 return BRKIND(BCFL); 134 #undef BRKIND 135 } 136 137 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, 138 SmallVectorImpl<MachineOperand> &Cond) { 139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); 140 Cond.push_back(LastInst->getOperand(1)); 141 Cond.push_back(LastInst->getOperand(2)); 142 Target = LastInst->getOperand(3).getMBB(); 143 } 144 145 bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 146 MachineBasicBlock *&FBB, 147 SmallVectorImpl<MachineOperand> &Cond, 148 bool AllowModify) const { 149 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); 150 if (I == MBB.end()) 151 return false; 152 153 if (!isUnpredicatedTerminator(*I)) 154 return false; 155 156 // Get the last instruction in the block. 157 MachineInstr *LastInst = &*I; 158 unsigned LastOpc = LastInst->getOpcode(); 159 160 // If there is only one terminator instruction, process it. 161 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 162 if (isUncondBranchOpcode(LastOpc)) { 163 TBB = LastInst->getOperand(0).getMBB(); 164 return false; 165 } 166 if (isCondBranchOpcode(LastOpc)) { 167 // Block ends with fall-through condbranch. 168 parseCondBranch(LastInst, TBB, Cond); 169 return false; 170 } 171 return true; // Can't handle indirect branch. 172 } 173 174 // Get the instruction before it if it is a terminator. 175 MachineInstr *SecondLastInst = &*I; 176 unsigned SecondLastOpc = SecondLastInst->getOpcode(); 177 178 // If AllowModify is true and the block ends with two or more unconditional 179 // branches, delete all but the first unconditional branch. 180 if (AllowModify && isUncondBranchOpcode(LastOpc)) { 181 while (isUncondBranchOpcode(SecondLastOpc)) { 182 LastInst->eraseFromParent(); 183 LastInst = SecondLastInst; 184 LastOpc = LastInst->getOpcode(); 185 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) { 186 // Return now the only terminator is an unconditional branch. 187 TBB = LastInst->getOperand(0).getMBB(); 188 return false; 189 } 190 SecondLastInst = &*I; 191 SecondLastOpc = SecondLastInst->getOpcode(); 192 } 193 } 194 195 // If there are three terminators, we don't know what sort of block this is. 196 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I)) 197 return true; 198 199 // If the block ends with a B and a Bcc, handle it. 200 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 201 parseCondBranch(SecondLastInst, TBB, Cond); 202 FBB = LastInst->getOperand(0).getMBB(); 203 return false; 204 } 205 206 // If the block ends with two unconditional branches, handle it. The second 207 // one is not executed. 208 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 209 TBB = SecondLastInst->getOperand(0).getMBB(); 210 return false; 211 } 212 213 // ...likewise if it ends with an indirect branch followed by an unconditional 214 // branch. 215 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) { 216 I = LastInst; 217 if (AllowModify) 218 I->eraseFromParent(); 219 return true; 220 } 221 222 // Otherwise, can't handle this. 223 return true; 224 } 225 226 unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB, 227 MachineBasicBlock *TBB, 228 MachineBasicBlock *FBB, 229 ArrayRef<MachineOperand> Cond, 230 const DebugLoc &DL, int *BytesAdded) const { 231 assert(TBB && "insertBranch must not be told to insert a fallthrough"); 232 assert((Cond.size() == 3 || Cond.size() == 0) && 233 "VE branch conditions should have three component!"); 234 assert(!BytesAdded && "code size not handled"); 235 if (Cond.empty()) { 236 // Uncondition branch 237 assert(!FBB && "Unconditional branch with multiple successors!"); 238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 239 .addMBB(TBB); 240 return 1; 241 } 242 243 // Conditional branch 244 // (BRCFir CC sy sz addr) 245 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); 246 247 unsigned opc[2]; 248 const TargetRegisterInfo *TRI = &getRegisterInfo(); 249 MachineFunction *MF = MBB.getParent(); 250 const MachineRegisterInfo &MRI = MF->getRegInfo(); 251 Register Reg = Cond[2].getReg(); 252 if (IsIntegerCC(Cond[0].getImm())) { 253 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 254 opc[0] = VE::BRCFWir; 255 opc[1] = VE::BRCFWrr; 256 } else { 257 opc[0] = VE::BRCFLir; 258 opc[1] = VE::BRCFLrr; 259 } 260 } else { 261 if (TRI->getRegSizeInBits(Reg, MRI) == 32) { 262 opc[0] = VE::BRCFSir; 263 opc[1] = VE::BRCFSrr; 264 } else { 265 opc[0] = VE::BRCFDir; 266 opc[1] = VE::BRCFDrr; 267 } 268 } 269 if (Cond[1].isImm()) { 270 BuildMI(&MBB, DL, get(opc[0])) 271 .add(Cond[0]) // condition code 272 .add(Cond[1]) // lhs 273 .add(Cond[2]) // rhs 274 .addMBB(TBB); 275 } else { 276 BuildMI(&MBB, DL, get(opc[1])) 277 .add(Cond[0]) 278 .add(Cond[1]) 279 .add(Cond[2]) 280 .addMBB(TBB); 281 } 282 283 if (!FBB) 284 return 1; 285 286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) 287 .addMBB(FBB); 288 return 2; 289 } 290 291 unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB, 292 int *BytesRemoved) const { 293 assert(!BytesRemoved && "code size not handled"); 294 295 MachineBasicBlock::iterator I = MBB.end(); 296 unsigned Count = 0; 297 while (I != MBB.begin()) { 298 --I; 299 300 if (I->isDebugValue()) 301 continue; 302 303 if (!isUncondBranchOpcode(I->getOpcode()) && 304 !isCondBranchOpcode(I->getOpcode())) 305 break; // Not a branch 306 307 I->eraseFromParent(); 308 I = MBB.end(); 309 ++Count; 310 } 311 return Count; 312 } 313 314 bool VEInstrInfo::reverseBranchCondition( 315 SmallVectorImpl<MachineOperand> &Cond) const { 316 VECC::CondCode CC = static_cast<VECC::CondCode>(Cond[0].getImm()); 317 Cond[0].setImm(GetOppositeBranchCondition(CC)); 318 return false; 319 } 320 321 static bool IsAliasOfSX(Register Reg) { 322 return VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) || 323 VE::F32RegClass.contains(Reg); 324 } 325 326 static void copyPhysSubRegs(MachineBasicBlock &MBB, 327 MachineBasicBlock::iterator I, const DebugLoc &DL, 328 MCRegister DestReg, MCRegister SrcReg, bool KillSrc, 329 const MCInstrDesc &MCID, unsigned int NumSubRegs, 330 const unsigned *SubRegIdx, 331 const TargetRegisterInfo *TRI) { 332 MachineInstr *MovMI = nullptr; 333 334 for (unsigned Idx = 0; Idx != NumSubRegs; ++Idx) { 335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); 336 Register SubSrc = TRI->getSubReg(SrcReg, SubRegIdx[Idx]); 337 assert(SubDest && SubSrc && "Bad sub-register"); 338 339 if (MCID.getOpcode() == VE::ORri) { 340 // generate "ORri, dest, src, 0" instruction. 341 MachineInstrBuilder MIB = 342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); 343 MovMI = MIB.getInstr(); 344 } else if (MCID.getOpcode() == VE::ANDMmm) { 345 // generate "ANDM, dest, vm0, src" instruction. 346 MachineInstrBuilder MIB = 347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); 348 MovMI = MIB.getInstr(); 349 } else { 350 llvm_unreachable("Unexpected reg-to-reg copy instruction"); 351 } 352 } 353 // Add implicit super-register defs and kills to the last MovMI. 354 MovMI->addRegisterDefined(DestReg, TRI); 355 if (KillSrc) 356 MovMI->addRegisterKilled(SrcReg, TRI, true); 357 } 358 359 void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 360 MachineBasicBlock::iterator I, const DebugLoc &DL, 361 MCRegister DestReg, MCRegister SrcReg, 362 bool KillSrc) const { 363 364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { 365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) 366 .addReg(SrcReg, getKillRegState(KillSrc)) 367 .addImm(0); 368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { 369 // Generate following instructions 370 // %sw16 = LEA32zii 256 371 // VORmvl %dest, (0)1, %src, %sw16 372 // TODO: reuse a register if vl is already assigned to a register 373 // FIXME: it would be better to scavenge a register here instead of 374 // reserving SX16 all of the time. 375 const TargetRegisterInfo *TRI = &getRegisterInfo(); 376 Register TmpReg = VE::SX16; 377 Register SubTmp = TRI->getSubReg(TmpReg, VE::sub_i32); 378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) 379 .addImm(0) 380 .addImm(0) 381 .addImm(256); 382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) 383 .addImm(M1(0)) // Represent (0)1. 384 .addReg(SrcReg, getKillRegState(KillSrc)) 385 .addReg(SubTmp, getKillRegState(true)); 386 MIB.getInstr()->addRegisterKilled(TmpReg, TRI, true); 387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { 388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) 389 .addReg(VE::VM0) 390 .addReg(SrcReg, getKillRegState(KillSrc)); 391 } else if (VE::VM512RegClass.contains(DestReg, SrcReg)) { 392 // Use two instructions. 393 const unsigned SubRegIdx[] = {VE::sub_vm_even, VE::sub_vm_odd}; 394 unsigned int NumSubRegs = 2; 395 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ANDMmm), 396 NumSubRegs, SubRegIdx, &getRegisterInfo()); 397 } else if (VE::F128RegClass.contains(DestReg, SrcReg)) { 398 // Use two instructions. 399 const unsigned SubRegIdx[] = {VE::sub_even, VE::sub_odd}; 400 unsigned int NumSubRegs = 2; 401 copyPhysSubRegs(MBB, I, DL, DestReg, SrcReg, KillSrc, get(VE::ORri), 402 NumSubRegs, SubRegIdx, &getRegisterInfo()); 403 } else { 404 const TargetRegisterInfo *TRI = &getRegisterInfo(); 405 dbgs() << "Impossible reg-to-reg copy from " << printReg(SrcReg, TRI) 406 << " to " << printReg(DestReg, TRI) << "\n"; 407 llvm_unreachable("Impossible reg-to-reg copy"); 408 } 409 } 410 411 /// isLoadFromStackSlot - If the specified machine instruction is a direct 412 /// load from a stack slot, return the virtual or physical register number of 413 /// the destination along with the FrameIndex of the loaded stack slot. If 414 /// not, return 0. This predicate must return 0 if the instruction has 415 /// any side effects other than loading from the stack slot. 416 unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 417 int &FrameIndex) const { 418 if (MI.getOpcode() == VE::LDrii || // I64 419 MI.getOpcode() == VE::LDLSXrii || // I32 420 MI.getOpcode() == VE::LDUrii || // F32 421 MI.getOpcode() == VE::LDQrii || // F128 (pseudo) 422 MI.getOpcode() == VE::LDVMrii || // VM (pseudo) 423 MI.getOpcode() == VE::LDVM512rii // VM512 (pseudo) 424 ) { 425 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && 426 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).isImm() && 427 MI.getOperand(3).getImm() == 0) { 428 FrameIndex = MI.getOperand(1).getIndex(); 429 return MI.getOperand(0).getReg(); 430 } 431 } 432 return 0; 433 } 434 435 /// isStoreToStackSlot - If the specified machine instruction is a direct 436 /// store to a stack slot, return the virtual or physical register number of 437 /// the source reg along with the FrameIndex of the loaded stack slot. If 438 /// not, return 0. This predicate must return 0 if the instruction has 439 /// any side effects other than storing to the stack slot. 440 unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 441 int &FrameIndex) const { 442 if (MI.getOpcode() == VE::STrii || // I64 443 MI.getOpcode() == VE::STLrii || // I32 444 MI.getOpcode() == VE::STUrii || // F32 445 MI.getOpcode() == VE::STQrii || // F128 (pseudo) 446 MI.getOpcode() == VE::STVMrii || // VM (pseudo) 447 MI.getOpcode() == VE::STVM512rii // VM512 (pseudo) 448 ) { 449 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && 450 MI.getOperand(1).getImm() == 0 && MI.getOperand(2).isImm() && 451 MI.getOperand(2).getImm() == 0) { 452 FrameIndex = MI.getOperand(0).getIndex(); 453 return MI.getOperand(3).getReg(); 454 } 455 } 456 return 0; 457 } 458 459 void VEInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 460 MachineBasicBlock::iterator I, 461 Register SrcReg, bool isKill, int FI, 462 const TargetRegisterClass *RC, 463 const TargetRegisterInfo *TRI) const { 464 DebugLoc DL; 465 if (I != MBB.end()) 466 DL = I->getDebugLoc(); 467 468 MachineFunction *MF = MBB.getParent(); 469 const MachineFrameInfo &MFI = MF->getFrameInfo(); 470 MachineMemOperand *MMO = MF->getMachineMemOperand( 471 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, 472 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 473 474 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 475 if (RC == &VE::I64RegClass) { 476 BuildMI(MBB, I, DL, get(VE::STrii)) 477 .addFrameIndex(FI) 478 .addImm(0) 479 .addImm(0) 480 .addReg(SrcReg, getKillRegState(isKill)) 481 .addMemOperand(MMO); 482 } else if (RC == &VE::I32RegClass) { 483 BuildMI(MBB, I, DL, get(VE::STLrii)) 484 .addFrameIndex(FI) 485 .addImm(0) 486 .addImm(0) 487 .addReg(SrcReg, getKillRegState(isKill)) 488 .addMemOperand(MMO); 489 } else if (RC == &VE::F32RegClass) { 490 BuildMI(MBB, I, DL, get(VE::STUrii)) 491 .addFrameIndex(FI) 492 .addImm(0) 493 .addImm(0) 494 .addReg(SrcReg, getKillRegState(isKill)) 495 .addMemOperand(MMO); 496 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 497 BuildMI(MBB, I, DL, get(VE::STQrii)) 498 .addFrameIndex(FI) 499 .addImm(0) 500 .addImm(0) 501 .addReg(SrcReg, getKillRegState(isKill)) 502 .addMemOperand(MMO); 503 } else if (RC == &VE::VMRegClass) { 504 BuildMI(MBB, I, DL, get(VE::STVMrii)) 505 .addFrameIndex(FI) 506 .addImm(0) 507 .addImm(0) 508 .addReg(SrcReg, getKillRegState(isKill)) 509 .addMemOperand(MMO); 510 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { 511 BuildMI(MBB, I, DL, get(VE::STVM512rii)) 512 .addFrameIndex(FI) 513 .addImm(0) 514 .addImm(0) 515 .addReg(SrcReg, getKillRegState(isKill)) 516 .addMemOperand(MMO); 517 } else 518 report_fatal_error("Can't store this register to stack slot"); 519 } 520 521 void VEInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 522 MachineBasicBlock::iterator I, 523 Register DestReg, int FI, 524 const TargetRegisterClass *RC, 525 const TargetRegisterInfo *TRI) const { 526 DebugLoc DL; 527 if (I != MBB.end()) 528 DL = I->getDebugLoc(); 529 530 MachineFunction *MF = MBB.getParent(); 531 const MachineFrameInfo &MFI = MF->getFrameInfo(); 532 MachineMemOperand *MMO = MF->getMachineMemOperand( 533 MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, 534 MFI.getObjectSize(FI), MFI.getObjectAlign(FI)); 535 536 if (RC == &VE::I64RegClass) { 537 BuildMI(MBB, I, DL, get(VE::LDrii), DestReg) 538 .addFrameIndex(FI) 539 .addImm(0) 540 .addImm(0) 541 .addMemOperand(MMO); 542 } else if (RC == &VE::I32RegClass) { 543 BuildMI(MBB, I, DL, get(VE::LDLSXrii), DestReg) 544 .addFrameIndex(FI) 545 .addImm(0) 546 .addImm(0) 547 .addMemOperand(MMO); 548 } else if (RC == &VE::F32RegClass) { 549 BuildMI(MBB, I, DL, get(VE::LDUrii), DestReg) 550 .addFrameIndex(FI) 551 .addImm(0) 552 .addImm(0) 553 .addMemOperand(MMO); 554 } else if (VE::F128RegClass.hasSubClassEq(RC)) { 555 BuildMI(MBB, I, DL, get(VE::LDQrii), DestReg) 556 .addFrameIndex(FI) 557 .addImm(0) 558 .addImm(0) 559 .addMemOperand(MMO); 560 } else if (RC == &VE::VMRegClass) { 561 BuildMI(MBB, I, DL, get(VE::LDVMrii), DestReg) 562 .addFrameIndex(FI) 563 .addImm(0) 564 .addImm(0) 565 .addMemOperand(MMO); 566 } else if (VE::VM512RegClass.hasSubClassEq(RC)) { 567 BuildMI(MBB, I, DL, get(VE::LDVM512rii), DestReg) 568 .addFrameIndex(FI) 569 .addImm(0) 570 .addImm(0) 571 .addMemOperand(MMO); 572 } else 573 report_fatal_error("Can't load this register from stack slot"); 574 } 575 576 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 577 Register Reg, MachineRegisterInfo *MRI) const { 578 LLVM_DEBUG(dbgs() << "FoldImmediate\n"); 579 580 LLVM_DEBUG(dbgs() << "checking DefMI\n"); 581 int64_t ImmVal; 582 switch (DefMI.getOpcode()) { 583 default: 584 return false; 585 case VE::ORim: 586 // General move small immediate instruction on VE. 587 LLVM_DEBUG(dbgs() << "checking ORim\n"); 588 LLVM_DEBUG(DefMI.dump()); 589 // FIXME: We may need to support FPImm too. 590 assert(DefMI.getOperand(1).isImm()); 591 assert(DefMI.getOperand(2).isImm()); 592 ImmVal = 593 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); 594 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 595 break; 596 case VE::LEAzii: 597 // General move immediate instruction on VE. 598 LLVM_DEBUG(dbgs() << "checking LEAzii\n"); 599 LLVM_DEBUG(DefMI.dump()); 600 // FIXME: We may need to support FPImm too. 601 assert(DefMI.getOperand(2).isImm()); 602 if (!DefMI.getOperand(3).isImm()) 603 // LEAzii may refer label 604 return false; 605 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); 606 LLVM_DEBUG(dbgs() << "ImmVal is " << ImmVal << "\n"); 607 break; 608 } 609 610 // Try to fold like below: 611 // %1:i64 = ORim 0, 0(1) 612 // %2:i64 = CMPSLrr %0, %1 613 // To 614 // %2:i64 = CMPSLrm %0, 0(1) 615 // 616 // Another example: 617 // %1:i64 = ORim 6, 0(1) 618 // %2:i64 = CMPSLrr %1, %0 619 // To 620 // %2:i64 = CMPSLir 6, %0 621 // 622 // Support commutable instructions like below: 623 // %1:i64 = ORim 6, 0(1) 624 // %2:i64 = ADDSLrr %1, %0 625 // To 626 // %2:i64 = ADDSLri %0, 6 627 // 628 // FIXME: Need to support i32. Current implementtation requires 629 // EXTRACT_SUBREG, so input has following COPY and it avoids folding: 630 // %1:i64 = ORim 6, 0(1) 631 // %2:i32 = COPY %1.sub_i32 632 // %3:i32 = ADDSWSXrr %0, %2 633 // FIXME: Need to support shift, cmov, and more instructions. 634 // FIXME: Need to support lvl too, but LVLGen runs after peephole-opt. 635 636 LLVM_DEBUG(dbgs() << "checking UseMI\n"); 637 LLVM_DEBUG(UseMI.dump()); 638 unsigned NewUseOpcSImm7; 639 unsigned NewUseOpcMImm; 640 enum InstType { 641 rr2ri_rm, // rr -> ri or rm, commutable 642 rr2ir_rm, // rr -> ir or rm 643 } InstType; 644 645 using namespace llvm::VE; 646 #define INSTRKIND(NAME) \ 647 case NAME##rr: \ 648 NewUseOpcSImm7 = NAME##ri; \ 649 NewUseOpcMImm = NAME##rm; \ 650 InstType = rr2ri_rm; \ 651 break 652 #define NCINSTRKIND(NAME) \ 653 case NAME##rr: \ 654 NewUseOpcSImm7 = NAME##ir; \ 655 NewUseOpcMImm = NAME##rm; \ 656 InstType = rr2ir_rm; \ 657 break 658 659 switch (UseMI.getOpcode()) { 660 default: 661 return false; 662 663 INSTRKIND(ADDUL); 664 INSTRKIND(ADDSWSX); 665 INSTRKIND(ADDSWZX); 666 INSTRKIND(ADDSL); 667 NCINSTRKIND(SUBUL); 668 NCINSTRKIND(SUBSWSX); 669 NCINSTRKIND(SUBSWZX); 670 NCINSTRKIND(SUBSL); 671 INSTRKIND(MULUL); 672 INSTRKIND(MULSWSX); 673 INSTRKIND(MULSWZX); 674 INSTRKIND(MULSL); 675 NCINSTRKIND(DIVUL); 676 NCINSTRKIND(DIVSWSX); 677 NCINSTRKIND(DIVSWZX); 678 NCINSTRKIND(DIVSL); 679 NCINSTRKIND(CMPUL); 680 NCINSTRKIND(CMPSWSX); 681 NCINSTRKIND(CMPSWZX); 682 NCINSTRKIND(CMPSL); 683 INSTRKIND(MAXSWSX); 684 INSTRKIND(MAXSWZX); 685 INSTRKIND(MAXSL); 686 INSTRKIND(MINSWSX); 687 INSTRKIND(MINSWZX); 688 INSTRKIND(MINSL); 689 INSTRKIND(AND); 690 INSTRKIND(OR); 691 INSTRKIND(XOR); 692 INSTRKIND(EQV); 693 NCINSTRKIND(NND); 694 NCINSTRKIND(MRG); 695 } 696 697 #undef INSTRKIND 698 699 unsigned NewUseOpc; 700 unsigned UseIdx; 701 bool Commute = false; 702 LLVM_DEBUG(dbgs() << "checking UseMI operands\n"); 703 switch (InstType) { 704 case rr2ri_rm: 705 UseIdx = 2; 706 if (UseMI.getOperand(1).getReg() == Reg) { 707 Commute = true; 708 } else { 709 assert(UseMI.getOperand(2).getReg() == Reg); 710 } 711 if (isInt<7>(ImmVal)) { 712 // This ImmVal matches to SImm7 slot, so change UseOpc to an instruction 713 // holds a simm7 slot. 714 NewUseOpc = NewUseOpcSImm7; 715 } else if (isMImmVal(ImmVal)) { 716 // Similarly, change UseOpc to an instruction holds a mimm slot. 717 NewUseOpc = NewUseOpcMImm; 718 ImmVal = val2MImm(ImmVal); 719 } else 720 return false; 721 break; 722 case rr2ir_rm: 723 if (UseMI.getOperand(1).getReg() == Reg) { 724 // Check immediate value whether it matchs to the UseMI instruction. 725 if (!isInt<7>(ImmVal)) 726 return false; 727 NewUseOpc = NewUseOpcSImm7; 728 UseIdx = 1; 729 } else { 730 assert(UseMI.getOperand(2).getReg() == Reg); 731 // Check immediate value whether it matchs to the UseMI instruction. 732 if (!isMImmVal(ImmVal)) 733 return false; 734 NewUseOpc = NewUseOpcMImm; 735 ImmVal = val2MImm(ImmVal); 736 UseIdx = 2; 737 } 738 break; 739 } 740 741 LLVM_DEBUG(dbgs() << "modifying UseMI\n"); 742 bool DeleteDef = MRI->hasOneNonDBGUse(Reg); 743 UseMI.setDesc(get(NewUseOpc)); 744 if (Commute) { 745 UseMI.getOperand(1).setReg(UseMI.getOperand(UseIdx).getReg()); 746 } 747 UseMI.getOperand(UseIdx).ChangeToImmediate(ImmVal); 748 if (DeleteDef) 749 DefMI.eraseFromParent(); 750 751 return true; 752 } 753 754 Register VEInstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 755 VEMachineFunctionInfo *VEFI = MF->getInfo<VEMachineFunctionInfo>(); 756 Register GlobalBaseReg = VEFI->getGlobalBaseReg(); 757 if (GlobalBaseReg != 0) 758 return GlobalBaseReg; 759 760 // We use %s15 (%got) as a global base register 761 GlobalBaseReg = VE::SX15; 762 763 // Insert a pseudo instruction to set the GlobalBaseReg into the first 764 // MBB of the function 765 MachineBasicBlock &FirstMBB = MF->front(); 766 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 767 DebugLoc dl; 768 BuildMI(FirstMBB, MBBI, dl, get(VE::GETGOT), GlobalBaseReg); 769 VEFI->setGlobalBaseReg(GlobalBaseReg); 770 return GlobalBaseReg; 771 } 772 773 static Register getVM512Upper(Register reg) { 774 return (reg - VE::VMP0) * 2 + VE::VM0; 775 } 776 777 static Register getVM512Lower(Register reg) { return getVM512Upper(reg) + 1; } 778 779 // Expand pseudo logical vector instructions for VM512 registers. 780 static void expandPseudoLogM(MachineInstr &MI, const MCInstrDesc &MCID) { 781 MachineBasicBlock *MBB = MI.getParent(); 782 DebugLoc DL = MI.getDebugLoc(); 783 784 Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 785 Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 786 Register VMYu = getVM512Upper(MI.getOperand(1).getReg()); 787 Register VMYl = getVM512Lower(MI.getOperand(1).getReg()); 788 789 switch (MI.getOpcode()) { 790 default: { 791 Register VMZu = getVM512Upper(MI.getOperand(2).getReg()); 792 Register VMZl = getVM512Lower(MI.getOperand(2).getReg()); 793 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); 794 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); 795 break; 796 } 797 case VE::NEGMy: 798 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); 799 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); 800 break; 801 } 802 MI.eraseFromParent(); 803 } 804 805 static void addOperandsForVFMK(MachineInstrBuilder &MIB, MachineInstr &MI, 806 bool Upper) { 807 // VM512 808 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(0).getReg()) 809 : getVM512Lower(MI.getOperand(0).getReg())); 810 811 switch (MI.getNumExplicitOperands()) { 812 default: 813 report_fatal_error("unexpected number of operands for pvfmk"); 814 case 2: // _Ml: VM512, VL 815 // VL 816 MIB.addReg(MI.getOperand(1).getReg()); 817 break; 818 case 4: // _Mvl: VM512, CC, VR, VL 819 // CC 820 MIB.addImm(MI.getOperand(1).getImm()); 821 // VR 822 MIB.addReg(MI.getOperand(2).getReg()); 823 // VL 824 MIB.addReg(MI.getOperand(3).getReg()); 825 break; 826 case 5: // _MvMl: VM512, CC, VR, VM512, VL 827 // CC 828 MIB.addImm(MI.getOperand(1).getImm()); 829 // VR 830 MIB.addReg(MI.getOperand(2).getReg()); 831 // VM512 832 MIB.addReg(Upper ? getVM512Upper(MI.getOperand(3).getReg()) 833 : getVM512Lower(MI.getOperand(3).getReg())); 834 // VL 835 MIB.addReg(MI.getOperand(4).getReg()); 836 break; 837 } 838 } 839 840 static void expandPseudoVFMK(const TargetInstrInfo &TI, MachineInstr &MI) { 841 // replace to pvfmk.w.up and pvfmk.w.lo 842 // replace to pvfmk.s.up and pvfmk.s.lo 843 844 static const std::pair<unsigned, std::pair<unsigned, unsigned>> VFMKMap[] = { 845 {VE::VFMKyal, {VE::VFMKLal, VE::VFMKLal}}, 846 {VE::VFMKynal, {VE::VFMKLnal, VE::VFMKLnal}}, 847 {VE::VFMKWyvl, {VE::PVFMKWUPvl, VE::PVFMKWLOvl}}, 848 {VE::VFMKWyvyl, {VE::PVFMKWUPvml, VE::PVFMKWLOvml}}, 849 {VE::VFMKSyvl, {VE::PVFMKSUPvl, VE::PVFMKSLOvl}}, 850 {VE::VFMKSyvyl, {VE::PVFMKSUPvml, VE::PVFMKSLOvml}}, 851 }; 852 853 unsigned Opcode = MI.getOpcode(); 854 855 const auto *Found = 856 llvm::find_if(VFMKMap, [&](auto P) { return P.first == Opcode; }); 857 if (Found == std::end(VFMKMap)) 858 report_fatal_error("unexpected opcode for pseudo vfmk"); 859 860 unsigned OpcodeUpper = (*Found).second.first; 861 unsigned OpcodeLower = (*Found).second.second; 862 863 MachineBasicBlock *MBB = MI.getParent(); 864 DebugLoc DL = MI.getDebugLoc(); 865 866 MachineInstrBuilder Bu = BuildMI(*MBB, MI, DL, TI.get(OpcodeUpper)); 867 addOperandsForVFMK(Bu, MI, /* Upper */ true); 868 MachineInstrBuilder Bl = BuildMI(*MBB, MI, DL, TI.get(OpcodeLower)); 869 addOperandsForVFMK(Bl, MI, /* Upper */ false); 870 871 MI.eraseFromParent(); 872 } 873 874 bool VEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 875 switch (MI.getOpcode()) { 876 case VE::EXTEND_STACK: { 877 return expandExtendStackPseudo(MI); 878 } 879 case VE::EXTEND_STACK_GUARD: { 880 MI.eraseFromParent(); // The pseudo instruction is gone now. 881 return true; 882 } 883 case VE::GETSTACKTOP: { 884 return expandGetStackTopPseudo(MI); 885 } 886 887 case VE::ANDMyy: 888 expandPseudoLogM(MI, get(VE::ANDMmm)); 889 return true; 890 case VE::ORMyy: 891 expandPseudoLogM(MI, get(VE::ORMmm)); 892 return true; 893 case VE::XORMyy: 894 expandPseudoLogM(MI, get(VE::XORMmm)); 895 return true; 896 case VE::EQVMyy: 897 expandPseudoLogM(MI, get(VE::EQVMmm)); 898 return true; 899 case VE::NNDMyy: 900 expandPseudoLogM(MI, get(VE::NNDMmm)); 901 return true; 902 case VE::NEGMy: 903 expandPseudoLogM(MI, get(VE::NEGMm)); 904 return true; 905 906 case VE::LVMyir: 907 case VE::LVMyim: 908 case VE::LVMyir_y: 909 case VE::LVMyim_y: { 910 Register VMXu = getVM512Upper(MI.getOperand(0).getReg()); 911 Register VMXl = getVM512Lower(MI.getOperand(0).getReg()); 912 int64_t Imm = MI.getOperand(1).getImm(); 913 bool IsSrcReg = 914 MI.getOpcode() == VE::LVMyir || MI.getOpcode() == VE::LVMyir_y; 915 Register Src = IsSrcReg ? MI.getOperand(2).getReg() : VE::NoRegister; 916 int64_t MImm = IsSrcReg ? 0 : MI.getOperand(2).getImm(); 917 bool KillSrc = IsSrcReg ? MI.getOperand(2).isKill() : false; 918 Register VMX = VMXl; 919 if (Imm >= 4) { 920 VMX = VMXu; 921 Imm -= 4; 922 } 923 MachineBasicBlock *MBB = MI.getParent(); 924 DebugLoc DL = MI.getDebugLoc(); 925 switch (MI.getOpcode()) { 926 case VE::LVMyir: 927 BuildMI(*MBB, MI, DL, get(VE::LVMir)) 928 .addDef(VMX) 929 .addImm(Imm) 930 .addReg(Src, getKillRegState(KillSrc)); 931 break; 932 case VE::LVMyim: 933 BuildMI(*MBB, MI, DL, get(VE::LVMim)) 934 .addDef(VMX) 935 .addImm(Imm) 936 .addImm(MImm); 937 break; 938 case VE::LVMyir_y: 939 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 940 "LVMyir_y has different register in 3rd operand"); 941 BuildMI(*MBB, MI, DL, get(VE::LVMir_m)) 942 .addDef(VMX) 943 .addImm(Imm) 944 .addReg(Src, getKillRegState(KillSrc)) 945 .addReg(VMX); 946 break; 947 case VE::LVMyim_y: 948 assert(MI.getOperand(0).getReg() == MI.getOperand(3).getReg() && 949 "LVMyim_y has different register in 3rd operand"); 950 BuildMI(*MBB, MI, DL, get(VE::LVMim_m)) 951 .addDef(VMX) 952 .addImm(Imm) 953 .addImm(MImm) 954 .addReg(VMX); 955 break; 956 } 957 MI.eraseFromParent(); 958 return true; 959 } 960 case VE::SVMyi: { 961 Register Dest = MI.getOperand(0).getReg(); 962 Register VMZu = getVM512Upper(MI.getOperand(1).getReg()); 963 Register VMZl = getVM512Lower(MI.getOperand(1).getReg()); 964 bool KillSrc = MI.getOperand(1).isKill(); 965 int64_t Imm = MI.getOperand(2).getImm(); 966 Register VMZ = VMZl; 967 if (Imm >= 4) { 968 VMZ = VMZu; 969 Imm -= 4; 970 } 971 MachineBasicBlock *MBB = MI.getParent(); 972 DebugLoc DL = MI.getDebugLoc(); 973 MachineInstrBuilder MIB = 974 BuildMI(*MBB, MI, DL, get(VE::SVMmi), Dest).addReg(VMZ).addImm(Imm); 975 MachineInstr *Inst = MIB.getInstr(); 976 if (KillSrc) { 977 const TargetRegisterInfo *TRI = &getRegisterInfo(); 978 Inst->addRegisterKilled(MI.getOperand(1).getReg(), TRI, true); 979 } 980 MI.eraseFromParent(); 981 return true; 982 } 983 case VE::VFMKyal: 984 case VE::VFMKynal: 985 case VE::VFMKWyvl: 986 case VE::VFMKWyvyl: 987 case VE::VFMKSyvl: 988 case VE::VFMKSyvyl: 989 expandPseudoVFMK(*this, MI); 990 return true; 991 } 992 return false; 993 } 994 995 bool VEInstrInfo::expandExtendStackPseudo(MachineInstr &MI) const { 996 MachineBasicBlock &MBB = *MI.getParent(); 997 MachineFunction &MF = *MBB.getParent(); 998 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 999 const VEInstrInfo &TII = *STI.getInstrInfo(); 1000 DebugLoc dl = MBB.findDebugLoc(MI); 1001 1002 // Create following instructions and multiple basic blocks. 1003 // 1004 // thisBB: 1005 // brge.l.t %sp, %sl, sinkBB 1006 // syscallBB: 1007 // ld %s61, 0x18(, %tp) // load param area 1008 // or %s62, 0, %s0 // spill the value of %s0 1009 // lea %s63, 0x13b // syscall # of grow 1010 // shm.l %s63, 0x0(%s61) // store syscall # at addr:0 1011 // shm.l %sl, 0x8(%s61) // store old limit at addr:8 1012 // shm.l %sp, 0x10(%s61) // store new limit at addr:16 1013 // monc // call monitor 1014 // or %s0, 0, %s62 // restore the value of %s0 1015 // sinkBB: 1016 1017 // Create new MBB 1018 MachineBasicBlock *BB = &MBB; 1019 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1020 MachineBasicBlock *syscallMBB = MF.CreateMachineBasicBlock(LLVM_BB); 1021 MachineBasicBlock *sinkMBB = MF.CreateMachineBasicBlock(LLVM_BB); 1022 MachineFunction::iterator It = ++(BB->getIterator()); 1023 MF.insert(It, syscallMBB); 1024 MF.insert(It, sinkMBB); 1025 1026 // Transfer the remainder of BB and its successor edges to sinkMBB. 1027 sinkMBB->splice(sinkMBB->begin(), BB, 1028 std::next(std::next(MachineBasicBlock::iterator(MI))), 1029 BB->end()); 1030 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1031 1032 // Next, add the true and fallthrough blocks as its successors. 1033 BB->addSuccessor(syscallMBB); 1034 BB->addSuccessor(sinkMBB); 1035 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) 1036 .addImm(VECC::CC_IGE) 1037 .addReg(VE::SX11) // %sp 1038 .addReg(VE::SX8) // %sl 1039 .addMBB(sinkMBB); 1040 1041 BB = syscallMBB; 1042 1043 // Update machine-CFG edges 1044 BB->addSuccessor(sinkMBB); 1045 1046 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) 1047 .addReg(VE::SX14) 1048 .addImm(0) 1049 .addImm(0x18); 1050 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 1051 .addReg(VE::SX0) 1052 .addImm(0); 1053 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) 1054 .addImm(0) 1055 .addImm(0) 1056 .addImm(0x13b); 1057 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1058 .addReg(VE::SX61) 1059 .addImm(0) 1060 .addReg(VE::SX63); 1061 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1062 .addReg(VE::SX61) 1063 .addImm(8) 1064 .addReg(VE::SX8); 1065 BuildMI(BB, dl, TII.get(VE::SHMLri)) 1066 .addReg(VE::SX61) 1067 .addImm(16) 1068 .addReg(VE::SX11); 1069 BuildMI(BB, dl, TII.get(VE::MONC)); 1070 1071 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX0) 1072 .addReg(VE::SX62) 1073 .addImm(0); 1074 1075 MI.eraseFromParent(); // The pseudo instruction is gone now. 1076 return true; 1077 } 1078 1079 bool VEInstrInfo::expandGetStackTopPseudo(MachineInstr &MI) const { 1080 MachineBasicBlock *MBB = MI.getParent(); 1081 MachineFunction &MF = *MBB->getParent(); 1082 const VESubtarget &STI = MF.getSubtarget<VESubtarget>(); 1083 const VEInstrInfo &TII = *STI.getInstrInfo(); 1084 DebugLoc DL = MBB->findDebugLoc(MI); 1085 1086 // Create following instruction 1087 // 1088 // dst = %sp + target specific frame + the size of parameter area 1089 1090 const MachineFrameInfo &MFI = MF.getFrameInfo(); 1091 const VEFrameLowering &TFL = *STI.getFrameLowering(); 1092 1093 // The VE ABI requires a reserved area at the top of stack as described 1094 // in VEFrameLowering.cpp. So, we adjust it here. 1095 unsigned NumBytes = STI.getAdjustedFrameSize(0); 1096 1097 // Also adds the size of parameter area. 1098 if (MFI.adjustsStack() && TFL.hasReservedCallFrame(MF)) 1099 NumBytes += MFI.getMaxCallFrameSize(); 1100 1101 BuildMI(*MBB, MI, DL, TII.get(VE::LEArii)) 1102 .addDef(MI.getOperand(0).getReg()) 1103 .addReg(VE::SX11) 1104 .addImm(0) 1105 .addImm(NumBytes); 1106 1107 MI.eraseFromParent(); // The pseudo instruction is gone now. 1108 return true; 1109 } 1110