1//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9// SX-Aurora uses little endian, but instructions are encoded little bit 10// different manner. Therefore, we need to tranlate the address of each 11// bitfield described in ISA documentation like below. 12// 13// ISA | InstrFormats.td 14// --------------------------- 15// 0-7 => 63-56 16// 8 => 55 17// 32-63 => 31-0 18 19//===----------------------------------------------------------------------===// 20// Instruction Format 21//===----------------------------------------------------------------------===// 22 23class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> 24 : Instruction { 25 field bits<64> Inst; 26 27 let Namespace = "VE"; 28 let Size = 8; 29 30 bits<8> op; 31 let Inst{63-56} = op; 32 33 dag OutOperandList = outs; 34 dag InOperandList = ins; 35 let AsmString = asmstr; 36 let Pattern = pattern; 37 38 let DecoderNamespace = "VE"; 39 field bits<64> SoftFail = 0; 40} 41 42//----------------------------------------------------------------------------- 43// Section 5.1 RM Type 44// 45// RM type has sx, sy, sz, and imm32. 46// The effective address is generated by sz + sy + imm32. 47//----------------------------------------------------------------------------- 48 49class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> 50 : InstVE<outs, ins, asmstr, pattern> { 51 bits<1> cx = 0; 52 bits<7> sx; 53 bits<1> cy = 1; 54 bits<7> sz; // defines sz prior to sy to assign from sz 55 bits<7> sy; 56 bits<1> cz = 1; 57 bits<32> imm32; 58 let op = opVal; 59 let Inst{55} = cx; 60 let Inst{54-48} = sx; 61 let Inst{47} = cy; 62 let Inst{46-40} = sy; 63 let Inst{39} = cz; 64 let Inst{38-32} = sz; 65 let Inst{31-0} = imm32; 66} 67 68//----------------------------------------------------------------------------- 69// Section 5.2 RRM Type 70// 71// RRM type is identical to RM, but the effective address is generated 72// by sz + imm32. The sy field is used by other purposes. 73//----------------------------------------------------------------------------- 74 75class RRM<bits<8>opVal, dag outs, dag ins, string asmstr, 76 list<dag> pattern = []> 77 : RM<opVal, outs, ins, asmstr, pattern>; 78 79// RRMHM type is to load/store host memory 80// It is similar to RRM and not use sy. 81class RRMHM<bits<8>opVal, dag outs, dag ins, string asmstr, 82 list<dag> pattern = []> 83 : RRM<opVal, outs, ins, asmstr, pattern> { 84 bits<2> ry = 0; 85 let cy = 0; 86 let sy{6-2} = 0; 87 let sy{1-0} = ry; 88} 89 90//----------------------------------------------------------------------------- 91// Section 5.3 CF Type 92// 93// CF type is used for control flow. 94//----------------------------------------------------------------------------- 95 96class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> 97 : InstVE<outs, ins, asmstr, pattern> { 98 bits<1> cx = 0; 99 bits<1> cx2 = 0; 100 bits<2> bpf = 0; 101 bits<4> cf; 102 bits<1> cy = 1; 103 bits<7> sy; 104 bits<1> cz = 1; 105 bits<7> sz; 106 bits<32> imm32; 107 let op = opVal; 108 let Inst{55} = cx; 109 let Inst{54} = cx2; 110 let Inst{53-52} = bpf; 111 let Inst{51-48} = cf; 112 let Inst{47} = cy; 113 let Inst{46-40} = sy; 114 let Inst{39} = cz; 115 let Inst{38-32} = sz; 116 let Inst{31-0} = imm32; 117} 118 119//----------------------------------------------------------------------------- 120// Section 5.4 RR Type 121// 122// RR type is for generic arithmetic instructions. 123//----------------------------------------------------------------------------- 124 125class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []> 126 : InstVE<outs, ins, asmstr, pattern> { 127 bits<1> cx = 0; 128 bits<7> sx; 129 bits<1> cy = 1; 130 bits<7> sy; 131 bits<1> cz = 1; 132 bits<7> sz; // m field places at the top sz field 133 bits<8> vx = 0; 134 bits<8> vz = 0; 135 bits<1> cw = 0; 136 bits<1> cw2 = 0; 137 bits<4> cfw = 0; 138 let op = opVal; 139 let Inst{55} = cx; 140 let Inst{54-48} = sx; 141 let Inst{47} = cy; 142 let Inst{46-40} = sy; 143 let Inst{39} = cz; 144 let Inst{38-32} = sz; 145 let Inst{31-24} = vx; 146 let Inst{23-16} = 0; 147 let Inst{15-8} = vz; 148 let Inst{7} = cw; 149 let Inst{6} = cw2; 150 let Inst{5-4} = 0; 151 let Inst{3-0} = cfw; 152} 153 154// RRFENCE type is special RR type for a FENCE instruction. 155class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr, 156 list<dag> pattern = []> 157 : InstVE<outs, ins, asmstr, pattern> { 158 bits<1> avo = 0; 159 bits<1> lf = 0; 160 bits<1> sf = 0; 161 bits<1> c2 = 0; 162 bits<1> c1 = 0; 163 bits<1> c0 = 0; 164 let op = opVal; 165 let Inst{55} = avo; 166 let Inst{54-50} = 0; 167 let Inst{49} = lf; 168 let Inst{48} = sf; 169 let Inst{47-43} = 0; 170 let Inst{42} = c2; 171 let Inst{41} = c1; 172 let Inst{40} = c0; 173 let Inst{39-0} = 0; 174} 175 176//----------------------------------------------------------------------------- 177// Section 5.5 RW Type 178//----------------------------------------------------------------------------- 179 180//----------------------------------------------------------------------------- 181// Section 5.6 RVM Type 182//----------------------------------------------------------------------------- 183 184//----------------------------------------------------------------------------- 185// Section 5.7 RV Type 186//----------------------------------------------------------------------------- 187 188// Pseudo instructions. 189class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = []> 190 : InstVE<outs, ins, asmstr, pattern> { 191 let isCodeGenOnly = 1; 192 let isPseudo = 1; 193} 194