1//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern> 10 : Instruction { 11 field bits<64> Inst; 12 13 let Namespace = "VE"; 14 let Size = 8; 15 16 bits<8> op; 17 let Inst{0-7} = op; 18 19 dag OutOperandList = outs; 20 dag InOperandList = ins; 21 let AsmString = asmstr; 22 let Pattern = pattern; 23 24 let DecoderNamespace = "VE"; 25 field bits<64> SoftFail = 0; 26} 27 28class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> 29 : InstVE<outs, ins, asmstr, pattern> { 30 bits<1> cx = 0; 31 bits<7> sx; 32 bits<1> cy = 0; 33 bits<7> sy; 34 bits<1> cz = 0; 35 bits<7> sz; 36 bits<32> imm32 = 0; 37 let op = opVal; 38 let Inst{15} = cx; 39 let Inst{14-8} = sx; 40 let Inst{23} = cy; 41 let Inst{22-16} = sy; 42 let Inst{31} = cz; 43 let Inst{30-24} = sz; 44 let Inst{63-32} = imm32; 45} 46 47class RR<bits<8>opVal, dag outs, dag ins, string asmstr> 48 : RM<opVal, outs, ins, asmstr> { 49 bits<1> cw = 0; 50 bits<1> cw2 = 0; 51 bits<4> cfw = 0; 52 let imm32{0-23} = 0; 53 let imm32{24} = cw; 54 let imm32{25} = cw2; 55 let imm32{26-27} = 0; 56 let imm32{28-31} = cfw; 57} 58 59class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]> 60 : RM<opVal, outs, ins, asmstr, pattern> { 61 bits<1> cx2; 62 bits<2> bpf; 63 bits<4> cf; 64 let cx = 0; 65 let sx{6} = cx2; 66 let sx{5-4} = bpf; 67 let sx{3-0} = cf; 68} 69 70// Pseudo instructions. 71class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]> 72 : InstVE<outs, ins, asmstr, pattern> { 73 let isCodeGenOnly = 1; 74 let isPseudo = 1; 75} 76