1 //===-- VEISelLowering.h - VE DAG Lowering Interface ------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines the interfaces that VE uses to lower LLVM code into a 10 // selection DAG. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_VE_VEISELLOWERING_H 15 #define LLVM_LIB_TARGET_VE_VEISELLOWERING_H 16 17 #include "VE.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 20 namespace llvm { 21 class VESubtarget; 22 23 namespace VEISD { 24 enum NodeType : unsigned { 25 FIRST_NUMBER = ISD::BUILTIN_OP_END, 26 27 Hi, 28 Lo, // Hi/Lo operations, typically on a global address. 29 30 GETFUNPLT, // load function address through %plt insturction 31 GETTLSADDR, // load address for TLS access 32 GETSTACKTOP, // retrieve address of stack top (first address of 33 // locals and temporaries) 34 35 CALL, // A call instruction. 36 RET_FLAG, // Return with a flag operand. 37 GLOBAL_BASE_REG, // Global base reg for PIC. 38 }; 39 } 40 41 class VETargetLowering : public TargetLowering { 42 const VESubtarget *Subtarget; 43 44 public: 45 VETargetLowering(const TargetMachine &TM, const VESubtarget &STI); 46 47 const char *getTargetNodeName(unsigned Opcode) const override; 48 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 49 return MVT::i32; 50 } 51 52 Register getRegisterByName(const char *RegName, LLT VT, 53 const MachineFunction &MF) const override; 54 55 /// getSetCCResultType - Return the ISD::SETCC ValueType 56 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 57 EVT VT) const override; 58 59 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 60 bool isVarArg, 61 const SmallVectorImpl<ISD::InputArg> &Ins, 62 const SDLoc &dl, SelectionDAG &DAG, 63 SmallVectorImpl<SDValue> &InVals) const override; 64 65 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 66 SmallVectorImpl<SDValue> &InVals) const override; 67 68 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 69 bool isVarArg, 70 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, 71 LLVMContext &Context) const override; 72 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, 73 const SmallVectorImpl<ISD::OutputArg> &Outs, 74 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl, 75 SelectionDAG &DAG) const override; 76 77 /// Custom Lower { 78 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 79 80 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 81 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 82 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 83 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 84 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 85 SDValue LowerToTLSGeneralDynamicModel(SDValue Op, SelectionDAG &DAG) const; 86 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 87 /// } Custom Lower 88 89 SDValue withTargetFlags(SDValue Op, unsigned TF, SelectionDAG &DAG) const; 90 SDValue makeHiLoPair(SDValue Op, unsigned HiTF, unsigned LoTF, 91 SelectionDAG &DAG) const; 92 SDValue makeAddress(SDValue Op, SelectionDAG &DAG) const; 93 94 bool isFPImmLegal(const APFloat &Imm, EVT VT, 95 bool ForCodeSize) const override; 96 /// Returns true if the target allows unaligned memory accesses of the 97 /// specified type. 98 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, 99 MachineMemOperand::Flags Flags, 100 bool *Fast) const override; 101 102 // Block s/udiv lowering for now 103 bool isIntDivCheap(EVT VT, AttributeList Attr) const override { return true; } 104 105 bool hasAndNot(SDValue Y) const override; 106 }; 107 } // namespace llvm 108 109 #endif // VE_ISELLOWERING_H 110