1//===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This describes the calling conventions for the VE architectures. 10// 11//===----------------------------------------------------------------------===// 12 13//===----------------------------------------------------------------------===// 14// Aurora VE 15//===----------------------------------------------------------------------===// 16def CC_VE_C_Stack: CallingConv<[ 17 // float --> need special handling like below. 18 // 0 4 19 // +------+------+ 20 // | empty| float| 21 // +------+------+ 22 CCIfType<[f32], CCCustom<"allocateFloat">>, 23 24 // All of the rest are assigned to the stack in 8-byte aligned units. 25 CCAssignToStack<0, 8> 26]>; 27 28def CC_VE : CallingConv<[ 29 // All arguments get passed in generic registers if there is space. 30 31 // Promote i1/i8/i16 arguments to i32. 32 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 33 34 // bool, char, int, enum, long --> generic integer 32 bit registers 35 CCIfType<[i32], CCAssignToRegWithShadow< 36 [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7], 37 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 38 39 // float --> generic floating point 32 bit registers 40 CCIfType<[f32], CCAssignToRegWithShadow< 41 [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7], 42 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 43 44 // long long/double --> generic 64 bit registers 45 CCIfType<[i64, f64], 46 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 47 48 // Alternatively, they are assigned to the stack in 8-byte aligned units. 49 CCDelegateTo<CC_VE_C_Stack> 50]>; 51 52// All arguments get passed in stack for varargs function or non-prototyped 53// function. 54def CC_VE2 : CallingConv<[ 55 // float --> need special handling like below. 56 // 0 4 57 // +------+------+ 58 // | empty| float| 59 // +------+------+ 60 CCIfType<[f32], CCCustom<"allocateFloat">>, 61 62 CCAssignToStack<0, 8> 63]>; 64 65def RetCC_VE : CallingConv<[ 66 // Promote i1/i8/i16 arguments to i32. 67 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 68 69 // bool, char, int, enum, long --> generic integer 32 bit registers 70 CCIfType<[i32], CCAssignToRegWithShadow< 71 [SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7], 72 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 73 74 // float --> generic floating point 32 bit registers 75 CCIfType<[f32], CCAssignToRegWithShadow< 76 [SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7], 77 [SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 78 79 // long long/double --> generic 64 bit registers 80 CCIfType<[i64, f64], 81 CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>, 82]>; 83 84// Callee-saved registers 85def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>; 86def CSR_NoRegs : CalleeSavedRegs<(add)>; 87 88// PreserveAll (clobbers s62,s63) - used for ve_grow_stack 89def CSR_preserve_all : CalleeSavedRegs<(add (sequence "SX%u", 0, 61))>; 90