1//===-- VE.td - Describe the VE Target Machine -------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces which we are implementing 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// VE Subtarget features. 20// 21def FeatureEnableVPU 22 : SubtargetFeature<"vpu", "EnableVPU", "true", 23 "Enable the VPU">; 24 25//===----------------------------------------------------------------------===// 26// Register File, Calling Conv, Instruction Descriptions 27//===----------------------------------------------------------------------===// 28 29include "VERegisterInfo.td" 30include "VECallingConv.td" 31include "VEInstrInfo.td" 32 33def VEInstrInfo : InstrInfo { 34 let useDeprecatedPositionallyEncodedOperands = 1; 35} 36 37def VEAsmParser : AsmParser { 38 // Use both VE register name matcher to accept "S0~S63" register names 39 // and default register matcher to accept other registeres. 40 let AllowDuplicateRegisterNames = 1; 41 let ShouldEmitMatchRegisterAltName = 1; 42} 43 44//===----------------------------------------------------------------------===// 45// VE processors supported. 46//===----------------------------------------------------------------------===// 47 48class Proc<string Name, list<SubtargetFeature> Features> 49 : Processor<Name, NoItineraries, Features>; 50 51def : Proc<"generic", []>; 52 53//===----------------------------------------------------------------------===// 54// Declare the target which we are implementing 55//===----------------------------------------------------------------------===// 56 57def VEAsmWriter : AsmWriter { 58 string AsmWriterClassName = "InstPrinter"; 59 int PassSubtarget = 1; 60 int Variant = 0; 61} 62 63def VE : Target { 64 // Pull in Instruction Info: 65 let InstructionSet = VEInstrInfo; 66 let AssemblyParsers = [VEAsmParser]; 67 let AssemblyWriters = [VEAsmWriter]; 68 let AllowRegisterRenaming = 1; 69} 70