xref: /freebsd/contrib/llvm-project/llvm/lib/Target/VE/Disassembler/VEDisassembler.cpp (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229)
1 //===- VEDisassembler.cpp - Disassembler for VE -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the VE Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "MCTargetDesc/VEMCTargetDesc.h"
14 #include "TargetInfo/VETargetInfo.h"
15 #include "VE.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/TargetRegistry.h"
22 
23 using namespace llvm;
24 
25 #define DEBUG_TYPE "ve-disassembler"
26 
27 typedef MCDisassembler::DecodeStatus DecodeStatus;
28 
29 namespace {
30 
31 /// A disassembler class for VE.
32 class VEDisassembler : public MCDisassembler {
33 public:
34   VEDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
35       : MCDisassembler(STI, Ctx) {}
36   virtual ~VEDisassembler() {}
37 
38   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
39                               ArrayRef<uint8_t> Bytes, uint64_t Address,
40                               raw_ostream &CStream) const override;
41 };
42 } // namespace
43 
44 static MCDisassembler *createVEDisassembler(const Target &T,
45                                             const MCSubtargetInfo &STI,
46                                             MCContext &Ctx) {
47   return new VEDisassembler(STI, Ctx);
48 }
49 
50 extern "C" void LLVMInitializeVEDisassembler() {
51   // Register the disassembler.
52   TargetRegistry::RegisterMCDisassembler(getTheVETarget(),
53                                          createVEDisassembler);
54 }
55 
56 static const unsigned I32RegDecoderTable[] = {
57     VE::SW0,  VE::SW1,  VE::SW2,  VE::SW3,  VE::SW4,  VE::SW5,  VE::SW6,
58     VE::SW7,  VE::SW8,  VE::SW9,  VE::SW10, VE::SW11, VE::SW12, VE::SW13,
59     VE::SW14, VE::SW15, VE::SW16, VE::SW17, VE::SW18, VE::SW19, VE::SW20,
60     VE::SW21, VE::SW22, VE::SW23, VE::SW24, VE::SW25, VE::SW26, VE::SW27,
61     VE::SW28, VE::SW29, VE::SW30, VE::SW31, VE::SW32, VE::SW33, VE::SW34,
62     VE::SW35, VE::SW36, VE::SW37, VE::SW38, VE::SW39, VE::SW40, VE::SW41,
63     VE::SW42, VE::SW43, VE::SW44, VE::SW45, VE::SW46, VE::SW47, VE::SW48,
64     VE::SW49, VE::SW50, VE::SW51, VE::SW52, VE::SW53, VE::SW54, VE::SW55,
65     VE::SW56, VE::SW57, VE::SW58, VE::SW59, VE::SW60, VE::SW61, VE::SW62,
66     VE::SW63};
67 
68 static const unsigned I64RegDecoderTable[] = {
69     VE::SX0,  VE::SX1,  VE::SX2,  VE::SX3,  VE::SX4,  VE::SX5,  VE::SX6,
70     VE::SX7,  VE::SX8,  VE::SX9,  VE::SX10, VE::SX11, VE::SX12, VE::SX13,
71     VE::SX14, VE::SX15, VE::SX16, VE::SX17, VE::SX18, VE::SX19, VE::SX20,
72     VE::SX21, VE::SX22, VE::SX23, VE::SX24, VE::SX25, VE::SX26, VE::SX27,
73     VE::SX28, VE::SX29, VE::SX30, VE::SX31, VE::SX32, VE::SX33, VE::SX34,
74     VE::SX35, VE::SX36, VE::SX37, VE::SX38, VE::SX39, VE::SX40, VE::SX41,
75     VE::SX42, VE::SX43, VE::SX44, VE::SX45, VE::SX46, VE::SX47, VE::SX48,
76     VE::SX49, VE::SX50, VE::SX51, VE::SX52, VE::SX53, VE::SX54, VE::SX55,
77     VE::SX56, VE::SX57, VE::SX58, VE::SX59, VE::SX60, VE::SX61, VE::SX62,
78     VE::SX63};
79 
80 static const unsigned F32RegDecoderTable[] = {
81     VE::SF0,  VE::SF1,  VE::SF2,  VE::SF3,  VE::SF4,  VE::SF5,  VE::SF6,
82     VE::SF7,  VE::SF8,  VE::SF9,  VE::SF10, VE::SF11, VE::SF12, VE::SF13,
83     VE::SF14, VE::SF15, VE::SF16, VE::SF17, VE::SF18, VE::SF19, VE::SF20,
84     VE::SF21, VE::SF22, VE::SF23, VE::SF24, VE::SF25, VE::SF26, VE::SF27,
85     VE::SF28, VE::SF29, VE::SF30, VE::SF31, VE::SF32, VE::SF33, VE::SF34,
86     VE::SF35, VE::SF36, VE::SF37, VE::SF38, VE::SF39, VE::SF40, VE::SF41,
87     VE::SF42, VE::SF43, VE::SF44, VE::SF45, VE::SF46, VE::SF47, VE::SF48,
88     VE::SF49, VE::SF50, VE::SF51, VE::SF52, VE::SF53, VE::SF54, VE::SF55,
89     VE::SF56, VE::SF57, VE::SF58, VE::SF59, VE::SF60, VE::SF61, VE::SF62,
90     VE::SF63};
91 
92 static const unsigned F128RegDecoderTable[] = {
93     VE::Q0,  VE::Q1,  VE::Q2,  VE::Q3,  VE::Q4,  VE::Q5,  VE::Q6,  VE::Q7,
94     VE::Q8,  VE::Q9,  VE::Q10, VE::Q11, VE::Q12, VE::Q13, VE::Q14, VE::Q15,
95     VE::Q16, VE::Q17, VE::Q18, VE::Q19, VE::Q20, VE::Q21, VE::Q22, VE::Q23,
96     VE::Q24, VE::Q25, VE::Q26, VE::Q27, VE::Q28, VE::Q29, VE::Q30, VE::Q31};
97 
98 static const unsigned MiscRegDecoderTable[] = {
99     VE::USRCC,      VE::PSW,        VE::SAR,        VE::NoRegister,
100     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::PMMR,
101     VE::PMCR0,      VE::PMCR1,      VE::PMCR2,      VE::PMCR3,
102     VE::NoRegister, VE::NoRegister, VE::NoRegister, VE::NoRegister,
103     VE::PMC0,       VE::PMC1,       VE::PMC2,       VE::PMC3,
104     VE::PMC4,       VE::PMC5,       VE::PMC6,       VE::PMC7,
105     VE::PMC8,       VE::PMC9,       VE::PMC10,      VE::PMC11,
106     VE::PMC12,      VE::PMC13,      VE::PMC14};
107 
108 static DecodeStatus DecodeI32RegisterClass(MCInst &Inst, unsigned RegNo,
109                                            uint64_t Address,
110                                            const void *Decoder) {
111   if (RegNo > 63)
112     return MCDisassembler::Fail;
113   unsigned Reg = I32RegDecoderTable[RegNo];
114   Inst.addOperand(MCOperand::createReg(Reg));
115   return MCDisassembler::Success;
116 }
117 
118 static DecodeStatus DecodeI64RegisterClass(MCInst &Inst, unsigned RegNo,
119                                            uint64_t Address,
120                                            const void *Decoder) {
121   if (RegNo > 63)
122     return MCDisassembler::Fail;
123   unsigned Reg = I64RegDecoderTable[RegNo];
124   Inst.addOperand(MCOperand::createReg(Reg));
125   return MCDisassembler::Success;
126 }
127 
128 static DecodeStatus DecodeF32RegisterClass(MCInst &Inst, unsigned RegNo,
129                                            uint64_t Address,
130                                            const void *Decoder) {
131   if (RegNo > 63)
132     return MCDisassembler::Fail;
133   unsigned Reg = F32RegDecoderTable[RegNo];
134   Inst.addOperand(MCOperand::createReg(Reg));
135   return MCDisassembler::Success;
136 }
137 
138 static DecodeStatus DecodeF128RegisterClass(MCInst &Inst, unsigned RegNo,
139                                             uint64_t Address,
140                                             const void *Decoder) {
141   if (RegNo % 2 || RegNo > 63)
142     return MCDisassembler::Fail;
143   unsigned Reg = F128RegDecoderTable[RegNo / 2];
144   Inst.addOperand(MCOperand::createReg(Reg));
145   return MCDisassembler::Success;
146 }
147 
148 static DecodeStatus DecodeMISCRegisterClass(MCInst &Inst, unsigned RegNo,
149                                             uint64_t Address,
150                                             const void *Decoder) {
151   if (RegNo > 30)
152     return MCDisassembler::Fail;
153   unsigned Reg = MiscRegDecoderTable[RegNo];
154   if (Reg == VE::NoRegister)
155     return MCDisassembler::Fail;
156   Inst.addOperand(MCOperand::createReg(Reg));
157   return MCDisassembler::Success;
158 }
159 
160 static DecodeStatus DecodeASX(MCInst &Inst, uint64_t insn, uint64_t Address,
161                               const void *Decoder);
162 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
163                                   const void *Decoder);
164 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
165                                    uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
167                                   const void *Decoder);
168 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
169                                    uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
171                                   const void *Decoder);
172 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
173                                    uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
175                                     uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
177                                      uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeTS1AMI64(MCInst &Inst, uint64_t insn,
179                                    uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeTS1AMI32(MCInst &Inst, uint64_t insn,
181                                    uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeCASI64(MCInst &Inst, uint64_t insn, uint64_t Address,
183                                  const void *Decoder);
184 static DecodeStatus DecodeCASI32(MCInst &Inst, uint64_t insn, uint64_t Address,
185                                  const void *Decoder);
186 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
187                                const void *Decoder);
188 static DecodeStatus DecodeSIMM7(MCInst &Inst, uint64_t insn, uint64_t Address,
189                                 const void *Decoder);
190 static DecodeStatus DecodeSIMM32(MCInst &Inst, uint64_t insn, uint64_t Address,
191                                  const void *Decoder);
192 static DecodeStatus DecodeCCOperand(MCInst &Inst, uint64_t insn,
193                                     uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRDOperand(MCInst &Inst, uint64_t insn,
195                                     uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeBranchCondition(MCInst &Inst, uint64_t insn,
197                                           uint64_t Address,
198                                           const void *Decoder);
199 static DecodeStatus DecodeBranchConditionAlways(MCInst &Inst, uint64_t insn,
200                                                 uint64_t Address,
201                                                 const void *Decoder);
202 
203 #include "VEGenDisassemblerTables.inc"
204 
205 /// Read four bytes from the ArrayRef and return 32 bit word.
206 static DecodeStatus readInstruction64(ArrayRef<uint8_t> Bytes, uint64_t Address,
207                                       uint64_t &Size, uint64_t &Insn,
208                                       bool IsLittleEndian) {
209   // We want to read exactly 8 Bytes of data.
210   if (Bytes.size() < 8) {
211     Size = 0;
212     return MCDisassembler::Fail;
213   }
214 
215   Insn = IsLittleEndian
216              ? ((uint64_t)Bytes[0] << 0) | ((uint64_t)Bytes[1] << 8) |
217                    ((uint64_t)Bytes[2] << 16) | ((uint64_t)Bytes[3] << 24) |
218                    ((uint64_t)Bytes[4] << 32) | ((uint64_t)Bytes[5] << 40) |
219                    ((uint64_t)Bytes[6] << 48) | ((uint64_t)Bytes[7] << 56)
220              : ((uint64_t)Bytes[7] << 0) | ((uint64_t)Bytes[6] << 8) |
221                    ((uint64_t)Bytes[5] << 16) | ((uint64_t)Bytes[4] << 24) |
222                    ((uint64_t)Bytes[3] << 32) | ((uint64_t)Bytes[2] << 40) |
223                    ((uint64_t)Bytes[1] << 48) | ((uint64_t)Bytes[0] << 56);
224 
225   return MCDisassembler::Success;
226 }
227 
228 DecodeStatus VEDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
229                                             ArrayRef<uint8_t> Bytes,
230                                             uint64_t Address,
231                                             raw_ostream &CStream) const {
232   uint64_t Insn;
233   bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
234   DecodeStatus Result =
235       readInstruction64(Bytes, Address, Size, Insn, isLittleEndian);
236   if (Result == MCDisassembler::Fail)
237     return MCDisassembler::Fail;
238 
239   // Calling the auto-generated decoder function.
240 
241   Result = decodeInstruction(DecoderTableVE64, Instr, Insn, Address, this, STI);
242 
243   if (Result != MCDisassembler::Fail) {
244     Size = 8;
245     return Result;
246   }
247 
248   return MCDisassembler::Fail;
249 }
250 
251 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned RegNo, uint64_t Address,
252                                    const void *Decoder);
253 
254 static DecodeStatus DecodeASX(MCInst &MI, uint64_t insn, uint64_t Address,
255                               const void *Decoder) {
256   unsigned sy = fieldFromInstruction(insn, 40, 7);
257   bool cy = fieldFromInstruction(insn, 47, 1);
258   unsigned sz = fieldFromInstruction(insn, 32, 7);
259   bool cz = fieldFromInstruction(insn, 39, 1);
260   uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
261   DecodeStatus status;
262 
263   // Decode sz.
264   if (cz) {
265     status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
266     if (status != MCDisassembler::Success)
267       return status;
268   } else {
269     MI.addOperand(MCOperand::createImm(0));
270   }
271 
272   // Decode sy.
273   if (cy) {
274     status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
275     if (status != MCDisassembler::Success)
276       return status;
277   } else {
278     MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
279   }
280 
281   // Decode simm32.
282   MI.addOperand(MCOperand::createImm(simm32));
283 
284   return MCDisassembler::Success;
285 }
286 
287 static DecodeStatus DecodeAS(MCInst &MI, uint64_t insn, uint64_t Address,
288                              const void *Decoder) {
289   unsigned sz = fieldFromInstruction(insn, 32, 7);
290   bool cz = fieldFromInstruction(insn, 39, 1);
291   uint64_t simm32 = SignExtend64<32>(fieldFromInstruction(insn, 0, 32));
292   DecodeStatus status;
293 
294   // Decode sz.
295   if (cz) {
296     status = DecodeI64RegisterClass(MI, sz, Address, Decoder);
297     if (status != MCDisassembler::Success)
298       return status;
299   } else {
300     MI.addOperand(MCOperand::createImm(0));
301   }
302 
303   // Decode simm32.
304   MI.addOperand(MCOperand::createImm(simm32));
305 
306   return MCDisassembler::Success;
307 }
308 
309 static DecodeStatus DecodeMem(MCInst &MI, uint64_t insn, uint64_t Address,
310                               const void *Decoder, bool isLoad,
311                               DecodeFunc DecodeSX) {
312   unsigned sx = fieldFromInstruction(insn, 48, 7);
313 
314   DecodeStatus status;
315   if (isLoad) {
316     status = DecodeSX(MI, sx, Address, Decoder);
317     if (status != MCDisassembler::Success)
318       return status;
319   }
320 
321   status = DecodeASX(MI, insn, Address, Decoder);
322   if (status != MCDisassembler::Success)
323     return status;
324 
325   if (!isLoad) {
326     status = DecodeSX(MI, sx, Address, Decoder);
327     if (status != MCDisassembler::Success)
328       return status;
329   }
330   return MCDisassembler::Success;
331 }
332 
333 static DecodeStatus DecodeMemAS(MCInst &MI, uint64_t insn, uint64_t Address,
334                                 const void *Decoder, bool isLoad,
335                                 DecodeFunc DecodeSX) {
336   unsigned sx = fieldFromInstruction(insn, 48, 7);
337 
338   DecodeStatus status;
339   if (isLoad) {
340     status = DecodeSX(MI, sx, Address, Decoder);
341     if (status != MCDisassembler::Success)
342       return status;
343   }
344 
345   status = DecodeAS(MI, insn, Address, Decoder);
346   if (status != MCDisassembler::Success)
347     return status;
348 
349   if (!isLoad) {
350     status = DecodeSX(MI, sx, Address, Decoder);
351     if (status != MCDisassembler::Success)
352       return status;
353   }
354   return MCDisassembler::Success;
355 }
356 
357 static DecodeStatus DecodeLoadI32(MCInst &Inst, uint64_t insn, uint64_t Address,
358                                   const void *Decoder) {
359   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI32RegisterClass);
360 }
361 
362 static DecodeStatus DecodeStoreI32(MCInst &Inst, uint64_t insn,
363                                    uint64_t Address, const void *Decoder) {
364   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI32RegisterClass);
365 }
366 
367 static DecodeStatus DecodeLoadI64(MCInst &Inst, uint64_t insn, uint64_t Address,
368                                   const void *Decoder) {
369   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
370 }
371 
372 static DecodeStatus DecodeStoreI64(MCInst &Inst, uint64_t insn,
373                                    uint64_t Address, const void *Decoder) {
374   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeI64RegisterClass);
375 }
376 
377 static DecodeStatus DecodeLoadF32(MCInst &Inst, uint64_t insn, uint64_t Address,
378                                   const void *Decoder) {
379   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeF32RegisterClass);
380 }
381 
382 static DecodeStatus DecodeStoreF32(MCInst &Inst, uint64_t insn,
383                                    uint64_t Address, const void *Decoder) {
384   return DecodeMem(Inst, insn, Address, Decoder, false, DecodeF32RegisterClass);
385 }
386 
387 static DecodeStatus DecodeLoadASI64(MCInst &Inst, uint64_t insn,
388                                     uint64_t Address, const void *Decoder) {
389   return DecodeMemAS(Inst, insn, Address, Decoder, true,
390                      DecodeI64RegisterClass);
391 }
392 
393 static DecodeStatus DecodeStoreASI64(MCInst &Inst, uint64_t insn,
394                                      uint64_t Address, const void *Decoder) {
395   return DecodeMemAS(Inst, insn, Address, Decoder, false,
396                      DecodeI64RegisterClass);
397 }
398 
399 static DecodeStatus DecodeCAS(MCInst &MI, uint64_t insn, uint64_t Address,
400                               const void *Decoder, bool isImmOnly, bool isUImm,
401                               DecodeFunc DecodeSX) {
402   unsigned sx = fieldFromInstruction(insn, 48, 7);
403   bool cy = fieldFromInstruction(insn, 47, 1);
404   unsigned sy = fieldFromInstruction(insn, 40, 7);
405 
406   // Add $sx.
407   DecodeStatus status;
408   status = DecodeSX(MI, sx, Address, Decoder);
409   if (status != MCDisassembler::Success)
410     return status;
411 
412   // Add $disp($sz).
413   status = DecodeAS(MI, insn, Address, Decoder);
414   if (status != MCDisassembler::Success)
415     return status;
416 
417   // Add $sy.
418   if (cy && !isImmOnly) {
419     status = DecodeSX(MI, sy, Address, Decoder);
420     if (status != MCDisassembler::Success)
421       return status;
422   } else {
423     if (isUImm)
424       MI.addOperand(MCOperand::createImm(sy));
425     else
426       MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
427   }
428 
429   // Add $sd.
430   status = DecodeSX(MI, sx, Address, Decoder);
431   if (status != MCDisassembler::Success)
432     return status;
433 
434   return MCDisassembler::Success;
435 }
436 
437 static DecodeStatus DecodeTS1AMI64(MCInst &MI, uint64_t insn, uint64_t Address,
438                                    const void *Decoder) {
439   return DecodeCAS(MI, insn, Address, Decoder, false, true,
440                    DecodeI64RegisterClass);
441 }
442 
443 static DecodeStatus DecodeTS1AMI32(MCInst &MI, uint64_t insn, uint64_t Address,
444                                    const void *Decoder) {
445   return DecodeCAS(MI, insn, Address, Decoder, false, true,
446                    DecodeI32RegisterClass);
447 }
448 
449 static DecodeStatus DecodeCASI64(MCInst &MI, uint64_t insn, uint64_t Address,
450                                  const void *Decoder) {
451   return DecodeCAS(MI, insn, Address, Decoder, false, false,
452                    DecodeI64RegisterClass);
453 }
454 
455 static DecodeStatus DecodeCASI32(MCInst &MI, uint64_t insn, uint64_t Address,
456                                  const void *Decoder) {
457   return DecodeCAS(MI, insn, Address, Decoder, false, false,
458                    DecodeI32RegisterClass);
459 }
460 
461 static DecodeStatus DecodeCall(MCInst &Inst, uint64_t insn, uint64_t Address,
462                                const void *Decoder) {
463   return DecodeMem(Inst, insn, Address, Decoder, true, DecodeI64RegisterClass);
464 }
465 
466 static DecodeStatus DecodeSIMM7(MCInst &MI, uint64_t insn, uint64_t Address,
467                                 const void *Decoder) {
468   uint64_t tgt = SignExtend64<7>(insn);
469   MI.addOperand(MCOperand::createImm(tgt));
470   return MCDisassembler::Success;
471 }
472 
473 static DecodeStatus DecodeSIMM32(MCInst &MI, uint64_t insn, uint64_t Address,
474                                  const void *Decoder) {
475   uint64_t tgt = SignExtend64<32>(insn);
476   MI.addOperand(MCOperand::createImm(tgt));
477   return MCDisassembler::Success;
478 }
479 
480 static bool isIntegerBCKind(MCInst &MI) {
481 
482 #define BCm_kind(NAME)                                                         \
483   case NAME##rri:                                                              \
484   case NAME##rzi:                                                              \
485   case NAME##iri:                                                              \
486   case NAME##izi:                                                              \
487   case NAME##rri_nt:                                                           \
488   case NAME##rzi_nt:                                                           \
489   case NAME##iri_nt:                                                           \
490   case NAME##izi_nt:                                                           \
491   case NAME##rri_t:                                                            \
492   case NAME##rzi_t:                                                            \
493   case NAME##iri_t:                                                            \
494   case NAME##izi_t:
495 
496 #define BCRm_kind(NAME)                                                        \
497   case NAME##rr:                                                               \
498   case NAME##ir:                                                               \
499   case NAME##rr_nt:                                                            \
500   case NAME##ir_nt:                                                            \
501   case NAME##rr_t:                                                             \
502   case NAME##ir_t:
503 
504   {
505     using namespace llvm::VE;
506     switch (MI.getOpcode()) {
507       BCm_kind(BCFL) BCm_kind(BCFW) BCRm_kind(BRCFL)
508           BCRm_kind(BRCFW) return true;
509     }
510   }
511 #undef BCm_kind
512 
513   return false;
514 }
515 
516 // Decode CC Operand field.
517 static DecodeStatus DecodeCCOperand(MCInst &MI, uint64_t cf, uint64_t Address,
518                                     const void *Decoder) {
519   MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
520   return MCDisassembler::Success;
521 }
522 
523 // Decode RD Operand field.
524 static DecodeStatus DecodeRDOperand(MCInst &MI, uint64_t cf, uint64_t Address,
525                                     const void *Decoder) {
526   MI.addOperand(MCOperand::createImm(VEValToRD(cf)));
527   return MCDisassembler::Success;
528 }
529 
530 // Decode branch condition instruction and CCOperand field in it.
531 static DecodeStatus DecodeBranchCondition(MCInst &MI, uint64_t insn,
532                                           uint64_t Address,
533                                           const void *Decoder) {
534   unsigned cf = fieldFromInstruction(insn, 48, 4);
535   bool cy = fieldFromInstruction(insn, 47, 1);
536   unsigned sy = fieldFromInstruction(insn, 40, 7);
537 
538   // Decode cf.
539   MI.addOperand(MCOperand::createImm(VEValToCondCode(cf, isIntegerBCKind(MI))));
540 
541   // Decode sy.
542   DecodeStatus status;
543   if (cy) {
544     status = DecodeI64RegisterClass(MI, sy, Address, Decoder);
545     if (status != MCDisassembler::Success)
546       return status;
547   } else {
548     MI.addOperand(MCOperand::createImm(SignExtend32<7>(sy)));
549   }
550 
551   // Decode MEMri.
552   return DecodeAS(MI, insn, Address, Decoder);
553 }
554 
555 static DecodeStatus DecodeBranchConditionAlways(MCInst &MI, uint64_t insn,
556                                                 uint64_t Address,
557                                                 const void *Decoder) {
558   // Decode MEMri.
559   return DecodeAS(MI, insn, Address, Decoder);
560 }
561