1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SystemZTargetMachine.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "SystemZ.h" 12 #include "SystemZMachineFunctionInfo.h" 13 #include "SystemZMachineScheduler.h" 14 #include "SystemZTargetTransformInfo.h" 15 #include "TargetInfo/SystemZTargetInfo.h" 16 #include "llvm/ADT/StringRef.h" 17 #include "llvm/Analysis/TargetTransformInfo.h" 18 #include "llvm/CodeGen/Passes.h" 19 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 20 #include "llvm/CodeGen/TargetPassConfig.h" 21 #include "llvm/IR/DataLayout.h" 22 #include "llvm/MC/TargetRegistry.h" 23 #include "llvm/Support/CodeGen.h" 24 #include "llvm/Target/TargetLoweringObjectFile.h" 25 #include "llvm/Transforms/Scalar.h" 26 #include <memory> 27 #include <optional> 28 #include <string> 29 30 using namespace llvm; 31 32 // NOLINTNEXTLINE(readability-identifier-naming) 33 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { 34 // Register the target. 35 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget()); 36 auto &PR = *PassRegistry::getPassRegistry(); 37 initializeSystemZElimComparePass(PR); 38 initializeSystemZShortenInstPass(PR); 39 initializeSystemZLongBranchPass(PR); 40 initializeSystemZLDCleanupPass(PR); 41 initializeSystemZShortenInstPass(PR); 42 initializeSystemZPostRewritePass(PR); 43 initializeSystemZTDCPassPass(PR); 44 initializeSystemZDAGToDAGISelPass(PR); 45 } 46 47 static std::string computeDataLayout(const Triple &TT) { 48 std::string Ret; 49 50 // Big endian. 51 Ret += "E"; 52 53 // Data mangling. 54 Ret += DataLayout::getManglingComponent(TT); 55 56 // Make sure that global data has at least 16 bits of alignment by 57 // default, so that we can refer to it using LARL. We don't have any 58 // special requirements for stack variables though. 59 Ret += "-i1:8:16-i8:8:16"; 60 61 // 64-bit integers are naturally aligned. 62 Ret += "-i64:64"; 63 64 // 128-bit floats are aligned only to 64 bits. 65 Ret += "-f128:64"; 66 67 // The DataLayout string always holds a vector alignment of 64 bits, see 68 // comment in clang/lib/Basic/Targets/SystemZ.h. 69 Ret += "-v128:64"; 70 71 // We prefer 16 bits of aligned for all globals; see above. 72 Ret += "-a:8:16"; 73 74 // Integer registers are 32 or 64 bits. 75 Ret += "-n32:64"; 76 77 return Ret; 78 } 79 80 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 81 if (TT.isOSzOS()) 82 return std::make_unique<TargetLoweringObjectFileGOFF>(); 83 84 // Note: Some times run with -triple s390x-unknown. 85 // In this case, default to ELF unless z/OS specifically provided. 86 return std::make_unique<TargetLoweringObjectFileELF>(); 87 } 88 89 static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) { 90 // Static code is suitable for use in a dynamic executable; there is no 91 // separate DynamicNoPIC model. 92 if (!RM || *RM == Reloc::DynamicNoPIC) 93 return Reloc::Static; 94 return *RM; 95 } 96 97 // For SystemZ we define the models as follows: 98 // 99 // Small: BRASL can call any function and will use a stub if necessary. 100 // Locally-binding symbols will always be in range of LARL. 101 // 102 // Medium: BRASL can call any function and will use a stub if necessary. 103 // GOT slots and locally-defined text will always be in range 104 // of LARL, but other symbols might not be. 105 // 106 // Large: Equivalent to Medium for now. 107 // 108 // Kernel: Equivalent to Medium for now. 109 // 110 // This means that any PIC module smaller than 4GB meets the 111 // requirements of Small, so Small seems like the best default there. 112 // 113 // All symbols bind locally in a non-PIC module, so the choice is less 114 // obvious. There are two cases: 115 // 116 // - When creating an executable, PLTs and copy relocations allow 117 // us to treat external symbols as part of the executable. 118 // Any executable smaller than 4GB meets the requirements of Small, 119 // so that seems like the best default. 120 // 121 // - When creating JIT code, stubs will be in range of BRASL if the 122 // image is less than 4GB in size. GOT entries will likewise be 123 // in range of LARL. However, the JIT environment has no equivalent 124 // of copy relocs, so locally-binding data symbols might not be in 125 // the range of LARL. We need the Medium model in that case. 126 static CodeModel::Model 127 getEffectiveSystemZCodeModel(std::optional<CodeModel::Model> CM, 128 Reloc::Model RM, bool JIT) { 129 if (CM) { 130 if (*CM == CodeModel::Tiny) 131 report_fatal_error("Target does not support the tiny CodeModel", false); 132 if (*CM == CodeModel::Kernel) 133 report_fatal_error("Target does not support the kernel CodeModel", false); 134 return *CM; 135 } 136 if (JIT) 137 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 138 return CodeModel::Small; 139 } 140 141 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 142 StringRef CPU, StringRef FS, 143 const TargetOptions &Options, 144 std::optional<Reloc::Model> RM, 145 std::optional<CodeModel::Model> CM, 146 CodeGenOptLevel OL, bool JIT) 147 : LLVMTargetMachine( 148 T, computeDataLayout(TT), TT, CPU, FS, Options, 149 getEffectiveRelocModel(RM), 150 getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), 151 OL), 152 TLOF(createTLOF(getTargetTriple())) { 153 initAsmInfo(); 154 } 155 156 SystemZTargetMachine::~SystemZTargetMachine() = default; 157 158 const SystemZSubtarget * 159 SystemZTargetMachine::getSubtargetImpl(const Function &F) const { 160 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 161 Attribute TuneAttr = F.getFnAttribute("tune-cpu"); 162 Attribute FSAttr = F.getFnAttribute("target-features"); 163 164 std::string CPU = 165 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 166 std::string TuneCPU = 167 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; 168 std::string FS = 169 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 170 171 // FIXME: This is related to the code below to reset the target options, 172 // we need to know whether the soft float and backchain flags are set on the 173 // function, so we can enable them as subtarget features. 174 bool SoftFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 175 if (SoftFloat) 176 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 177 bool BackChain = F.hasFnAttribute("backchain"); 178 if (BackChain) 179 FS += FS.empty() ? "+backchain" : ",+backchain"; 180 181 auto &I = SubtargetMap[CPU + TuneCPU + FS]; 182 if (!I) { 183 // This needs to be done before we create a new subtarget since any 184 // creation will depend on the TM and the code generation flags on the 185 // function that reside in TargetOptions. 186 resetTargetOptions(F); 187 I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, TuneCPU, FS, 188 *this); 189 } 190 191 return I.get(); 192 } 193 194 namespace { 195 196 /// SystemZ Code Generator Pass Configuration Options. 197 class SystemZPassConfig : public TargetPassConfig { 198 public: 199 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM) 200 : TargetPassConfig(TM, PM) {} 201 202 SystemZTargetMachine &getSystemZTargetMachine() const { 203 return getTM<SystemZTargetMachine>(); 204 } 205 206 ScheduleDAGInstrs * 207 createPostMachineScheduler(MachineSchedContext *C) const override { 208 return new ScheduleDAGMI(C, 209 std::make_unique<SystemZPostRASchedStrategy>(C), 210 /*RemoveKillFlags=*/true); 211 } 212 213 void addIRPasses() override; 214 bool addInstSelector() override; 215 bool addILPOpts() override; 216 void addPreRegAlloc() override; 217 void addPostRewrite() override; 218 void addPostRegAlloc() override; 219 void addPreSched2() override; 220 void addPreEmitPass() override; 221 }; 222 223 } // end anonymous namespace 224 225 void SystemZPassConfig::addIRPasses() { 226 if (getOptLevel() != CodeGenOptLevel::None) { 227 addPass(createSystemZTDCPass()); 228 addPass(createLoopDataPrefetchPass()); 229 } 230 231 addPass(createAtomicExpandPass()); 232 233 TargetPassConfig::addIRPasses(); 234 } 235 236 bool SystemZPassConfig::addInstSelector() { 237 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 238 239 if (getOptLevel() != CodeGenOptLevel::None) 240 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine())); 241 242 return false; 243 } 244 245 bool SystemZPassConfig::addILPOpts() { 246 addPass(&EarlyIfConverterID); 247 return true; 248 } 249 250 void SystemZPassConfig::addPreRegAlloc() { 251 addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine())); 252 } 253 254 void SystemZPassConfig::addPostRewrite() { 255 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 256 } 257 258 void SystemZPassConfig::addPostRegAlloc() { 259 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite() 260 // is not called). 261 if (getOptLevel() == CodeGenOptLevel::None) 262 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 263 } 264 265 void SystemZPassConfig::addPreSched2() { 266 if (getOptLevel() != CodeGenOptLevel::None) 267 addPass(&IfConverterID); 268 } 269 270 void SystemZPassConfig::addPreEmitPass() { 271 // Do instruction shortening before compare elimination because some 272 // vector instructions will be shortened into opcodes that compare 273 // elimination recognizes. 274 if (getOptLevel() != CodeGenOptLevel::None) 275 addPass(createSystemZShortenInstPass(getSystemZTargetMachine())); 276 277 // We eliminate comparisons here rather than earlier because some 278 // transformations can change the set of available CC values and we 279 // generally want those transformations to have priority. This is 280 // especially true in the commonest case where the result of the comparison 281 // is used by a single in-range branch instruction, since we will then 282 // be able to fuse the compare and the branch instead. 283 // 284 // For example, two-address NILF can sometimes be converted into 285 // three-address RISBLG. NILF produces a CC value that indicates whether 286 // the low word is zero, but RISBLG does not modify CC at all. On the 287 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG. 288 // The CC value produced by NILL isn't useful for our purposes, but the 289 // value produced by RISBG can be used for any comparison with zero 290 // (not just equality). So there are some transformations that lose 291 // CC values (while still being worthwhile) and others that happen to make 292 // the CC result more useful than it was originally. 293 // 294 // Another reason is that we only want to use BRANCH ON COUNT in cases 295 // where we know that the count register is not going to be spilled. 296 // 297 // Doing it so late makes it more likely that a register will be reused 298 // between the comparison and the branch, but it isn't clear whether 299 // preventing that would be a win or not. 300 if (getOptLevel() != CodeGenOptLevel::None) 301 addPass(createSystemZElimComparePass(getSystemZTargetMachine())); 302 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 303 304 // Do final scheduling after all other optimizations, to get an 305 // optimal input for the decoder (branch relaxation must happen 306 // after block placement). 307 if (getOptLevel() != CodeGenOptLevel::None) 308 addPass(&PostMachineSchedulerID); 309 } 310 311 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 312 return new SystemZPassConfig(*this, PM); 313 } 314 315 TargetTransformInfo 316 SystemZTargetMachine::getTargetTransformInfo(const Function &F) const { 317 return TargetTransformInfo(SystemZTTIImpl(this, F)); 318 } 319 320 MachineFunctionInfo *SystemZTargetMachine::createMachineFunctionInfo( 321 BumpPtrAllocator &Allocator, const Function &F, 322 const TargetSubtargetInfo *STI) const { 323 return SystemZMachineFunctionInfo::create<SystemZMachineFunctionInfo>( 324 Allocator, F, STI); 325 } 326