1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SystemZTargetMachine.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "SystemZ.h" 12 #include "SystemZMachineScheduler.h" 13 #include "SystemZTargetTransformInfo.h" 14 #include "TargetInfo/SystemZTargetInfo.h" 15 #include "llvm/ADT/Optional.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/CodeGen/TargetPassConfig.h" 23 #include "llvm/IR/DataLayout.h" 24 #include "llvm/Support/CodeGen.h" 25 #include "llvm/Support/TargetRegistry.h" 26 #include "llvm/Target/TargetLoweringObjectFile.h" 27 #include "llvm/Transforms/Scalar.h" 28 #include <string> 29 30 using namespace llvm; 31 32 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { 33 // Register the target. 34 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget()); 35 } 36 37 // Determine whether we use the vector ABI. 38 static bool UsesVectorABI(StringRef CPU, StringRef FS) { 39 // We use the vector ABI whenever the vector facility is avaiable. 40 // This is the case by default if CPU is z13 or later, and can be 41 // overridden via "[+-]vector" feature string elements. 42 bool VectorABI = true; 43 bool SoftFloat = false; 44 if (CPU.empty() || CPU == "generic" || 45 CPU == "z10" || CPU == "z196" || CPU == "zEC12" || 46 CPU == "arch8" || CPU == "arch9" || CPU == "arch10") 47 VectorABI = false; 48 49 SmallVector<StringRef, 3> Features; 50 FS.split(Features, ',', -1, false /* KeepEmpty */); 51 for (auto &Feature : Features) { 52 if (Feature == "vector" || Feature == "+vector") 53 VectorABI = true; 54 if (Feature == "-vector") 55 VectorABI = false; 56 if (Feature == "soft-float" || Feature == "+soft-float") 57 SoftFloat = true; 58 if (Feature == "-soft-float") 59 SoftFloat = false; 60 } 61 62 return VectorABI && !SoftFloat; 63 } 64 65 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 66 StringRef FS) { 67 bool VectorABI = UsesVectorABI(CPU, FS); 68 std::string Ret; 69 70 // Big endian. 71 Ret += "E"; 72 73 // Data mangling. 74 Ret += DataLayout::getManglingComponent(TT); 75 76 // Make sure that global data has at least 16 bits of alignment by 77 // default, so that we can refer to it using LARL. We don't have any 78 // special requirements for stack variables though. 79 Ret += "-i1:8:16-i8:8:16"; 80 81 // 64-bit integers are naturally aligned. 82 Ret += "-i64:64"; 83 84 // 128-bit floats are aligned only to 64 bits. 85 Ret += "-f128:64"; 86 87 // When using the vector ABI, 128-bit vectors are also aligned to 64 bits. 88 if (VectorABI) 89 Ret += "-v128:64"; 90 91 // We prefer 16 bits of aligned for all globals; see above. 92 Ret += "-a:8:16"; 93 94 // Integer registers are 32 or 64 bits. 95 Ret += "-n32:64"; 96 97 return Ret; 98 } 99 100 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 101 // Static code is suitable for use in a dynamic executable; there is no 102 // separate DynamicNoPIC model. 103 if (!RM.hasValue() || *RM == Reloc::DynamicNoPIC) 104 return Reloc::Static; 105 return *RM; 106 } 107 108 // For SystemZ we define the models as follows: 109 // 110 // Small: BRASL can call any function and will use a stub if necessary. 111 // Locally-binding symbols will always be in range of LARL. 112 // 113 // Medium: BRASL can call any function and will use a stub if necessary. 114 // GOT slots and locally-defined text will always be in range 115 // of LARL, but other symbols might not be. 116 // 117 // Large: Equivalent to Medium for now. 118 // 119 // Kernel: Equivalent to Medium for now. 120 // 121 // This means that any PIC module smaller than 4GB meets the 122 // requirements of Small, so Small seems like the best default there. 123 // 124 // All symbols bind locally in a non-PIC module, so the choice is less 125 // obvious. There are two cases: 126 // 127 // - When creating an executable, PLTs and copy relocations allow 128 // us to treat external symbols as part of the executable. 129 // Any executable smaller than 4GB meets the requirements of Small, 130 // so that seems like the best default. 131 // 132 // - When creating JIT code, stubs will be in range of BRASL if the 133 // image is less than 4GB in size. GOT entries will likewise be 134 // in range of LARL. However, the JIT environment has no equivalent 135 // of copy relocs, so locally-binding data symbols might not be in 136 // the range of LARL. We need the Medium model in that case. 137 static CodeModel::Model 138 getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, 139 bool JIT) { 140 if (CM) { 141 if (*CM == CodeModel::Tiny) 142 report_fatal_error("Target does not support the tiny CodeModel", false); 143 if (*CM == CodeModel::Kernel) 144 report_fatal_error("Target does not support the kernel CodeModel", false); 145 return *CM; 146 } 147 if (JIT) 148 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 149 return CodeModel::Small; 150 } 151 152 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 153 StringRef CPU, StringRef FS, 154 const TargetOptions &Options, 155 Optional<Reloc::Model> RM, 156 Optional<CodeModel::Model> CM, 157 CodeGenOpt::Level OL, bool JIT) 158 : LLVMTargetMachine( 159 T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, 160 getEffectiveRelocModel(RM), 161 getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), 162 OL), 163 TLOF(std::make_unique<TargetLoweringObjectFileELF>()) { 164 initAsmInfo(); 165 } 166 167 SystemZTargetMachine::~SystemZTargetMachine() = default; 168 169 const SystemZSubtarget * 170 SystemZTargetMachine::getSubtargetImpl(const Function &F) const { 171 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 172 Attribute FSAttr = F.getFnAttribute("target-features"); 173 174 std::string CPU = 175 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 176 std::string FS = 177 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 178 179 // FIXME: This is related to the code below to reset the target options, 180 // we need to know whether or not the soft float flag is set on the 181 // function, so we can enable it as a subtarget feature. 182 bool softFloat = 183 F.hasFnAttribute("use-soft-float") && 184 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 185 186 if (softFloat) 187 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 188 189 auto &I = SubtargetMap[CPU + FS]; 190 if (!I) { 191 // This needs to be done before we create a new subtarget since any 192 // creation will depend on the TM and the code generation flags on the 193 // function that reside in TargetOptions. 194 resetTargetOptions(F); 195 I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, FS, *this); 196 } 197 198 return I.get(); 199 } 200 201 namespace { 202 203 /// SystemZ Code Generator Pass Configuration Options. 204 class SystemZPassConfig : public TargetPassConfig { 205 public: 206 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM) 207 : TargetPassConfig(TM, PM) {} 208 209 SystemZTargetMachine &getSystemZTargetMachine() const { 210 return getTM<SystemZTargetMachine>(); 211 } 212 213 ScheduleDAGInstrs * 214 createPostMachineScheduler(MachineSchedContext *C) const override { 215 return new ScheduleDAGMI(C, 216 std::make_unique<SystemZPostRASchedStrategy>(C), 217 /*RemoveKillFlags=*/true); 218 } 219 220 void addIRPasses() override; 221 bool addInstSelector() override; 222 bool addILPOpts() override; 223 void addPreRegAlloc() override; 224 void addPostRewrite() override; 225 void addPostRegAlloc() override; 226 void addPreSched2() override; 227 void addPreEmitPass() override; 228 }; 229 230 } // end anonymous namespace 231 232 void SystemZPassConfig::addIRPasses() { 233 if (getOptLevel() != CodeGenOpt::None) { 234 addPass(createSystemZTDCPass()); 235 addPass(createLoopDataPrefetchPass()); 236 } 237 238 TargetPassConfig::addIRPasses(); 239 } 240 241 bool SystemZPassConfig::addInstSelector() { 242 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 243 244 if (getOptLevel() != CodeGenOpt::None) 245 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine())); 246 247 return false; 248 } 249 250 bool SystemZPassConfig::addILPOpts() { 251 addPass(&EarlyIfConverterID); 252 return true; 253 } 254 255 void SystemZPassConfig::addPreRegAlloc() { 256 addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine())); 257 } 258 259 void SystemZPassConfig::addPostRewrite() { 260 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 261 } 262 263 void SystemZPassConfig::addPostRegAlloc() { 264 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite() 265 // is not called). 266 if (getOptLevel() == CodeGenOpt::None) 267 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 268 } 269 270 void SystemZPassConfig::addPreSched2() { 271 if (getOptLevel() != CodeGenOpt::None) 272 addPass(&IfConverterID); 273 } 274 275 void SystemZPassConfig::addPreEmitPass() { 276 // Do instruction shortening before compare elimination because some 277 // vector instructions will be shortened into opcodes that compare 278 // elimination recognizes. 279 if (getOptLevel() != CodeGenOpt::None) 280 addPass(createSystemZShortenInstPass(getSystemZTargetMachine()), false); 281 282 // We eliminate comparisons here rather than earlier because some 283 // transformations can change the set of available CC values and we 284 // generally want those transformations to have priority. This is 285 // especially true in the commonest case where the result of the comparison 286 // is used by a single in-range branch instruction, since we will then 287 // be able to fuse the compare and the branch instead. 288 // 289 // For example, two-address NILF can sometimes be converted into 290 // three-address RISBLG. NILF produces a CC value that indicates whether 291 // the low word is zero, but RISBLG does not modify CC at all. On the 292 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG. 293 // The CC value produced by NILL isn't useful for our purposes, but the 294 // value produced by RISBG can be used for any comparison with zero 295 // (not just equality). So there are some transformations that lose 296 // CC values (while still being worthwhile) and others that happen to make 297 // the CC result more useful than it was originally. 298 // 299 // Another reason is that we only want to use BRANCH ON COUNT in cases 300 // where we know that the count register is not going to be spilled. 301 // 302 // Doing it so late makes it more likely that a register will be reused 303 // between the comparison and the branch, but it isn't clear whether 304 // preventing that would be a win or not. 305 if (getOptLevel() != CodeGenOpt::None) 306 addPass(createSystemZElimComparePass(getSystemZTargetMachine()), false); 307 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 308 309 // Do final scheduling after all other optimizations, to get an 310 // optimal input for the decoder (branch relaxation must happen 311 // after block placement). 312 if (getOptLevel() != CodeGenOpt::None) 313 addPass(&PostMachineSchedulerID); 314 } 315 316 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 317 return new SystemZPassConfig(*this, PM); 318 } 319 320 TargetTransformInfo 321 SystemZTargetMachine::getTargetTransformInfo(const Function &F) { 322 return TargetTransformInfo(SystemZTTIImpl(this, F)); 323 } 324