1 //===-- SystemZTargetMachine.cpp - Define TargetMachine for SystemZ -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SystemZTargetMachine.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "SystemZ.h" 12 #include "SystemZMachineScheduler.h" 13 #include "SystemZTargetTransformInfo.h" 14 #include "TargetInfo/SystemZTargetInfo.h" 15 #include "llvm/ADT/Optional.h" 16 #include "llvm/ADT/STLExtras.h" 17 #include "llvm/ADT/SmallVector.h" 18 #include "llvm/ADT/StringRef.h" 19 #include "llvm/Analysis/TargetTransformInfo.h" 20 #include "llvm/CodeGen/Passes.h" 21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 22 #include "llvm/CodeGen/TargetPassConfig.h" 23 #include "llvm/IR/DataLayout.h" 24 #include "llvm/MC/TargetRegistry.h" 25 #include "llvm/Support/CodeGen.h" 26 #include "llvm/Target/TargetLoweringObjectFile.h" 27 #include "llvm/Transforms/Scalar.h" 28 #include <string> 29 30 using namespace llvm; 31 32 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZTarget() { 33 // Register the target. 34 RegisterTargetMachine<SystemZTargetMachine> X(getTheSystemZTarget()); 35 auto &PR = *PassRegistry::getPassRegistry(); 36 initializeSystemZElimComparePass(PR); 37 initializeSystemZShortenInstPass(PR); 38 initializeSystemZLongBranchPass(PR); 39 initializeSystemZLDCleanupPass(PR); 40 initializeSystemZShortenInstPass(PR); 41 initializeSystemZPostRewritePass(PR); 42 initializeSystemZTDCPassPass(PR); 43 } 44 45 // Determine whether we use the vector ABI. 46 static bool UsesVectorABI(StringRef CPU, StringRef FS) { 47 // We use the vector ABI whenever the vector facility is avaiable. 48 // This is the case by default if CPU is z13 or later, and can be 49 // overridden via "[+-]vector" feature string elements. 50 bool VectorABI = true; 51 bool SoftFloat = false; 52 if (CPU.empty() || CPU == "generic" || 53 CPU == "z10" || CPU == "z196" || CPU == "zEC12" || 54 CPU == "arch8" || CPU == "arch9" || CPU == "arch10") 55 VectorABI = false; 56 57 SmallVector<StringRef, 3> Features; 58 FS.split(Features, ',', -1, false /* KeepEmpty */); 59 for (auto &Feature : Features) { 60 if (Feature == "vector" || Feature == "+vector") 61 VectorABI = true; 62 if (Feature == "-vector") 63 VectorABI = false; 64 if (Feature == "soft-float" || Feature == "+soft-float") 65 SoftFloat = true; 66 if (Feature == "-soft-float") 67 SoftFloat = false; 68 } 69 70 return VectorABI && !SoftFloat; 71 } 72 73 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 74 StringRef FS) { 75 bool VectorABI = UsesVectorABI(CPU, FS); 76 std::string Ret; 77 78 // Big endian. 79 Ret += "E"; 80 81 // Data mangling. 82 Ret += DataLayout::getManglingComponent(TT); 83 84 // Make sure that global data has at least 16 bits of alignment by 85 // default, so that we can refer to it using LARL. We don't have any 86 // special requirements for stack variables though. 87 Ret += "-i1:8:16-i8:8:16"; 88 89 // 64-bit integers are naturally aligned. 90 Ret += "-i64:64"; 91 92 // 128-bit floats are aligned only to 64 bits. 93 Ret += "-f128:64"; 94 95 // When using the vector ABI on Linux, 128-bit vectors are also aligned to 64 96 // bits. On z/OS, vector types are always aligned to 64 bits. 97 if (VectorABI || TT.isOSzOS()) 98 Ret += "-v128:64"; 99 100 // We prefer 16 bits of aligned for all globals; see above. 101 Ret += "-a:8:16"; 102 103 // Integer registers are 32 or 64 bits. 104 Ret += "-n32:64"; 105 106 return Ret; 107 } 108 109 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) { 110 if (TT.isOSzOS()) 111 return std::make_unique<TargetLoweringObjectFileGOFF>(); 112 113 // Note: Some times run with -triple s390x-unknown. 114 // In this case, default to ELF unless z/OS specifically provided. 115 return std::make_unique<TargetLoweringObjectFileELF>(); 116 } 117 118 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) { 119 // Static code is suitable for use in a dynamic executable; there is no 120 // separate DynamicNoPIC model. 121 if (!RM || *RM == Reloc::DynamicNoPIC) 122 return Reloc::Static; 123 return *RM; 124 } 125 126 // For SystemZ we define the models as follows: 127 // 128 // Small: BRASL can call any function and will use a stub if necessary. 129 // Locally-binding symbols will always be in range of LARL. 130 // 131 // Medium: BRASL can call any function and will use a stub if necessary. 132 // GOT slots and locally-defined text will always be in range 133 // of LARL, but other symbols might not be. 134 // 135 // Large: Equivalent to Medium for now. 136 // 137 // Kernel: Equivalent to Medium for now. 138 // 139 // This means that any PIC module smaller than 4GB meets the 140 // requirements of Small, so Small seems like the best default there. 141 // 142 // All symbols bind locally in a non-PIC module, so the choice is less 143 // obvious. There are two cases: 144 // 145 // - When creating an executable, PLTs and copy relocations allow 146 // us to treat external symbols as part of the executable. 147 // Any executable smaller than 4GB meets the requirements of Small, 148 // so that seems like the best default. 149 // 150 // - When creating JIT code, stubs will be in range of BRASL if the 151 // image is less than 4GB in size. GOT entries will likewise be 152 // in range of LARL. However, the JIT environment has no equivalent 153 // of copy relocs, so locally-binding data symbols might not be in 154 // the range of LARL. We need the Medium model in that case. 155 static CodeModel::Model 156 getEffectiveSystemZCodeModel(Optional<CodeModel::Model> CM, Reloc::Model RM, 157 bool JIT) { 158 if (CM) { 159 if (*CM == CodeModel::Tiny) 160 report_fatal_error("Target does not support the tiny CodeModel", false); 161 if (*CM == CodeModel::Kernel) 162 report_fatal_error("Target does not support the kernel CodeModel", false); 163 return *CM; 164 } 165 if (JIT) 166 return RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 167 return CodeModel::Small; 168 } 169 170 SystemZTargetMachine::SystemZTargetMachine(const Target &T, const Triple &TT, 171 StringRef CPU, StringRef FS, 172 const TargetOptions &Options, 173 Optional<Reloc::Model> RM, 174 Optional<CodeModel::Model> CM, 175 CodeGenOpt::Level OL, bool JIT) 176 : LLVMTargetMachine( 177 T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, 178 getEffectiveRelocModel(RM), 179 getEffectiveSystemZCodeModel(CM, getEffectiveRelocModel(RM), JIT), 180 OL), 181 TLOF(createTLOF(getTargetTriple())) { 182 initAsmInfo(); 183 } 184 185 SystemZTargetMachine::~SystemZTargetMachine() = default; 186 187 const SystemZSubtarget * 188 SystemZTargetMachine::getSubtargetImpl(const Function &F) const { 189 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 190 Attribute TuneAttr = F.getFnAttribute("tune-cpu"); 191 Attribute FSAttr = F.getFnAttribute("target-features"); 192 193 std::string CPU = 194 CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; 195 std::string TuneCPU = 196 TuneAttr.isValid() ? TuneAttr.getValueAsString().str() : CPU; 197 std::string FS = 198 FSAttr.isValid() ? FSAttr.getValueAsString().str() : TargetFS; 199 200 // FIXME: This is related to the code below to reset the target options, 201 // we need to know whether or not the soft float flag is set on the 202 // function, so we can enable it as a subtarget feature. 203 bool softFloat = F.getFnAttribute("use-soft-float").getValueAsBool(); 204 205 if (softFloat) 206 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 207 208 auto &I = SubtargetMap[CPU + TuneCPU + FS]; 209 if (!I) { 210 // This needs to be done before we create a new subtarget since any 211 // creation will depend on the TM and the code generation flags on the 212 // function that reside in TargetOptions. 213 resetTargetOptions(F); 214 I = std::make_unique<SystemZSubtarget>(TargetTriple, CPU, TuneCPU, FS, 215 *this); 216 } 217 218 return I.get(); 219 } 220 221 namespace { 222 223 /// SystemZ Code Generator Pass Configuration Options. 224 class SystemZPassConfig : public TargetPassConfig { 225 public: 226 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM) 227 : TargetPassConfig(TM, PM) {} 228 229 SystemZTargetMachine &getSystemZTargetMachine() const { 230 return getTM<SystemZTargetMachine>(); 231 } 232 233 ScheduleDAGInstrs * 234 createPostMachineScheduler(MachineSchedContext *C) const override { 235 return new ScheduleDAGMI(C, 236 std::make_unique<SystemZPostRASchedStrategy>(C), 237 /*RemoveKillFlags=*/true); 238 } 239 240 void addIRPasses() override; 241 bool addInstSelector() override; 242 bool addILPOpts() override; 243 void addPreRegAlloc() override; 244 void addPostRewrite() override; 245 void addPostRegAlloc() override; 246 void addPreSched2() override; 247 void addPreEmitPass() override; 248 }; 249 250 } // end anonymous namespace 251 252 void SystemZPassConfig::addIRPasses() { 253 if (getOptLevel() != CodeGenOpt::None) { 254 addPass(createSystemZTDCPass()); 255 addPass(createLoopDataPrefetchPass()); 256 } 257 258 TargetPassConfig::addIRPasses(); 259 } 260 261 bool SystemZPassConfig::addInstSelector() { 262 addPass(createSystemZISelDag(getSystemZTargetMachine(), getOptLevel())); 263 264 if (getOptLevel() != CodeGenOpt::None) 265 addPass(createSystemZLDCleanupPass(getSystemZTargetMachine())); 266 267 return false; 268 } 269 270 bool SystemZPassConfig::addILPOpts() { 271 addPass(&EarlyIfConverterID); 272 return true; 273 } 274 275 void SystemZPassConfig::addPreRegAlloc() { 276 addPass(createSystemZCopyPhysRegsPass(getSystemZTargetMachine())); 277 } 278 279 void SystemZPassConfig::addPostRewrite() { 280 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 281 } 282 283 void SystemZPassConfig::addPostRegAlloc() { 284 // PostRewrite needs to be run at -O0 also (in which case addPostRewrite() 285 // is not called). 286 if (getOptLevel() == CodeGenOpt::None) 287 addPass(createSystemZPostRewritePass(getSystemZTargetMachine())); 288 } 289 290 void SystemZPassConfig::addPreSched2() { 291 if (getOptLevel() != CodeGenOpt::None) 292 addPass(&IfConverterID); 293 } 294 295 void SystemZPassConfig::addPreEmitPass() { 296 // Do instruction shortening before compare elimination because some 297 // vector instructions will be shortened into opcodes that compare 298 // elimination recognizes. 299 if (getOptLevel() != CodeGenOpt::None) 300 addPass(createSystemZShortenInstPass(getSystemZTargetMachine())); 301 302 // We eliminate comparisons here rather than earlier because some 303 // transformations can change the set of available CC values and we 304 // generally want those transformations to have priority. This is 305 // especially true in the commonest case where the result of the comparison 306 // is used by a single in-range branch instruction, since we will then 307 // be able to fuse the compare and the branch instead. 308 // 309 // For example, two-address NILF can sometimes be converted into 310 // three-address RISBLG. NILF produces a CC value that indicates whether 311 // the low word is zero, but RISBLG does not modify CC at all. On the 312 // other hand, 64-bit ANDs like NILL can sometimes be converted to RISBG. 313 // The CC value produced by NILL isn't useful for our purposes, but the 314 // value produced by RISBG can be used for any comparison with zero 315 // (not just equality). So there are some transformations that lose 316 // CC values (while still being worthwhile) and others that happen to make 317 // the CC result more useful than it was originally. 318 // 319 // Another reason is that we only want to use BRANCH ON COUNT in cases 320 // where we know that the count register is not going to be spilled. 321 // 322 // Doing it so late makes it more likely that a register will be reused 323 // between the comparison and the branch, but it isn't clear whether 324 // preventing that would be a win or not. 325 if (getOptLevel() != CodeGenOpt::None) 326 addPass(createSystemZElimComparePass(getSystemZTargetMachine())); 327 addPass(createSystemZLongBranchPass(getSystemZTargetMachine())); 328 329 // Do final scheduling after all other optimizations, to get an 330 // optimal input for the decoder (branch relaxation must happen 331 // after block placement). 332 if (getOptLevel() != CodeGenOpt::None) 333 addPass(&PostMachineSchedulerID); 334 } 335 336 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) { 337 return new SystemZPassConfig(*this, PM); 338 } 339 340 TargetTransformInfo 341 SystemZTargetMachine::getTargetTransformInfo(const Function &F) const { 342 return TargetTransformInfo(SystemZTTIImpl(this, F)); 343 } 344