xref: /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp (revision fe6060f10f634930ff71b7c50291ddc610da2475)
10b57cec5SDimitry Andric //===-- SystemZRegisterInfo.cpp - SystemZ register information ------------===//
20b57cec5SDimitry Andric //
30b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
40b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information.
50b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
60b57cec5SDimitry Andric //
70b57cec5SDimitry Andric //===----------------------------------------------------------------------===//
80b57cec5SDimitry Andric 
90b57cec5SDimitry Andric #include "SystemZRegisterInfo.h"
100b57cec5SDimitry Andric #include "SystemZInstrInfo.h"
110b57cec5SDimitry Andric #include "SystemZSubtarget.h"
120b57cec5SDimitry Andric #include "llvm/ADT/SmallSet.h"
13*fe6060f1SDimitry Andric #include "llvm/CodeGen/LiveIntervals.h"
140b57cec5SDimitry Andric #include "llvm/CodeGen/MachineInstrBuilder.h"
150b57cec5SDimitry Andric #include "llvm/CodeGen/MachineRegisterInfo.h"
160b57cec5SDimitry Andric #include "llvm/CodeGen/TargetFrameLowering.h"
170b57cec5SDimitry Andric #include "llvm/CodeGen/VirtRegMap.h"
18*fe6060f1SDimitry Andric #include "llvm/IR/DebugInfoMetadata.h"
190b57cec5SDimitry Andric 
200b57cec5SDimitry Andric using namespace llvm;
210b57cec5SDimitry Andric 
220b57cec5SDimitry Andric #define GET_REGINFO_TARGET_DESC
230b57cec5SDimitry Andric #include "SystemZGenRegisterInfo.inc"
240b57cec5SDimitry Andric 
250b57cec5SDimitry Andric // Given that MO is a GRX32 operand, return either GR32 or GRH32 if MO
260b57cec5SDimitry Andric // somehow belongs in it. Otherwise, return GRX32.
270b57cec5SDimitry Andric static const TargetRegisterClass *getRC32(MachineOperand &MO,
280b57cec5SDimitry Andric                                           const VirtRegMap *VRM,
290b57cec5SDimitry Andric                                           const MachineRegisterInfo *MRI) {
300b57cec5SDimitry Andric   const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
310b57cec5SDimitry Andric 
320b57cec5SDimitry Andric   if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) ||
330b57cec5SDimitry Andric       MO.getSubReg() == SystemZ::subreg_l32 ||
340b57cec5SDimitry Andric       MO.getSubReg() == SystemZ::subreg_hl32)
350b57cec5SDimitry Andric     return &SystemZ::GR32BitRegClass;
360b57cec5SDimitry Andric   if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) ||
370b57cec5SDimitry Andric       MO.getSubReg() == SystemZ::subreg_h32 ||
380b57cec5SDimitry Andric       MO.getSubReg() == SystemZ::subreg_hh32)
390b57cec5SDimitry Andric     return &SystemZ::GRH32BitRegClass;
400b57cec5SDimitry Andric 
410b57cec5SDimitry Andric   if (VRM && VRM->hasPhys(MO.getReg())) {
428bcb0991SDimitry Andric     Register PhysReg = VRM->getPhys(MO.getReg());
430b57cec5SDimitry Andric     if (SystemZ::GR32BitRegClass.contains(PhysReg))
440b57cec5SDimitry Andric       return &SystemZ::GR32BitRegClass;
450b57cec5SDimitry Andric     assert (SystemZ::GRH32BitRegClass.contains(PhysReg) &&
460b57cec5SDimitry Andric             "Phys reg not in GR32 or GRH32?");
470b57cec5SDimitry Andric     return &SystemZ::GRH32BitRegClass;
480b57cec5SDimitry Andric   }
490b57cec5SDimitry Andric 
500b57cec5SDimitry Andric   assert (RC == &SystemZ::GRX32BitRegClass);
510b57cec5SDimitry Andric   return RC;
520b57cec5SDimitry Andric }
530b57cec5SDimitry Andric 
540b57cec5SDimitry Andric // Pass the registers of RC as hints while making sure that if any of these
550b57cec5SDimitry Andric // registers are copy hints (and therefore already in Hints), hint them
560b57cec5SDimitry Andric // first.
570b57cec5SDimitry Andric static void addHints(ArrayRef<MCPhysReg> Order,
580b57cec5SDimitry Andric                      SmallVectorImpl<MCPhysReg> &Hints,
590b57cec5SDimitry Andric                      const TargetRegisterClass *RC,
600b57cec5SDimitry Andric                      const MachineRegisterInfo *MRI) {
610b57cec5SDimitry Andric   SmallSet<unsigned, 4> CopyHints;
620b57cec5SDimitry Andric   CopyHints.insert(Hints.begin(), Hints.end());
630b57cec5SDimitry Andric   Hints.clear();
640b57cec5SDimitry Andric   for (MCPhysReg Reg : Order)
650b57cec5SDimitry Andric     if (CopyHints.count(Reg) &&
660b57cec5SDimitry Andric         RC->contains(Reg) && !MRI->isReserved(Reg))
670b57cec5SDimitry Andric       Hints.push_back(Reg);
680b57cec5SDimitry Andric   for (MCPhysReg Reg : Order)
690b57cec5SDimitry Andric     if (!CopyHints.count(Reg) &&
700b57cec5SDimitry Andric         RC->contains(Reg) && !MRI->isReserved(Reg))
710b57cec5SDimitry Andric       Hints.push_back(Reg);
720b57cec5SDimitry Andric }
730b57cec5SDimitry Andric 
745ffd83dbSDimitry Andric bool SystemZRegisterInfo::getRegAllocationHints(
755ffd83dbSDimitry Andric     Register VirtReg, ArrayRef<MCPhysReg> Order,
765ffd83dbSDimitry Andric     SmallVectorImpl<MCPhysReg> &Hints, const MachineFunction &MF,
775ffd83dbSDimitry Andric     const VirtRegMap *VRM, const LiveRegMatrix *Matrix) const {
780b57cec5SDimitry Andric   const MachineRegisterInfo *MRI = &MF.getRegInfo();
790b57cec5SDimitry Andric   const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
800b57cec5SDimitry Andric   const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
810b57cec5SDimitry Andric 
820b57cec5SDimitry Andric   bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
830b57cec5SDimitry Andric       VirtReg, Order, Hints, MF, VRM, Matrix);
840b57cec5SDimitry Andric 
85480093f4SDimitry Andric   if (VRM != nullptr) {
86480093f4SDimitry Andric     // Add any two address hints after any copy hints.
87480093f4SDimitry Andric     SmallSet<unsigned, 4> TwoAddrHints;
88480093f4SDimitry Andric     for (auto &Use : MRI->reg_nodbg_instructions(VirtReg))
89480093f4SDimitry Andric       if (SystemZ::getTwoOperandOpcode(Use.getOpcode()) != -1) {
90480093f4SDimitry Andric         const MachineOperand *VRRegMO = nullptr;
91480093f4SDimitry Andric         const MachineOperand *OtherMO = nullptr;
92480093f4SDimitry Andric         const MachineOperand *CommuMO = nullptr;
93480093f4SDimitry Andric         if (VirtReg == Use.getOperand(0).getReg()) {
94480093f4SDimitry Andric           VRRegMO = &Use.getOperand(0);
95480093f4SDimitry Andric           OtherMO = &Use.getOperand(1);
96480093f4SDimitry Andric           if (Use.isCommutable())
97480093f4SDimitry Andric             CommuMO = &Use.getOperand(2);
98480093f4SDimitry Andric         } else if (VirtReg == Use.getOperand(1).getReg()) {
99480093f4SDimitry Andric           VRRegMO = &Use.getOperand(1);
100480093f4SDimitry Andric           OtherMO = &Use.getOperand(0);
101480093f4SDimitry Andric         } else if (VirtReg == Use.getOperand(2).getReg() &&
102480093f4SDimitry Andric                    Use.isCommutable()) {
103480093f4SDimitry Andric           VRRegMO = &Use.getOperand(2);
104480093f4SDimitry Andric           OtherMO = &Use.getOperand(0);
105480093f4SDimitry Andric         } else
106480093f4SDimitry Andric           continue;
107480093f4SDimitry Andric 
108480093f4SDimitry Andric         auto tryAddHint = [&](const MachineOperand *MO) -> void {
109480093f4SDimitry Andric           Register Reg = MO->getReg();
110e8d8bef9SDimitry Andric           Register PhysReg = Register::isPhysicalRegister(Reg)
111e8d8bef9SDimitry Andric                                  ? Reg
112e8d8bef9SDimitry Andric                                  : Register(VRM->getPhys(Reg));
113480093f4SDimitry Andric           if (PhysReg) {
114480093f4SDimitry Andric             if (MO->getSubReg())
115480093f4SDimitry Andric               PhysReg = getSubReg(PhysReg, MO->getSubReg());
116480093f4SDimitry Andric             if (VRRegMO->getSubReg())
117480093f4SDimitry Andric               PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(),
118480093f4SDimitry Andric                                             MRI->getRegClass(VirtReg));
119480093f4SDimitry Andric             if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
120480093f4SDimitry Andric               TwoAddrHints.insert(PhysReg);
121480093f4SDimitry Andric           }
122480093f4SDimitry Andric         };
123480093f4SDimitry Andric         tryAddHint(OtherMO);
124480093f4SDimitry Andric         if (CommuMO)
125480093f4SDimitry Andric           tryAddHint(CommuMO);
126480093f4SDimitry Andric       }
127480093f4SDimitry Andric     for (MCPhysReg OrderReg : Order)
128480093f4SDimitry Andric       if (TwoAddrHints.count(OrderReg))
129480093f4SDimitry Andric         Hints.push_back(OrderReg);
130480093f4SDimitry Andric   }
131480093f4SDimitry Andric 
1320b57cec5SDimitry Andric   if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
1335ffd83dbSDimitry Andric     SmallVector<Register, 8> Worklist;
1345ffd83dbSDimitry Andric     SmallSet<Register, 4> DoneRegs;
1350b57cec5SDimitry Andric     Worklist.push_back(VirtReg);
1360b57cec5SDimitry Andric     while (Worklist.size()) {
1375ffd83dbSDimitry Andric       Register Reg = Worklist.pop_back_val();
1380b57cec5SDimitry Andric       if (!DoneRegs.insert(Reg).second)
1390b57cec5SDimitry Andric         continue;
1400b57cec5SDimitry Andric 
1410b57cec5SDimitry Andric       for (auto &Use : MRI->reg_instructions(Reg)) {
1420b57cec5SDimitry Andric         // For LOCRMux, see if the other operand is already a high or low
1430b57cec5SDimitry Andric         // register, and in that case give the corresponding hints for
1440b57cec5SDimitry Andric         // VirtReg. LOCR instructions need both operands in either high or
1450b57cec5SDimitry Andric         // low parts. Same handling for SELRMux.
1460b57cec5SDimitry Andric         if (Use.getOpcode() == SystemZ::LOCRMux ||
1470b57cec5SDimitry Andric             Use.getOpcode() == SystemZ::SELRMux) {
1480b57cec5SDimitry Andric           MachineOperand &TrueMO = Use.getOperand(1);
1490b57cec5SDimitry Andric           MachineOperand &FalseMO = Use.getOperand(2);
1500b57cec5SDimitry Andric           const TargetRegisterClass *RC =
1510b57cec5SDimitry Andric             TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
1520b57cec5SDimitry Andric                                    getRC32(TrueMO, VRM, MRI));
1530b57cec5SDimitry Andric           if (Use.getOpcode() == SystemZ::SELRMux)
1540b57cec5SDimitry Andric             RC = TRI->getCommonSubClass(RC,
1550b57cec5SDimitry Andric                                         getRC32(Use.getOperand(0), VRM, MRI));
1560b57cec5SDimitry Andric           if (RC && RC != &SystemZ::GRX32BitRegClass) {
1570b57cec5SDimitry Andric             addHints(Order, Hints, RC, MRI);
1580b57cec5SDimitry Andric             // Return true to make these hints the only regs available to
1590b57cec5SDimitry Andric             // RA. This may mean extra spilling but since the alternative is
1600b57cec5SDimitry Andric             // a jump sequence expansion of the LOCRMux, it is preferred.
1610b57cec5SDimitry Andric             return true;
1620b57cec5SDimitry Andric           }
1630b57cec5SDimitry Andric 
1640b57cec5SDimitry Andric           // Add the other operand of the LOCRMux to the worklist.
1658bcb0991SDimitry Andric           Register OtherReg =
1660b57cec5SDimitry Andric               (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
1670b57cec5SDimitry Andric           if (MRI->getRegClass(OtherReg) == &SystemZ::GRX32BitRegClass)
1680b57cec5SDimitry Andric             Worklist.push_back(OtherReg);
1690b57cec5SDimitry Andric         } // end LOCRMux
1700b57cec5SDimitry Andric         else if (Use.getOpcode() == SystemZ::CHIMux ||
1710b57cec5SDimitry Andric                  Use.getOpcode() == SystemZ::CFIMux) {
1720b57cec5SDimitry Andric           if (Use.getOperand(1).getImm() == 0) {
1730b57cec5SDimitry Andric             bool OnlyLMuxes = true;
1740b57cec5SDimitry Andric             for (MachineInstr &DefMI : MRI->def_instructions(VirtReg))
1750b57cec5SDimitry Andric               if (DefMI.getOpcode() != SystemZ::LMux)
1760b57cec5SDimitry Andric                 OnlyLMuxes = false;
1770b57cec5SDimitry Andric             if (OnlyLMuxes) {
1780b57cec5SDimitry Andric               addHints(Order, Hints, &SystemZ::GR32BitRegClass, MRI);
1790b57cec5SDimitry Andric               // Return false to make these hints preferred but not obligatory.
1800b57cec5SDimitry Andric               return false;
1810b57cec5SDimitry Andric             }
1820b57cec5SDimitry Andric           }
1830b57cec5SDimitry Andric         } // end CHIMux / CFIMux
1840b57cec5SDimitry Andric       }
1850b57cec5SDimitry Andric     }
1860b57cec5SDimitry Andric   }
1870b57cec5SDimitry Andric 
1880b57cec5SDimitry Andric   return BaseImplRetVal;
1890b57cec5SDimitry Andric }
1900b57cec5SDimitry Andric 
1910b57cec5SDimitry Andric const MCPhysReg *
192*fe6060f1SDimitry Andric SystemZXPLINK64Registers::getCalleeSavedRegs(const MachineFunction *MF) const {
193*fe6060f1SDimitry Andric   return CSR_SystemZ_XPLINK64_SaveList;
194*fe6060f1SDimitry Andric }
195*fe6060f1SDimitry Andric 
196*fe6060f1SDimitry Andric const MCPhysReg *
197*fe6060f1SDimitry Andric SystemZELFRegisters::getCalleeSavedRegs(const MachineFunction *MF) const {
1980b57cec5SDimitry Andric   const SystemZSubtarget &Subtarget = MF->getSubtarget<SystemZSubtarget>();
199480093f4SDimitry Andric   if (MF->getFunction().getCallingConv() == CallingConv::GHC)
200480093f4SDimitry Andric     return CSR_SystemZ_NoRegs_SaveList;
2010b57cec5SDimitry Andric   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
2020b57cec5SDimitry Andric     return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_SaveList
2030b57cec5SDimitry Andric                                 : CSR_SystemZ_AllRegs_SaveList;
2040b57cec5SDimitry Andric   if (MF->getSubtarget().getTargetLowering()->supportSwiftError() &&
2050b57cec5SDimitry Andric       MF->getFunction().getAttributes().hasAttrSomewhere(
2060b57cec5SDimitry Andric           Attribute::SwiftError))
2070b57cec5SDimitry Andric     return CSR_SystemZ_SwiftError_SaveList;
208*fe6060f1SDimitry Andric   return CSR_SystemZ_ELF_SaveList;
2090b57cec5SDimitry Andric }
2100b57cec5SDimitry Andric 
2110b57cec5SDimitry Andric const uint32_t *
212*fe6060f1SDimitry Andric SystemZXPLINK64Registers::getCallPreservedMask(const MachineFunction &MF,
213*fe6060f1SDimitry Andric                                                CallingConv::ID CC) const {
214*fe6060f1SDimitry Andric   return CSR_SystemZ_XPLINK64_RegMask;
215*fe6060f1SDimitry Andric }
216*fe6060f1SDimitry Andric 
217*fe6060f1SDimitry Andric const uint32_t *
218*fe6060f1SDimitry Andric SystemZELFRegisters::getCallPreservedMask(const MachineFunction &MF,
2190b57cec5SDimitry Andric                                           CallingConv::ID CC) const {
2200b57cec5SDimitry Andric   const SystemZSubtarget &Subtarget = MF.getSubtarget<SystemZSubtarget>();
221480093f4SDimitry Andric   if (CC == CallingConv::GHC)
222480093f4SDimitry Andric     return CSR_SystemZ_NoRegs_RegMask;
2230b57cec5SDimitry Andric   if (CC == CallingConv::AnyReg)
2240b57cec5SDimitry Andric     return Subtarget.hasVector()? CSR_SystemZ_AllRegs_Vector_RegMask
2250b57cec5SDimitry Andric                                 : CSR_SystemZ_AllRegs_RegMask;
2260b57cec5SDimitry Andric   if (MF.getSubtarget().getTargetLowering()->supportSwiftError() &&
2270b57cec5SDimitry Andric       MF.getFunction().getAttributes().hasAttrSomewhere(
2280b57cec5SDimitry Andric           Attribute::SwiftError))
2290b57cec5SDimitry Andric     return CSR_SystemZ_SwiftError_RegMask;
230*fe6060f1SDimitry Andric   return CSR_SystemZ_ELF_RegMask;
231*fe6060f1SDimitry Andric }
232*fe6060f1SDimitry Andric 
233*fe6060f1SDimitry Andric SystemZRegisterInfo::SystemZRegisterInfo(unsigned int RA)
234*fe6060f1SDimitry Andric     : SystemZGenRegisterInfo(RA) {}
235*fe6060f1SDimitry Andric 
236*fe6060f1SDimitry Andric const MCPhysReg *
237*fe6060f1SDimitry Andric SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
238*fe6060f1SDimitry Andric 
239*fe6060f1SDimitry Andric   const SystemZSubtarget *Subtarget = &MF->getSubtarget<SystemZSubtarget>();
240*fe6060f1SDimitry Andric   SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
241*fe6060f1SDimitry Andric 
242*fe6060f1SDimitry Andric   return Regs->getCalleeSavedRegs(MF);
243*fe6060f1SDimitry Andric }
244*fe6060f1SDimitry Andric 
245*fe6060f1SDimitry Andric const uint32_t *
246*fe6060f1SDimitry Andric SystemZRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
247*fe6060f1SDimitry Andric                                           CallingConv::ID CC) const {
248*fe6060f1SDimitry Andric 
249*fe6060f1SDimitry Andric   const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
250*fe6060f1SDimitry Andric   SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
251*fe6060f1SDimitry Andric   return Regs->getCallPreservedMask(MF, CC);
2520b57cec5SDimitry Andric }
2530b57cec5SDimitry Andric 
2540b57cec5SDimitry Andric BitVector
2550b57cec5SDimitry Andric SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
2560b57cec5SDimitry Andric   BitVector Reserved(getNumRegs());
2570b57cec5SDimitry Andric   const SystemZFrameLowering *TFI = getFrameLowering(MF);
258*fe6060f1SDimitry Andric   const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
259*fe6060f1SDimitry Andric   SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
260*fe6060f1SDimitry Andric   if (TFI->hasFP(MF))
261*fe6060f1SDimitry Andric     // The frame pointer. Reserve all aliases.
262*fe6060f1SDimitry Andric     for (MCRegAliasIterator AI(Regs->getFramePointerRegister(), this, true);
263*fe6060f1SDimitry Andric          AI.isValid(); ++AI)
264*fe6060f1SDimitry Andric       Reserved.set(*AI);
2650b57cec5SDimitry Andric 
266*fe6060f1SDimitry Andric   // Reserve all aliases for the stack pointer.
267*fe6060f1SDimitry Andric   for (MCRegAliasIterator AI(Regs->getStackPointerRegister(), this, true);
268*fe6060f1SDimitry Andric        AI.isValid(); ++AI)
269*fe6060f1SDimitry Andric     Reserved.set(*AI);
2700b57cec5SDimitry Andric 
2710b57cec5SDimitry Andric   // A0 and A1 hold the thread pointer.
2720b57cec5SDimitry Andric   Reserved.set(SystemZ::A0);
2730b57cec5SDimitry Andric   Reserved.set(SystemZ::A1);
2740b57cec5SDimitry Andric 
2750b57cec5SDimitry Andric   // FPC is the floating-point control register.
2760b57cec5SDimitry Andric   Reserved.set(SystemZ::FPC);
2770b57cec5SDimitry Andric 
2780b57cec5SDimitry Andric   return Reserved;
2790b57cec5SDimitry Andric }
2800b57cec5SDimitry Andric 
2810b57cec5SDimitry Andric void
2820b57cec5SDimitry Andric SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
2830b57cec5SDimitry Andric                                          int SPAdj, unsigned FIOperandNum,
2840b57cec5SDimitry Andric                                          RegScavenger *RS) const {
2850b57cec5SDimitry Andric   assert(SPAdj == 0 && "Outgoing arguments should be part of the frame");
2860b57cec5SDimitry Andric 
2870b57cec5SDimitry Andric   MachineBasicBlock &MBB = *MI->getParent();
2880b57cec5SDimitry Andric   MachineFunction &MF = *MBB.getParent();
2890b57cec5SDimitry Andric   auto *TII =
2900b57cec5SDimitry Andric       static_cast<const SystemZInstrInfo *>(MF.getSubtarget().getInstrInfo());
2910b57cec5SDimitry Andric   const SystemZFrameLowering *TFI = getFrameLowering(MF);
2920b57cec5SDimitry Andric   DebugLoc DL = MI->getDebugLoc();
2930b57cec5SDimitry Andric 
2940b57cec5SDimitry Andric   // Decompose the frame index into a base and offset.
2950b57cec5SDimitry Andric   int FrameIndex = MI->getOperand(FIOperandNum).getIndex();
2965ffd83dbSDimitry Andric   Register BasePtr;
297e8d8bef9SDimitry Andric   int64_t Offset =
298e8d8bef9SDimitry Andric       (TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed() +
2990b57cec5SDimitry Andric        MI->getOperand(FIOperandNum + 1).getImm());
3000b57cec5SDimitry Andric 
3010b57cec5SDimitry Andric   // Special handling of dbg_value instructions.
3020b57cec5SDimitry Andric   if (MI->isDebugValue()) {
3030b57cec5SDimitry Andric     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, /*isDef*/ false);
304*fe6060f1SDimitry Andric     if (MI->isNonListDebugValue()) {
3055ffd83dbSDimitry Andric       MI->getDebugOffset().ChangeToImmediate(Offset);
306*fe6060f1SDimitry Andric     } else {
307*fe6060f1SDimitry Andric       unsigned OpIdx = MI->getDebugOperandIndex(&MI->getOperand(FIOperandNum));
308*fe6060f1SDimitry Andric       SmallVector<uint64_t, 3> Ops;
309*fe6060f1SDimitry Andric       DIExpression::appendOffset(
310*fe6060f1SDimitry Andric           Ops, TFI->getFrameIndexReference(MF, FrameIndex, BasePtr).getFixed());
311*fe6060f1SDimitry Andric       MI->getDebugExpressionOp().setMetadata(
312*fe6060f1SDimitry Andric           DIExpression::appendOpsToArg(MI->getDebugExpression(), Ops, OpIdx));
313*fe6060f1SDimitry Andric     }
3140b57cec5SDimitry Andric     return;
3150b57cec5SDimitry Andric   }
3160b57cec5SDimitry Andric 
3170b57cec5SDimitry Andric   // See if the offset is in range, or if an equivalent instruction that
3180b57cec5SDimitry Andric   // accepts the offset exists.
3190b57cec5SDimitry Andric   unsigned Opcode = MI->getOpcode();
3200b57cec5SDimitry Andric   unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
3210b57cec5SDimitry Andric   if (OpcodeForOffset) {
3220b57cec5SDimitry Andric     if (OpcodeForOffset == SystemZ::LE &&
3230b57cec5SDimitry Andric         MF.getSubtarget<SystemZSubtarget>().hasVector()) {
3240b57cec5SDimitry Andric       // If LE is ok for offset, use LDE instead on z13.
3250b57cec5SDimitry Andric       OpcodeForOffset = SystemZ::LDE32;
3260b57cec5SDimitry Andric     }
3270b57cec5SDimitry Andric     MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
3280b57cec5SDimitry Andric   }
3290b57cec5SDimitry Andric   else {
3300b57cec5SDimitry Andric     // Create an anchor point that is in range.  Start at 0xffff so that
3310b57cec5SDimitry Andric     // can use LLILH to load the immediate.
3320b57cec5SDimitry Andric     int64_t OldOffset = Offset;
3330b57cec5SDimitry Andric     int64_t Mask = 0xffff;
3340b57cec5SDimitry Andric     do {
3350b57cec5SDimitry Andric       Offset = OldOffset & Mask;
3360b57cec5SDimitry Andric       OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
3370b57cec5SDimitry Andric       Mask >>= 1;
3380b57cec5SDimitry Andric       assert(Mask && "One offset must be OK");
3390b57cec5SDimitry Andric     } while (!OpcodeForOffset);
3400b57cec5SDimitry Andric 
3418bcb0991SDimitry Andric     Register ScratchReg =
3420b57cec5SDimitry Andric         MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass);
3430b57cec5SDimitry Andric     int64_t HighOffset = OldOffset - Offset;
3440b57cec5SDimitry Andric 
3450b57cec5SDimitry Andric     if (MI->getDesc().TSFlags & SystemZII::HasIndex
3460b57cec5SDimitry Andric         && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
3470b57cec5SDimitry Andric       // Load the offset into the scratch register and use it as an index.
3480b57cec5SDimitry Andric       // The scratch register then dies here.
3490b57cec5SDimitry Andric       TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
3500b57cec5SDimitry Andric       MI->getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
3510b57cec5SDimitry Andric       MI->getOperand(FIOperandNum + 2).ChangeToRegister(ScratchReg,
3520b57cec5SDimitry Andric                                                         false, false, true);
3530b57cec5SDimitry Andric     } else {
3540b57cec5SDimitry Andric       // Load the anchor address into a scratch register.
3550b57cec5SDimitry Andric       unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset);
3560b57cec5SDimitry Andric       if (LAOpcode)
3570b57cec5SDimitry Andric         BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
3580b57cec5SDimitry Andric           .addReg(BasePtr).addImm(HighOffset).addReg(0);
3590b57cec5SDimitry Andric       else {
3600b57cec5SDimitry Andric         // Load the high offset into the scratch register and use it as
3610b57cec5SDimitry Andric         // an index.
3620b57cec5SDimitry Andric         TII->loadImmediate(MBB, MI, ScratchReg, HighOffset);
363e8d8bef9SDimitry Andric         BuildMI(MBB, MI, DL, TII->get(SystemZ::LA), ScratchReg)
364e8d8bef9SDimitry Andric           .addReg(BasePtr, RegState::Kill).addImm(0).addReg(ScratchReg);
3650b57cec5SDimitry Andric       }
3660b57cec5SDimitry Andric 
3670b57cec5SDimitry Andric       // Use the scratch register as the base.  It then dies here.
3680b57cec5SDimitry Andric       MI->getOperand(FIOperandNum).ChangeToRegister(ScratchReg,
3690b57cec5SDimitry Andric                                                     false, false, true);
3700b57cec5SDimitry Andric     }
3710b57cec5SDimitry Andric   }
3720b57cec5SDimitry Andric   MI->setDesc(TII->get(OpcodeForOffset));
3730b57cec5SDimitry Andric   MI->getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
3740b57cec5SDimitry Andric }
3750b57cec5SDimitry Andric 
3760b57cec5SDimitry Andric bool SystemZRegisterInfo::shouldCoalesce(MachineInstr *MI,
3770b57cec5SDimitry Andric                                   const TargetRegisterClass *SrcRC,
3780b57cec5SDimitry Andric                                   unsigned SubReg,
3790b57cec5SDimitry Andric                                   const TargetRegisterClass *DstRC,
3800b57cec5SDimitry Andric                                   unsigned DstSubReg,
3810b57cec5SDimitry Andric                                   const TargetRegisterClass *NewRC,
3820b57cec5SDimitry Andric                                   LiveIntervals &LIS) const {
3830b57cec5SDimitry Andric   assert (MI->isCopy() && "Only expecting COPY instructions");
3840b57cec5SDimitry Andric 
3850b57cec5SDimitry Andric   // Coalesce anything which is not a COPY involving a subreg to/from GR128.
3860b57cec5SDimitry Andric   if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
3870b57cec5SDimitry Andric         (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64)))
3880b57cec5SDimitry Andric     return true;
3890b57cec5SDimitry Andric 
3900b57cec5SDimitry Andric   // Allow coalescing of a GR128 subreg COPY only if the live ranges are small
3910b57cec5SDimitry Andric   // and local to one MBB with not too much interferring registers. Otherwise
3920b57cec5SDimitry Andric   // regalloc may run out of registers.
3930b57cec5SDimitry Andric 
3940b57cec5SDimitry Andric   unsigned WideOpNo = (getRegSizeInBits(*SrcRC) == 128 ? 1 : 0);
3958bcb0991SDimitry Andric   Register GR128Reg = MI->getOperand(WideOpNo).getReg();
3968bcb0991SDimitry Andric   Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
3970b57cec5SDimitry Andric   LiveInterval &IntGR128 = LIS.getInterval(GR128Reg);
3980b57cec5SDimitry Andric   LiveInterval &IntGRNar = LIS.getInterval(GRNarReg);
3990b57cec5SDimitry Andric 
4000b57cec5SDimitry Andric   // Check that the two virtual registers are local to MBB.
4010b57cec5SDimitry Andric   MachineBasicBlock *MBB = MI->getParent();
4020b57cec5SDimitry Andric   MachineInstr *FirstMI_GR128 =
4030b57cec5SDimitry Andric     LIS.getInstructionFromIndex(IntGR128.beginIndex());
4040b57cec5SDimitry Andric   MachineInstr *FirstMI_GRNar =
4050b57cec5SDimitry Andric     LIS.getInstructionFromIndex(IntGRNar.beginIndex());
4060b57cec5SDimitry Andric   MachineInstr *LastMI_GR128 = LIS.getInstructionFromIndex(IntGR128.endIndex());
4070b57cec5SDimitry Andric   MachineInstr *LastMI_GRNar = LIS.getInstructionFromIndex(IntGRNar.endIndex());
4080b57cec5SDimitry Andric   if ((!FirstMI_GR128 || FirstMI_GR128->getParent() != MBB) ||
4090b57cec5SDimitry Andric       (!FirstMI_GRNar || FirstMI_GRNar->getParent() != MBB) ||
4100b57cec5SDimitry Andric       (!LastMI_GR128 || LastMI_GR128->getParent() != MBB) ||
4110b57cec5SDimitry Andric       (!LastMI_GRNar || LastMI_GRNar->getParent() != MBB))
4120b57cec5SDimitry Andric     return false;
4130b57cec5SDimitry Andric 
4140b57cec5SDimitry Andric   MachineBasicBlock::iterator MII = nullptr, MEE = nullptr;
4150b57cec5SDimitry Andric   if (WideOpNo == 1) {
4160b57cec5SDimitry Andric     MII = FirstMI_GR128;
4170b57cec5SDimitry Andric     MEE = LastMI_GRNar;
4180b57cec5SDimitry Andric   } else {
4190b57cec5SDimitry Andric     MII = FirstMI_GRNar;
4200b57cec5SDimitry Andric     MEE = LastMI_GR128;
4210b57cec5SDimitry Andric   }
4220b57cec5SDimitry Andric 
4230b57cec5SDimitry Andric   // Check if coalescing seems safe by finding the set of clobbered physreg
4240b57cec5SDimitry Andric   // pairs in the region.
4250b57cec5SDimitry Andric   BitVector PhysClobbered(getNumRegs());
4260b57cec5SDimitry Andric   MEE++;
4270b57cec5SDimitry Andric   for (; MII != MEE; ++MII) {
4280b57cec5SDimitry Andric     for (const MachineOperand &MO : MII->operands())
4298bcb0991SDimitry Andric       if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
4300b57cec5SDimitry Andric         for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
4310b57cec5SDimitry Andric              SI.isValid(); ++SI)
4320b57cec5SDimitry Andric           if (NewRC->contains(*SI)) {
4330b57cec5SDimitry Andric             PhysClobbered.set(*SI);
4340b57cec5SDimitry Andric             break;
4350b57cec5SDimitry Andric           }
4360b57cec5SDimitry Andric       }
4370b57cec5SDimitry Andric   }
4380b57cec5SDimitry Andric 
4390b57cec5SDimitry Andric   // Demand an arbitrary margin of free regs.
4400b57cec5SDimitry Andric   unsigned const DemandedFreeGR128 = 3;
4410b57cec5SDimitry Andric   if (PhysClobbered.count() > (NewRC->getNumRegs() - DemandedFreeGR128))
4420b57cec5SDimitry Andric     return false;
4430b57cec5SDimitry Andric 
4440b57cec5SDimitry Andric   return true;
4450b57cec5SDimitry Andric }
4460b57cec5SDimitry Andric 
4470b57cec5SDimitry Andric Register
4480b57cec5SDimitry Andric SystemZRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
4490b57cec5SDimitry Andric   const SystemZFrameLowering *TFI = getFrameLowering(MF);
450*fe6060f1SDimitry Andric   const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
451*fe6060f1SDimitry Andric   SystemZCallingConventionRegisters *Regs = Subtarget->getSpecialRegisters();
452*fe6060f1SDimitry Andric 
453*fe6060f1SDimitry Andric   return TFI->hasFP(MF) ? Regs->getFramePointerRegister()
454*fe6060f1SDimitry Andric                         : Regs->getStackPointerRegister();
4550b57cec5SDimitry Andric }
4560b57cec5SDimitry Andric 
4570b57cec5SDimitry Andric const TargetRegisterClass *
4580b57cec5SDimitry Andric SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
4590b57cec5SDimitry Andric   if (RC == &SystemZ::CCRRegClass)
4600b57cec5SDimitry Andric     return &SystemZ::GR32BitRegClass;
4610b57cec5SDimitry Andric   return RC;
4620b57cec5SDimitry Andric }
4630b57cec5SDimitry Andric 
464