1//===-- SystemZOperands.td - SystemZ instruction operands ----*- tblgen-*--===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Class definitions 11//===----------------------------------------------------------------------===// 12 13class ImmediateAsmOperand<string name> 14 : AsmOperandClass { 15 let Name = name; 16 let RenderMethod = "addImmOperands"; 17} 18class ImmediateTLSAsmOperand<string name> 19 : AsmOperandClass { 20 let Name = name; 21 let RenderMethod = "addImmTLSOperands"; 22} 23 24class ImmediateOp<ValueType vt, string asmop> : Operand<vt> { 25 let PrintMethod = "print"#asmop#"Operand"; 26 let EncoderMethod = "getImmOpValue<SystemZ::FK_390_"#asmop#">"; 27 let DecoderMethod = "decode"#asmop#"Operand"; 28 let ParserMatchClass = !cast<AsmOperandClass>(asmop); 29 let OperandType = "OPERAND_IMMEDIATE"; 30} 31 32class ImmOpWithPattern<ValueType vt, string asmop, code pred, SDNodeXForm xform, 33 SDNode ImmNode = imm> : 34 ImmediateOp<vt, asmop>, PatLeaf<(vt ImmNode), pred, xform>; 35 36// class ImmediatePatLeaf<ValueType vt, code pred, 37// SDNodeXForm xform, SDNode ImmNode> 38// : PatLeaf<(vt ImmNode), pred, xform>; 39 40 41// Constructs both a DAG pattern and instruction operand for an immediate 42// of type VT. PRED returns true if a node is acceptable and XFORM returns 43// the operand value associated with the node. ASMOP is the name of the 44// associated asm operand, and also forms the basis of the asm print method. 45multiclass Immediate<ValueType vt, code pred, SDNodeXForm xform, string asmop> { 46 // def "" : ImmediateOp<vt, asmop>, 47 // PatLeaf<(vt imm), pred, xform>; 48 def "" : ImmOpWithPattern<vt, asmop, pred, xform>; 49 50// def _timm : PatLeaf<(vt timm), pred, xform>; 51 def _timm : ImmOpWithPattern<vt, asmop, pred, xform, timm>; 52} 53 54// Constructs an asm operand for a PC-relative address. SIZE says how 55// many bits there are. 56class PCRelAsmOperand<string size> : ImmediateAsmOperand<"PCRel"#size> { 57 let PredicateMethod = "isImm"; 58 let ParserMethod = "parsePCRel"#size; 59} 60class PCRelTLSAsmOperand<string size> 61 : ImmediateTLSAsmOperand<"PCRelTLS"#size> { 62 let PredicateMethod = "isImmTLS"; 63 let ParserMethod = "parsePCRelTLS"#size; 64} 65 66// Constructs an operand for a PC-relative address with address type VT. 67// ASMOP is the associated asm operand. 68let OperandType = "OPERAND_PCREL" in { 69 class PCRelOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 70 let PrintMethod = "printPCRelOperand"; 71 let ParserMatchClass = asmop; 72 } 73 class PCRelTLSOperand<ValueType vt, AsmOperandClass asmop> : Operand<vt> { 74 let PrintMethod = "printPCRelTLSOperand"; 75 let ParserMatchClass = asmop; 76 } 77} 78 79// Constructs both a DAG pattern and instruction operand for a PC-relative 80// address with address size VT. SELF is the name of the operand and 81// ASMOP is the associated asm operand. 82class PCRelAddress<ValueType vt, string self, AsmOperandClass asmop> 83 : ComplexPattern<vt, 1, "selectPCRelAddress", 84 [z_pcrel_wrapper, z_pcrel_offset]>, 85 PCRelOperand<vt, asmop> { 86 let MIOperandInfo = (ops !cast<Operand>(self)); 87} 88 89// Constructs an AsmOperandClass for addressing mode FORMAT, treating the 90// registers as having BITSIZE bits and displacements as having DISPSIZE bits. 91// LENGTH is "LenN" for addresses with an N-bit length field, otherwise it 92// is "". 93class AddressAsmOperand<string format, string bitsize, string dispsize, 94 string length = ""> 95 : AsmOperandClass { 96 let Name = format#bitsize#"Disp"#dispsize#length; 97 let ParserMethod = "parse"#format#bitsize; 98 let RenderMethod = "add"#format#"Operands"; 99} 100 101// Constructs an instruction operand for an addressing mode. FORMAT, 102// BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 103// AddressAsmOperand. OPERANDS is a list of individual operands 104// (base register, displacement, etc.). 105class AddressOperand<string bitsize, string dispsize, string length, 106 string format, dag operands> 107 : Operand<!cast<ValueType>("i"#bitsize)> { 108 let PrintMethod = "print"#format#"Operand"; 109 let OperandType = "OPERAND_MEMORY"; 110 let MIOperandInfo = operands; 111 let ParserMatchClass = 112 !cast<AddressAsmOperand>(format#bitsize#"Disp"#dispsize#length); 113} 114 115// Constructs both a DAG pattern and instruction operand for an addressing mode. 116// FORMAT, BITSIZE, DISPSIZE and LENGTH are the parameters to an associated 117// AddressAsmOperand. OPERANDS is a list of NUMOPS individual operands 118// (base register, displacement, etc.). SELTYPE is the type of the memory 119// operand for selection purposes; sometimes we want different selection 120// choices for the same underlying addressing mode. SUFFIX is similarly 121// a suffix appended to the displacement for selection purposes; 122// e.g. we want to reject small 20-bit displacements if a 12-bit form 123// also exists, but we want to accept them otherwise. 124class AddressingMode<string seltype, string bitsize, string dispsize, 125 string suffix, string length, int numops, string format, 126 dag operands> 127 : ComplexPattern<!cast<ValueType>("i"#bitsize), numops, 128 "select"#seltype#dispsize#suffix#length, 129 [add, sub, or, frameindex, z_adjdynalloc]>, 130 AddressOperand<bitsize, dispsize, length, format, operands>; 131 132// An addressing mode with a base and displacement but no index. 133class BDMode<string type, string bitsize, string dispsize, string suffix> 134 : AddressingMode<type, bitsize, dispsize, suffix, "", 2, "BDAddr", 135 (ops !cast<RegisterOperand>("ADDR"#bitsize), 136 !cast<Operand>("disp"#dispsize#"imm"#bitsize))>; 137 138// An addressing mode with a base, displacement and index. 139class BDXMode<string type, string bitsize, string dispsize, string suffix> 140 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDXAddr", 141 (ops !cast<RegisterOperand>("ADDR"#bitsize), 142 !cast<Operand>("disp"#dispsize#"imm"#bitsize), 143 !cast<RegisterOperand>("ADDR"#bitsize))>; 144 145// A BDMode paired with an immediate length operand of LENSIZE bits. 146class BDLMode<string type, string bitsize, string dispsize, string suffix, 147 string lensize> 148 : AddressingMode<type, bitsize, dispsize, suffix, "Len"#lensize, 3, 149 "BDLAddr", 150 (ops !cast<RegisterOperand>("ADDR"#bitsize), 151 !cast<Operand>("disp"#dispsize#"imm"#bitsize), 152 !cast<Operand>("len"#lensize#"imm"#bitsize))>; 153 154// A BDMode paired with a register length operand. 155class BDRMode<string type, string bitsize, string dispsize, string suffix> 156 : AddressingMode<type, bitsize, dispsize, suffix, "", 3, "BDRAddr", 157 (ops !cast<RegisterOperand>("ADDR"#bitsize), 158 !cast<Operand>("disp"#dispsize#"imm"#bitsize), 159 !cast<RegisterOperand>("GR"#bitsize))>; 160 161// An addressing mode with a base, displacement and a vector index. 162class BDVMode<string bitsize, string dispsize> 163 : AddressOperand<bitsize, dispsize, "", "BDVAddr", 164 (ops !cast<RegisterOperand>("ADDR"#bitsize), 165 !cast<Operand>("disp"#dispsize#"imm"#bitsize), 166 !cast<RegisterOperand>("VR128"))>; 167 168//===----------------------------------------------------------------------===// 169// Extracting immediate operands from nodes 170// These all create MVT::i64 nodes to ensure the value is not sign-extended 171// when converted from an SDNode to a MachineOperand later on. 172//===----------------------------------------------------------------------===// 173 174// Bits 0-15 (counting from the lsb). 175def LL16 : SDNodeXForm<imm, [{ 176 uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL; 177 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 178}]>; 179 180// Bits 16-31 (counting from the lsb). 181def LH16 : SDNodeXForm<imm, [{ 182 uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 183 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 184}]>; 185 186// Bits 32-47 (counting from the lsb). 187def HL16 : SDNodeXForm<imm, [{ 188 uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32; 189 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 190}]>; 191 192// Bits 48-63 (counting from the lsb). 193def HH16 : SDNodeXForm<imm, [{ 194 uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48; 195 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 196}]>; 197 198// Low 32 bits. 199def LF32 : SDNodeXForm<imm, [{ 200 uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL; 201 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 202}]>; 203 204// High 32 bits. 205def HF32 : SDNodeXForm<imm, [{ 206 uint64_t Value = N->getZExtValue() >> 32; 207 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 208}]>; 209 210// Negated variants. 211def NEGLH16 : SDNodeXForm<imm, [{ 212 uint64_t Value = (-N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16; 213 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 214}]>; 215 216def NEGLF32 : SDNodeXForm<imm, [{ 217 uint64_t Value = -N->getZExtValue() & 0x00000000FFFFFFFFULL; 218 return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64); 219}]>; 220 221// Truncate an immediate to a 8-bit signed quantity. 222def SIMM8 : SDNodeXForm<imm, [{ 223 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N), 224 MVT::i64); 225}]>; 226 227// Truncate an immediate to a 8-bit unsigned quantity. 228def UIMM8 : SDNodeXForm<imm, [{ 229 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N), 230 MVT::i64); 231}]>; 232 233// Truncate an immediate to a 8-bit unsigned quantity and mask off low bit. 234def UIMM8EVEN : SDNodeXForm<imm, [{ 235 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N), 236 MVT::i64); 237}]>; 238 239// Truncate an immediate to a 12-bit unsigned quantity. 240def UIMM12 : SDNodeXForm<imm, [{ 241 return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N), 242 MVT::i64); 243}]>; 244 245// Truncate an immediate to a 16-bit signed quantity. 246def SIMM16 : SDNodeXForm<imm, [{ 247 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N), 248 MVT::i64); 249}]>; 250 251// Negate and then truncate an immediate to a 16-bit signed quantity. 252def NEGSIMM16 : SDNodeXForm<imm, [{ 253 return CurDAG->getTargetConstant(int16_t(-N->getZExtValue()), SDLoc(N), 254 MVT::i64); 255}]>; 256 257// Truncate an immediate to a 16-bit unsigned quantity. 258def UIMM16 : SDNodeXForm<imm, [{ 259 return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N), 260 MVT::i64); 261}]>; 262 263// Truncate an immediate to a 32-bit signed quantity. 264def SIMM32 : SDNodeXForm<imm, [{ 265 return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N), 266 MVT::i64); 267}]>; 268 269// Negate and then truncate an immediate to a 32-bit unsigned quantity. 270def NEGSIMM32 : SDNodeXForm<imm, [{ 271 return CurDAG->getTargetConstant(int32_t(-N->getZExtValue()), SDLoc(N), 272 MVT::i64); 273}]>; 274 275// Truncate an immediate to a 32-bit unsigned quantity. 276def UIMM32 : SDNodeXForm<imm, [{ 277 return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N), 278 MVT::i64); 279}]>; 280 281// Negate and then truncate an immediate to a 32-bit unsigned quantity. 282def NEGUIMM32 : SDNodeXForm<imm, [{ 283 return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N), 284 MVT::i64); 285}]>; 286 287// Truncate an immediate to a 48-bit unsigned quantity. 288def UIMM48 : SDNodeXForm<imm, [{ 289 return CurDAG->getTargetConstant(uint64_t(N->getZExtValue()) & 0xffffffffffff, 290 SDLoc(N), MVT::i64); 291}]>; 292 293//===----------------------------------------------------------------------===// 294// Immediate asm operands. 295//===----------------------------------------------------------------------===// 296 297def U1Imm : ImmediateAsmOperand<"U1Imm">; 298def U2Imm : ImmediateAsmOperand<"U2Imm">; 299def U3Imm : ImmediateAsmOperand<"U3Imm">; 300def U4Imm : ImmediateAsmOperand<"U4Imm">; 301def S8Imm : ImmediateAsmOperand<"S8Imm">; 302def U8Imm : ImmediateAsmOperand<"U8Imm">; 303def U12Imm : ImmediateAsmOperand<"U12Imm">; 304def S16Imm : ImmediateAsmOperand<"S16Imm">; 305def U16Imm : ImmediateAsmOperand<"U16Imm">; 306def S32Imm : ImmediateAsmOperand<"S32Imm">; 307def U32Imm : ImmediateAsmOperand<"U32Imm">; 308def U48Imm : ImmediateAsmOperand<"U48Imm">; 309 310//===----------------------------------------------------------------------===// 311// i32 immediates 312//===----------------------------------------------------------------------===// 313 314// Immediates for the lower and upper 16 bits of an i32, with the other 315// bits of the i32 being zero. 316defm imm32ll16 : Immediate<i32, [{ 317 return SystemZ::isImmLL(N->getZExtValue()); 318}], LL16, "U16Imm">; 319 320defm imm32lh16 : Immediate<i32, [{ 321 return SystemZ::isImmLH(N->getZExtValue()); 322}], LH16, "U16Imm">; 323 324// Immediates for the lower and upper 16 bits of an i32, with the other 325// bits of the i32 being one. 326defm imm32ll16c : Immediate<i32, [{ 327 return SystemZ::isImmLL(uint32_t(~N->getZExtValue())); 328}], LL16, "U16Imm">; 329 330defm imm32lh16c : Immediate<i32, [{ 331 return SystemZ::isImmLH(uint32_t(~N->getZExtValue())); 332}], LH16, "U16Imm">; 333 334// Short immediates 335defm imm32zx1 : Immediate<i32, [{ 336 return isUInt<1>(N->getZExtValue()); 337}], NOOP_SDNodeXForm, "U1Imm">; 338 339defm imm32zx2 : Immediate<i32, [{ 340 return isUInt<2>(N->getZExtValue()); 341}], NOOP_SDNodeXForm, "U2Imm">; 342 343defm imm32zx3 : Immediate<i32, [{ 344 return isUInt<3>(N->getZExtValue()); 345}], NOOP_SDNodeXForm, "U3Imm">; 346 347defm imm32zx4 : Immediate<i32, [{ 348 return isUInt<4>(N->getZExtValue()); 349}], NOOP_SDNodeXForm, "U4Imm">; 350 351// Note: this enforces an even value during code generation only. 352// When used from the assembler, any 4-bit value is allowed. 353defm imm32zx4even : Immediate<i32, [{ 354 return isUInt<4>(N->getZExtValue()); 355}], UIMM8EVEN, "U4Imm">; 356 357defm imm32sx8 : Immediate<i32, [{ 358 return isInt<8>(N->getSExtValue()); 359}], SIMM8, "S8Imm">; 360 361defm imm32zx8 : Immediate<i32, [{ 362 return isUInt<8>(N->getZExtValue()); 363}], UIMM8, "U8Imm">; 364 365defm imm32zx8trunc : Immediate<i32, [{}], UIMM8, "U8Imm">; 366 367defm imm32zx12 : Immediate<i32, [{ 368 return isUInt<12>(N->getZExtValue()); 369}], UIMM12, "U12Imm">; 370 371defm imm32sx16 : Immediate<i32, [{ 372 return isInt<16>(N->getSExtValue()); 373}], SIMM16, "S16Imm">; 374 375defm imm32sx16n : Immediate<i32, [{ 376 return isInt<16>(-N->getSExtValue()); 377}], NEGSIMM16, "S16Imm">; 378 379defm imm32zx16 : Immediate<i32, [{ 380 return isUInt<16>(N->getZExtValue()); 381}], UIMM16, "U16Imm">; 382 383defm imm32sx16trunc : Immediate<i32, [{}], SIMM16, "S16Imm">; 384defm imm32zx16trunc : Immediate<i32, [{}], UIMM16, "U16Imm">; 385 386// Full 32-bit immediates. we need both signed and unsigned versions 387// because the assembler is picky. E.g. AFI requires signed operands 388// while NILF requires unsigned ones. 389defm simm32 : Immediate<i32, [{}], SIMM32, "S32Imm">; 390defm uimm32 : Immediate<i32, [{}], UIMM32, "U32Imm">; 391 392defm simm32n : Immediate<i32, [{ 393 return isInt<32>(-N->getSExtValue()); 394}], NEGSIMM32, "S32Imm">; 395 396def imm32 : ImmLeaf<i32, [{}]>; 397 398//===----------------------------------------------------------------------===// 399// 64-bit immediates 400//===----------------------------------------------------------------------===// 401 402// Immediates for 16-bit chunks of an i64, with the other bits of the 403// i32 being zero. 404defm imm64ll16 : Immediate<i64, [{ 405 return SystemZ::isImmLL(N->getZExtValue()); 406}], LL16, "U16Imm">; 407 408defm imm64lh16 : Immediate<i64, [{ 409 return SystemZ::isImmLH(N->getZExtValue()); 410}], LH16, "U16Imm">; 411 412defm imm64hl16 : Immediate<i64, [{ 413 return SystemZ::isImmHL(N->getZExtValue()); 414}], HL16, "U16Imm">; 415 416defm imm64hh16 : Immediate<i64, [{ 417 return SystemZ::isImmHH(N->getZExtValue()); 418}], HH16, "U16Imm">; 419 420// Immediates for 16-bit chunks of an i64, with the other bits of the 421// i32 being one. 422defm imm64ll16c : Immediate<i64, [{ 423 return SystemZ::isImmLL(uint64_t(~N->getZExtValue())); 424}], LL16, "U16Imm">; 425 426defm imm64lh16c : Immediate<i64, [{ 427 return SystemZ::isImmLH(uint64_t(~N->getZExtValue())); 428}], LH16, "U16Imm">; 429 430defm imm64hl16c : Immediate<i64, [{ 431 return SystemZ::isImmHL(uint64_t(~N->getZExtValue())); 432}], HL16, "U16Imm">; 433 434defm imm64hh16c : Immediate<i64, [{ 435 return SystemZ::isImmHH(uint64_t(~N->getZExtValue())); 436}], HH16, "U16Imm">; 437 438// Immediates for the lower and upper 32 bits of an i64, with the other 439// bits of the i32 being zero. 440defm imm64lf32 : Immediate<i64, [{ 441 return SystemZ::isImmLF(N->getZExtValue()); 442}], LF32, "U32Imm">; 443 444defm imm64hf32 : Immediate<i64, [{ 445 return SystemZ::isImmHF(N->getZExtValue()); 446}], HF32, "U32Imm">; 447 448// Immediates for the lower and upper 32 bits of an i64, with the other 449// bits of the i32 being one. 450defm imm64lf32c : Immediate<i64, [{ 451 return SystemZ::isImmLF(uint64_t(~N->getZExtValue())); 452}], LF32, "U32Imm">; 453 454defm imm64hf32c : Immediate<i64, [{ 455 return SystemZ::isImmHF(uint64_t(~N->getZExtValue())); 456}], HF32, "U32Imm">; 457 458// Negated immediates that fit LF32 or LH16. 459defm imm64lh16n : Immediate<i64, [{ 460 return SystemZ::isImmLH(uint64_t(-N->getZExtValue())); 461}], NEGLH16, "U16Imm">; 462 463defm imm64lf32n : Immediate<i64, [{ 464 return SystemZ::isImmLF(uint64_t(-N->getZExtValue())); 465}], NEGLF32, "U32Imm">; 466 467// Short immediates. 468defm imm64sx8 : Immediate<i64, [{ 469 return isInt<8>(N->getSExtValue()); 470}], SIMM8, "S8Imm">; 471 472defm imm64zx8 : Immediate<i64, [{ 473 return isUInt<8>(N->getSExtValue()); 474}], UIMM8, "U8Imm">; 475 476defm imm64sx16 : Immediate<i64, [{ 477 return isInt<16>(N->getSExtValue()); 478}], SIMM16, "S16Imm">; 479 480defm imm64sx16n : Immediate<i64, [{ 481 return isInt<16>(-N->getSExtValue()); 482}], NEGSIMM16, "S16Imm">; 483 484defm imm64zx16 : Immediate<i64, [{ 485 return isUInt<16>(N->getZExtValue()); 486}], UIMM16, "U16Imm">; 487 488defm imm64sx32 : Immediate<i64, [{ 489 return isInt<32>(N->getSExtValue()); 490}], SIMM32, "S32Imm">; 491 492defm imm64sx32n : Immediate<i64, [{ 493 return isInt<32>(-N->getSExtValue()); 494}], NEGSIMM32, "S32Imm">; 495 496defm imm64zx32 : Immediate<i64, [{ 497 return isUInt<32>(N->getZExtValue()); 498}], UIMM32, "U32Imm">; 499 500defm imm64zx32n : Immediate<i64, [{ 501 return isUInt<32>(-N->getSExtValue()); 502}], NEGUIMM32, "U32Imm">; 503 504defm imm64zx48 : Immediate<i64, [{ 505 return isUInt<64>(N->getZExtValue()); 506}], UIMM48, "U48Imm">; 507 508class Imm64 : ImmLeaf<i64, [{}]>, Operand<i64> { 509 let OperandType = "OPERAND_IMMEDIATE"; 510} 511def imm64 : Imm64; 512def len4imm64 : Imm64 { 513 let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U4Imm>"; 514 let DecoderMethod = "decodeLenOperand<4>"; 515} 516def len8imm64 : Imm64 { 517 let EncoderMethod = "getLenEncoding<SystemZ::FK_390_U8Imm>"; 518 let DecoderMethod = "decodeLenOperand<8>"; 519} 520 521//===----------------------------------------------------------------------===// 522// Floating-point immediates 523//===----------------------------------------------------------------------===// 524 525// Floating-point zero. 526def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>; 527 528// Floating point negative zero. 529def fpimmneg0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(-0.0); }]>; 530 531//===----------------------------------------------------------------------===// 532// Symbolic address operands 533//===----------------------------------------------------------------------===// 534 535// PC-relative asm operands. 536def PCRel12 : PCRelAsmOperand<"12">; 537def PCRel16 : PCRelAsmOperand<"16">; 538def PCRel24 : PCRelAsmOperand<"24">; 539def PCRel32 : PCRelAsmOperand<"32">; 540def PCRelTLS16 : PCRelTLSAsmOperand<"16">; 541def PCRelTLS32 : PCRelTLSAsmOperand<"32">; 542 543// PC-relative offsets of a basic block. The offset is sign-extended 544// and multiplied by 2. 545def brtarget16 : PCRelOperand<OtherVT, PCRel16> { 546 let EncoderMethod = "getPC16DBLEncoding"; 547 let DecoderMethod = "decodePC16DBLBranchOperand"; 548} 549def brtarget32 : PCRelOperand<OtherVT, PCRel32> { 550 let EncoderMethod = "getPC32DBLEncoding"; 551 let DecoderMethod = "decodePC32DBLBranchOperand"; 552} 553 554// Variants of brtarget for use with branch prediction preload. 555def brtarget12bpp : PCRelOperand<OtherVT, PCRel12> { 556 let EncoderMethod = "getPC12DBLBPPEncoding"; 557 let DecoderMethod = "decodePC12DBLBranchOperand"; 558} 559def brtarget16bpp : PCRelOperand<OtherVT, PCRel16> { 560 let EncoderMethod = "getPC16DBLBPPEncoding"; 561 let DecoderMethod = "decodePC16DBLBranchOperand"; 562} 563def brtarget24bpp : PCRelOperand<OtherVT, PCRel24> { 564 let EncoderMethod = "getPC24DBLBPPEncoding"; 565 let DecoderMethod = "decodePC24DBLBranchOperand"; 566} 567 568// Variants of brtarget16/32 with an optional additional TLS symbol. 569// These are used to annotate calls to __tls_get_offset. 570def tlssym : Operand<i64> { } 571def brtarget16tls : PCRelTLSOperand<OtherVT, PCRelTLS16> { 572 let MIOperandInfo = (ops brtarget16:$func, tlssym:$sym); 573 let EncoderMethod = "getPC16DBLTLSEncoding"; 574 let DecoderMethod = "decodePC16DBLBranchOperand"; 575} 576def brtarget32tls : PCRelTLSOperand<OtherVT, PCRelTLS32> { 577 let MIOperandInfo = (ops brtarget32:$func, tlssym:$sym); 578 let EncoderMethod = "getPC32DBLTLSEncoding"; 579 let DecoderMethod = "decodePC32DBLBranchOperand"; 580} 581 582// A PC-relative offset of a global value. The offset is sign-extended 583// and multiplied by 2. 584def pcrel32 : PCRelAddress<i64, "pcrel32", PCRel32> { 585 let EncoderMethod = "getPC32DBLEncoding"; 586 let DecoderMethod = "decodePC32DBLOperand"; 587} 588 589//===----------------------------------------------------------------------===// 590// Addressing modes 591//===----------------------------------------------------------------------===// 592 593// 12-bit displacement operands. 594let EncoderMethod = "getImmOpValue<SystemZ::FK_390_U12Imm>", 595 DecoderMethod = "decodeU12ImmOperand" in { 596 def disp12imm32 : Operand<i32>; 597 def disp12imm64 : Operand<i64>; 598} 599 600// 20-bit displacement operands. 601let EncoderMethod = "getImmOpValue<SystemZ::FK_390_S20Imm>", 602 DecoderMethod = "decodeS20ImmOperand" in { 603 def disp20imm32 : Operand<i32>; 604 def disp20imm64 : Operand<i64>; 605} 606 607def BDAddr32Disp12 : AddressAsmOperand<"BDAddr", "32", "12">; 608def BDAddr32Disp20 : AddressAsmOperand<"BDAddr", "32", "20">; 609def BDAddr64Disp12 : AddressAsmOperand<"BDAddr", "64", "12">; 610def BDAddr64Disp20 : AddressAsmOperand<"BDAddr", "64", "20">; 611def BDXAddr64Disp12 : AddressAsmOperand<"BDXAddr", "64", "12">; 612def BDXAddr64Disp20 : AddressAsmOperand<"BDXAddr", "64", "20">; 613def BDLAddr64Disp12Len4 : AddressAsmOperand<"BDLAddr", "64", "12", "Len4">; 614def BDLAddr64Disp12Len8 : AddressAsmOperand<"BDLAddr", "64", "12", "Len8">; 615def BDRAddr64Disp12 : AddressAsmOperand<"BDRAddr", "64", "12">; 616def BDVAddr64Disp12 : AddressAsmOperand<"BDVAddr", "64", "12">; 617 618// DAG patterns and operands for addressing modes. Each mode has 619// the form <type><range><group>[<len>] where: 620// 621// <type> is one of: 622// shift : base + displacement (32-bit) 623// bdaddr : base + displacement 624// mviaddr : like bdaddr, but reject cases with a natural index 625// bdxaddr : base + displacement + index 626// laaddr : like bdxaddr, but used for Load Address operations 627// dynalloc : base + displacement + index + ADJDYNALLOC 628// bdladdr : base + displacement with a length field 629// bdvaddr : base + displacement with a vector index 630// 631// <range> is one of: 632// 12 : the displacement is an unsigned 12-bit value 633// 20 : the displacement is a signed 20-bit value 634// 635// <group> is one of: 636// pair : used when there is an equivalent instruction with the opposite 637// range value (12 or 20) 638// only : used when there is no equivalent instruction with the opposite 639// range value 640// 641// <len> is one of: 642// 643// <empty> : there is no length field 644// len8 : the length field is 8 bits, with a range of [1, 0x100]. 645def shift12only : BDMode <"BDAddr", "32", "12", "Only">; 646def shift20only : BDMode <"BDAddr", "32", "20", "Only">; 647def bdaddr12only : BDMode <"BDAddr", "64", "12", "Only">; 648def bdaddr12pair : BDMode <"BDAddr", "64", "12", "Pair">; 649def bdaddr20only : BDMode <"BDAddr", "64", "20", "Only">; 650def bdaddr20pair : BDMode <"BDAddr", "64", "20", "Pair">; 651def mviaddr12pair : BDMode <"MVIAddr", "64", "12", "Pair">; 652def mviaddr20pair : BDMode <"MVIAddr", "64", "20", "Pair">; 653def bdxaddr12only : BDXMode<"BDXAddr", "64", "12", "Only">; 654def bdxaddr12pair : BDXMode<"BDXAddr", "64", "12", "Pair">; 655def bdxaddr20only : BDXMode<"BDXAddr", "64", "20", "Only">; 656def bdxaddr20only128 : BDXMode<"BDXAddr", "64", "20", "Only128">; 657def bdxaddr20pair : BDXMode<"BDXAddr", "64", "20", "Pair">; 658def dynalloc12only : BDXMode<"DynAlloc", "64", "12", "Only">; 659def laaddr12pair : BDXMode<"LAAddr", "64", "12", "Pair">; 660def laaddr20pair : BDXMode<"LAAddr", "64", "20", "Pair">; 661def bdladdr12onlylen4 : BDLMode<"BDLAddr", "64", "12", "Only", "4">; 662def bdladdr12onlylen8 : BDLMode<"BDLAddr", "64", "12", "Only", "8">; 663def bdraddr12only : BDRMode<"BDRAddr", "64", "12", "Only">; 664def bdvaddr12only : BDVMode< "64", "12">; 665 666//===----------------------------------------------------------------------===// 667// Miscellaneous 668//===----------------------------------------------------------------------===// 669 670// A 4-bit condition-code mask. 671def cond4 : PatLeaf<(i32 timm), [{ return (N->getZExtValue() < 16); }]>, 672 Operand<i32> { 673 let PrintMethod = "printCond4Operand"; 674 let OperandType = "OPERAND_IMMEDIATE"; 675} 676