1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1, 46 hasSideEffects = 1 in 47 def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>; 48 49//===----------------------------------------------------------------------===// 50// Branch instructions 51//===----------------------------------------------------------------------===// 52 53// Conditional branches. 54let isBranch = 1, isTerminator = 1, Uses = [CC] in { 55 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 56 // with the condition-code mask being the first operand. It seems friendlier 57 // to use mnemonic forms like JE and JLH when writing out the assembly though. 58 let isCodeGenOnly = 1 in { 59 // An assembler extended mnemonic for BRC. 60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 61 // An assembler extended mnemonic for BRCL. (The extension is "G" 62 // rather than "L" because "JL" is "Jump if Less".) 63 def BRCL : CondBranchRIL<"jg#", 0xC04>; 64 let isIndirectBranch = 1 in { 65 def BC : CondBranchRX<"b#", 0x47>; 66 def BCR : CondBranchRR<"b#r", 0x07>; 67 def BIC : CondBranchRXY<"bi#", 0xe347>, 68 Requires<[FeatureMiscellaneousExtensions2]>; 69 } 70 } 71 72 // Allow using the raw forms directly from the assembler (and occasional 73 // special code generation needs) as well. 74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 76 let isIndirectBranch = 1 in { 77 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 79 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 80 Requires<[FeatureMiscellaneousExtensions2]>; 81 } 82 83 // Define AsmParser extended mnemonics for each general condition-code mask 84 // (integer or floating-point) 85 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 86 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 87 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 88 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 89 let isIndirectBranch = 1 in { 90 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 91 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 92 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 93 Requires<[FeatureMiscellaneousExtensions2]>; 94 } 95 } 96} 97 98// Unconditional branches. These are in fact simply variants of the 99// conditional branches with the condition mask set to "always". 100let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 101 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 102 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 103 let isIndirectBranch = 1 in { 104 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 105 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 106 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 107 Requires<[FeatureMiscellaneousExtensions2]>; 108 } 109} 110 111// NOPs. These are again variants of the conditional branches, with the 112// condition mask set to "never". NOP_bare can't be an InstAlias since it 113// would need R0D hard coded which is not part of ADDR64BitRegClass. 114def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 115let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 116 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 117def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 118def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 119 120// An alias of BRC 0, label 121def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 122 123// An alias of BRCL 0, label 124// jgnop on att ; jlnop on hlasm 125def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 126 127// Fused compare-and-branch instructions. 128// 129// These instructions do not use or clobber the condition codes. 130// We nevertheless pretend that the relative compare-and-branch 131// instructions clobber CC, so that we can lower them to separate 132// comparisons and BRCLs if the branch ends up being out of range. 133let isBranch = 1, isTerminator = 1 in { 134 // As for normal branches, we handle these instructions internally in 135 // their raw CRJ-like form, but use assembly macros like CRJE when writing 136 // them out. Using the *Pair multiclasses, we also create the raw forms. 137 let Defs = [CC] in { 138 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 139 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 140 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 141 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 142 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 143 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 144 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 145 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 146 } 147 let isIndirectBranch = 1 in { 148 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 149 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 150 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 151 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 152 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 153 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 154 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 155 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 156 } 157 158 // Define AsmParser mnemonics for each integer condition-code mask. 159 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 160 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 161 let Defs = [CC] in { 162 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 163 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 164 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 165 imm32sx8>; 166 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 167 imm64sx8>; 168 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 169 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 170 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 171 imm32zx8>; 172 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 173 imm64zx8>; 174 } 175 let isIndirectBranch = 1 in { 176 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 177 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 178 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 179 imm32sx8>; 180 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 181 imm64sx8>; 182 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 183 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 184 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 185 imm32zx8>; 186 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 187 imm64zx8>; 188 } 189 } 190} 191 192// Decrement a register and branch if it is nonzero. These don't clobber CC, 193// but we might need to split long relative branches into sequences that do. 194let isBranch = 1, isTerminator = 1 in { 195 let Defs = [CC] in { 196 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 197 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 198 } 199 // This doesn't need to clobber CC since we never need to split it. 200 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 201 Requires<[FeatureHighWord]>; 202 203 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 204 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 205 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 206 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 207} 208 209let isBranch = 1, isTerminator = 1 in { 210 let Defs = [CC] in { 211 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 212 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 213 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 214 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 215 } 216 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 217 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 218 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 219 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 220} 221 222//===----------------------------------------------------------------------===// 223// Trap instructions 224//===----------------------------------------------------------------------===// 225 226// Unconditional trap. 227let hasCtrlDep = 1, hasSideEffects = 1 in 228 def Trap : Alias<4, (outs), (ins), [(trap)]>; 229 230// Conditional trap. 231let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 232 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 233 234// Fused compare-and-trap instructions. 235let hasCtrlDep = 1, hasSideEffects = 1 in { 236 // These patterns work the same way as for compare-and-branch. 237 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 238 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 239 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 240 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 241 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 242 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 243 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 244 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 245 let Predicates = [FeatureMiscellaneousExtensions] in { 246 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 247 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 248 } 249 250 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 251 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 252 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 253 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 254 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 255 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 256 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 257 imm32sx16>; 258 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 259 imm64sx16>; 260 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 261 imm32zx16>; 262 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 263 imm64zx16>; 264 let Predicates = [FeatureMiscellaneousExtensions] in { 265 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 266 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 267 } 268 } 269} 270 271//===----------------------------------------------------------------------===// 272// Call and return instructions 273//===----------------------------------------------------------------------===// 274 275// Define the general form of the call instructions for the asm parser. 276// These instructions don't hard-code %r14 as the return address register. 277let isCall = 1, Defs = [CC] in { 278 def BRAS : CallRI <"bras", 0xA75>; 279 def BRASL : CallRIL<"brasl", 0xC05>; 280 def BAS : CallRX <"bas", 0x4D>; 281 def BASR : CallRR <"basr", 0x0D>; 282} 283 284// z/OS XPLINK 285let Predicates = [IsTargetXPLINK64] in { 286 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 287 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 288 [(z_call pcrel32:$I2)]>; 289 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 290 [(z_call ADDR64:$R2)]>; 291 } 292 293 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in { 294 def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>; 295 } 296} 297 298// Regular calls. 299// z/Linux ELF 300let Predicates = [IsTargetELF] in { 301 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 302 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 303 [(z_call pcrel32:$I2)]>; 304 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 305 [(z_call ADDR64:$R2)]>; 306 } 307 308 // TLS calls. These will be lowered into a call to __tls_get_offset, 309 // with an extra relocation specifying the TLS symbol. 310 let isCall = 1, Defs = [R14D, CC] in { 311 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 312 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 313 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 314 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 315 } 316} 317 318// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 319// R1 used for ELF 320let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 321 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 322 [(z_sibcall pcrel32:$I2)]>; 323 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 324 [(z_sibcall ADDR64:$R2)]>; 325} 326 327// Conditional sibling calls. 328let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 329 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 330 pcrel32:$I2), []>; 331 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 332 ADDR64:$R2), []>; 333} 334 335// Fused compare and conditional sibling calls. 336let isCall = 1, isTerminator = 1, isReturn = 1 in { 337 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 338 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 339 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 340 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 341 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 342 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 343 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 344 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 345} 346 347let Predicates = [IsTargetXPLINK64] in { 348 // A return instruction (b 2(%r7)). 349 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 350 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retflag)]>; 351 352 // A conditional return instruction (bc <cond>, 2(%r7)). 353 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 354 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 355} 356 357let Predicates = [IsTargetELF] in { 358 // A return instruction (br %r14). 359 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 360 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 361 362 // A conditional return instruction (bcr <cond>, %r14). 363 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 364 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 365} 366 367// Fused compare and conditional returns. 368let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 369 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 370 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 371 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 372 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 373 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 374 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 375 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 376 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 377} 378 379//===----------------------------------------------------------------------===// 380// Select instructions 381//===----------------------------------------------------------------------===// 382 383def Select32 : SelectWrapper<i32, GR32>, 384 Requires<[FeatureNoLoadStoreOnCond]>; 385def Select64 : SelectWrapper<i64, GR64>, 386 Requires<[FeatureNoLoadStoreOnCond]>; 387 388// We don't define 32-bit Mux stores if we don't have STOCFH, because the 389// low-only STOC should then always be used if possible. 390defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 391 nonvolatile_anyextloadi8, bdxaddr20only>, 392 Requires<[FeatureHighWord]>; 393defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 394 nonvolatile_anyextloadi16, bdxaddr20only>, 395 Requires<[FeatureHighWord]>; 396defm CondStore32Mux : CondStores<GRX32, simple_store, 397 simple_load, bdxaddr20only>, 398 Requires<[FeatureLoadStoreOnCond2]>; 399defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 400 nonvolatile_anyextloadi8, bdxaddr20only>; 401defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 402 nonvolatile_anyextloadi16, bdxaddr20only>; 403defm CondStore32 : CondStores<GR32, simple_store, 404 simple_load, bdxaddr20only>; 405 406defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 407 nonvolatile_anyextloadi8, bdxaddr20only>; 408defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 409 nonvolatile_anyextloadi16, bdxaddr20only>; 410defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 411 nonvolatile_anyextloadi32, bdxaddr20only>; 412defm CondStore64 : CondStores<GR64, simple_store, 413 simple_load, bdxaddr20only>; 414 415//===----------------------------------------------------------------------===// 416// Move instructions 417//===----------------------------------------------------------------------===// 418 419// Register moves. 420def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 421def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 422 423let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 424 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 425 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 426} 427 428let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 429 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 430 431// Immediate moves. 432let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 433 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 434 // deopending on the choice of register. 435 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 436 Requires<[FeatureHighWord]>; 437 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 438 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 439 440 // Other 16-bit immediates. 441 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 442 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 443 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 444 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 445 446 // 32-bit immediates. 447 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 448 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 449 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 450} 451 452// Register loads. 453let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 454 // Expands to L, LY or LFH, depending on the choice of register. 455 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 456 Requires<[FeatureHighWord]>; 457 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 458 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 459 Requires<[FeatureHighWord]>; 460 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 461 462 // These instructions are split after register allocation, so we don't 463 // want a custom inserter. 464 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 465 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 466 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 467 } 468} 469let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 470 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 471 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 472} 473 474let canFoldAsLoad = 1 in { 475 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 476 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 477} 478 479// Load and zero rightmost byte. 480let Predicates = [FeatureLoadAndZeroRightmostByte] in { 481 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 482 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 483 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 484 (LZRF bdxaddr20only:$src)>; 485 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 486 (LZRG bdxaddr20only:$src)>; 487} 488 489// Load and trap. 490let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 491 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 492 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 493 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 494} 495 496// Register stores. 497let SimpleBDXStore = 1, mayStore = 1 in { 498 // Expands to ST, STY or STFH, depending on the choice of register. 499 def STMux : StoreRXYPseudo<store, GRX32, 4>, 500 Requires<[FeatureHighWord]>; 501 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 502 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 503 Requires<[FeatureHighWord]>; 504 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 505 506 // These instructions are split after register allocation, so we don't 507 // want a custom inserter. 508 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 509 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 510 [(store GR128:$src, bdxaddr20only128:$dst)]>; 511 } 512} 513def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 514def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 515 516// 8-bit immediate stores to 8-bit fields. 517defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 518 519// 16-bit immediate stores to 16-, 32- or 64-bit fields. 520def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 521def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 522def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 523 524// Memory-to-memory moves. 525let mayLoad = 1, mayStore = 1 in 526 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 527let mayLoad = 1, mayStore = 1, Defs = [CC] in { 528 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 529 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 530 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 531} 532 533// Memset[Length][Byte] pseudos. 534def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 535def MemsetImmReg : MemsetPseudo<imm64, GR32>; 536def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 537def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 538 539// Move right. 540let Predicates = [FeatureMiscellaneousExtensions3], 541 mayLoad = 1, mayStore = 1, Uses = [R0L] in 542 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 543 544// String moves. 545let mayLoad = 1, mayStore = 1, Defs = [CC] in 546 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 547 548//===----------------------------------------------------------------------===// 549// Conditional move instructions 550//===----------------------------------------------------------------------===// 551 552let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 553 // Select. 554 let isCommutable = 1 in { 555 // Expands to SELR or SELFHR or a branch-and-move sequence, 556 // depending on the choice of registers. 557 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 558 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 559 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 560 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 561 } 562 563 // Define AsmParser extended mnemonics for each general condition-code mask. 564 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 565 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 566 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 567 GR32, GR32, GR32>; 568 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 569 GRH32, GRH32, GRH32>; 570 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 571 GR64, GR64, GR64>; 572 } 573} 574 575let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 576 // Load immediate on condition. Matched via DAG pattern and created 577 // by the PeepholeOptimizer via FoldImmediate. 578 579 // Expands to LOCHI or LOCHHI, depending on the choice of register. 580 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 581 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 582 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 583 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 584 585 // Move register on condition. Matched via DAG pattern and 586 // created by early if-conversion. 587 let isCommutable = 1 in { 588 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 589 // depending on the choice of registers. 590 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 591 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 592 } 593 594 // Load on condition. Matched via DAG pattern. 595 // Expands to LOC or LOCFH, depending on the choice of register. 596 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 597 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 598 599 // Store on condition. Expanded from CondStore* pseudos. 600 // Expands to STOC or STOCFH, depending on the choice of register. 601 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 602 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 603 604 // Define AsmParser extended mnemonics for each general condition-code mask. 605 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 606 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 607 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 608 imm32sx16>; 609 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 610 imm64sx16>; 611 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 612 imm32sx16>; 613 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 614 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 615 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 616 } 617} 618 619let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 620 // Move register on condition. Matched via DAG pattern and 621 // created by early if-conversion. 622 let isCommutable = 1 in { 623 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 624 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 625 } 626 627 // Load on condition. Matched via DAG pattern. 628 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 629 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 630 631 // Store on condition. Expanded from CondStore* pseudos. 632 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 633 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 634 635 // Define AsmParser extended mnemonics for each general condition-code mask. 636 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 637 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 638 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 639 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 640 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 641 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 642 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 643 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 644 } 645} 646//===----------------------------------------------------------------------===// 647// Sign extensions 648//===----------------------------------------------------------------------===// 649// 650// Note that putting these before zero extensions mean that we will prefer 651// them for anyextload*. There's not really much to choose between the two 652// either way, but signed-extending loads have a short LH and a long LHY, 653// while zero-extending loads have only the long LLH. 654// 655//===----------------------------------------------------------------------===// 656 657// 32-bit extensions from registers. 658def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 659def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 660 661// 64-bit extensions from registers. 662def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 663def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 664def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 665 666let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 667 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 668 669// Match 32-to-64-bit sign extensions in which the source is already 670// in a 64-bit register. 671def : Pat<(sext_inreg GR64:$src, i32), 672 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 673 674// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 675// depending on the choice of register. 676def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 677 Requires<[FeatureHighWord]>; 678def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 679def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 680 Requires<[FeatureHighWord]>; 681 682// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 683// depending on the choice of register. 684def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 685 Requires<[FeatureHighWord]>; 686defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 687def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 688 Requires<[FeatureHighWord]>; 689def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 690 691// 64-bit extensions from memory. 692def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 693def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 694def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 695def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 696def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 697let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 698 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 699 700//===----------------------------------------------------------------------===// 701// Zero extensions 702//===----------------------------------------------------------------------===// 703 704// 32-bit extensions from registers. 705 706// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 707def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 708 Requires<[FeatureHighWord]>; 709def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 710// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 711def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 712 Requires<[FeatureHighWord]>; 713def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 714 715// 64-bit extensions from registers. 716def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 717def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 718def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 719 720// Match 32-to-64-bit zero extensions in which the source is already 721// in a 64-bit register. 722def : Pat<(and GR64:$src, 0xffffffff), 723 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 724 725// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 726// depending on the choice of register. 727def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 728 Requires<[FeatureHighWord]>; 729def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 730def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 731 Requires<[FeatureHighWord]>; 732 733// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 734// depending on the choice of register. 735def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 736 Requires<[FeatureHighWord]>; 737def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 738def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 739 Requires<[FeatureHighWord]>; 740def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 741 742// 64-bit extensions from memory. 743def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 744def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 745def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 746def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 747def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 748 749// 31-to-64-bit zero extensions. 750def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 751def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 752def : Pat<(and GR64:$src, 0x7fffffff), 753 (LLGTR GR64:$src)>; 754def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 755 (LLGT bdxaddr20only:$src)>; 756 757// Load and zero rightmost byte. 758let Predicates = [FeatureLoadAndZeroRightmostByte] in { 759 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 760 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 761 (LLZRGF bdxaddr20only:$src)>; 762} 763 764// Load and trap. 765let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 766 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 767 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 768} 769 770// Extend GR64s to GR128s. 771let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 772 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 773 774//===----------------------------------------------------------------------===// 775// "Any" extensions 776//===----------------------------------------------------------------------===// 777 778// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 779def : Pat<(i64 (anyext GR32:$src)), 780 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 781 782// Extend GR64s to GR128s. 783let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 784 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 785 786//===----------------------------------------------------------------------===// 787// Truncations 788//===----------------------------------------------------------------------===// 789 790// Truncations of 64-bit registers to 32-bit registers. 791def : Pat<(i32 (trunc GR64:$src)), 792 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 793 794// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 795// STC, STCY or STCH, depending on the choice of register. 796def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 797 Requires<[FeatureHighWord]>; 798defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 799def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 800 Requires<[FeatureHighWord]>; 801 802// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 803// STH, STHY or STHH, depending on the choice of register. 804def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 805 Requires<[FeatureHighWord]>; 806defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 807def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 808 Requires<[FeatureHighWord]>; 809def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 810 811// Truncations of 64-bit registers to memory. 812defm : StoreGR64Pair<STC, STCY, truncstorei8>; 813defm : StoreGR64Pair<STH, STHY, truncstorei16>; 814def : StoreGR64PC<STHRL, aligned_truncstorei16>; 815defm : StoreGR64Pair<ST, STY, truncstorei32>; 816def : StoreGR64PC<STRL, aligned_truncstorei32>; 817 818// Store characters under mask -- not (yet) used for codegen. 819defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 820def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 821 822//===----------------------------------------------------------------------===// 823// Multi-register moves 824//===----------------------------------------------------------------------===// 825 826// Multi-register loads. 827defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 828def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 829def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 830def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 831 832// Multi-register stores. 833defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 834def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 835def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 836 837//===----------------------------------------------------------------------===// 838// Byte swaps 839//===----------------------------------------------------------------------===// 840 841// Byte-swapping register moves. 842def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 843def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 844 845// Byte-swapping loads. 846def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 847def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 848def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 849 850// Byte-swapping stores. 851def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 852def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 853def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 854 855// Byte-swapping memory-to-memory moves. 856let mayLoad = 1, mayStore = 1 in 857 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 858 859//===----------------------------------------------------------------------===// 860// Load address instructions 861//===----------------------------------------------------------------------===// 862 863// Load BDX-style addresses. 864let isAsCheapAsAMove = 1, isReMaterializable = 1 in 865 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 866 867// Load a PC-relative address. There's no version of this instruction 868// with a 16-bit offset, so there's no relaxation. 869let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 870 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 871 872// Load the Global Offset Table address. This will be lowered into a 873// larl $R1, _GLOBAL_OFFSET_TABLE_ 874// instruction. 875def GOT : Alias<6, (outs GR64:$R1), (ins), 876 [(set GR64:$R1, (global_offset_table))]>; 877 878//===----------------------------------------------------------------------===// 879// Absolute and Negation 880//===----------------------------------------------------------------------===// 881 882let Defs = [CC] in { 883 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 884 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 885 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 886 } 887 let CCValues = 0xE, CompareZeroCCMask = 0xE in 888 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 889} 890defm : SXU<abs, LPGFR>; 891 892let Defs = [CC] in { 893 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 894 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 895 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 896 } 897 let CCValues = 0xE, CompareZeroCCMask = 0xE in 898 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 899} 900defm : SXU<z_inegabs, LNGFR>; 901 902let Defs = [CC] in { 903 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 904 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 905 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 906 } 907 let CCValues = 0xE, CompareZeroCCMask = 0xE in 908 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 909} 910defm : SXU<ineg, LCGFR>; 911 912//===----------------------------------------------------------------------===// 913// Insertion 914//===----------------------------------------------------------------------===// 915 916let isCodeGenOnly = 1 in 917 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 918defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 919 920defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 921defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 922 923defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 924defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 925 926// Insert characters under mask -- not (yet) used for codegen. 927let Defs = [CC] in { 928 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 929 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 930} 931 932// Insertions of a 16-bit immediate, leaving other bits unaffected. 933// We don't have or_as_insert equivalents of these operations because 934// OI is available instead. 935// 936// IIxMux expands to II[LH]x, depending on the choice of register. 937def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 938 Requires<[FeatureHighWord]>; 939def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 940 Requires<[FeatureHighWord]>; 941def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 942def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 943def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 944def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 945def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 946def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 947def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 948def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 949 950// ...likewise for 32-bit immediates. For GR32s this is a general 951// full-width move. (We use IILF rather than something like LLILF 952// for 32-bit moves because IILF leaves the upper 32 bits of the 953// GR64 unchanged.) 954let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 955 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 956 Requires<[FeatureHighWord]>; 957 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 958 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 959} 960def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 961def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 962 963// An alternative model of inserthf, with the first operand being 964// a zero-extended value. 965def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 966 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 967 imm64hf32:$imm)>; 968 969//===----------------------------------------------------------------------===// 970// Addition 971//===----------------------------------------------------------------------===// 972 973// Addition producing a signed overflow flag. 974let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 975 // Addition of a register. 976 let isCommutable = 1 in { 977 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 978 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 979 } 980 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 981 982 // Addition to a high register. 983 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 984 Requires<[FeatureHighWord]>; 985 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 986 Requires<[FeatureHighWord]>; 987 988 // Addition of signed 16-bit immediates. 989 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 990 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 991 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 992 993 // Addition of signed 32-bit immediates. 994 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 995 Requires<[FeatureHighWord]>; 996 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 997 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 998 Requires<[FeatureHighWord]>; 999 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 1000 1001 // Addition of memory. 1002 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 1003 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 1004 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 1005 Requires<[FeatureMiscellaneousExtensions2]>; 1006 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 1007 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 1008 1009 // Addition to memory. 1010 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 1011 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 1012} 1013defm : SXB<z_sadd, GR64, AGFR>; 1014 1015// Addition producing a carry. 1016let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 1017 // Addition of a register. 1018 let isCommutable = 1 in { 1019 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1020 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1021 } 1022 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1023 1024 // Addition to a high register. 1025 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1026 Requires<[FeatureHighWord]>; 1027 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1028 Requires<[FeatureHighWord]>; 1029 1030 // Addition of signed 16-bit immediates. 1031 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1032 Requires<[FeatureDistinctOps]>; 1033 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1034 Requires<[FeatureDistinctOps]>; 1035 1036 // Addition of unsigned 32-bit immediates. 1037 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1038 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1039 1040 // Addition of signed 32-bit immediates. 1041 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1042 Requires<[FeatureHighWord]>; 1043 1044 // Addition of memory. 1045 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1046 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1047 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1048 1049 // Addition to memory. 1050 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1051 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1052} 1053defm : ZXB<z_uadd, GR64, ALGFR>; 1054 1055// Addition producing and using a carry. 1056let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1057 // Addition of a register. 1058 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1059 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1060 1061 // Addition of memory. 1062 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1063 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1064} 1065 1066// Addition that does not modify the condition code. 1067def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1068 Requires<[FeatureHighWord]>; 1069 1070 1071//===----------------------------------------------------------------------===// 1072// Subtraction 1073//===----------------------------------------------------------------------===// 1074 1075// Subtraction producing a signed overflow flag. 1076let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1077 CCIfNoSignedWrap = 1 in { 1078 // Subtraction of a register. 1079 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1080 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1081 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1082 1083 // Subtraction from a high register. 1084 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1085 Requires<[FeatureHighWord]>; 1086 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1087 Requires<[FeatureHighWord]>; 1088 1089 // Subtraction of memory. 1090 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1091 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1092 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1093 Requires<[FeatureMiscellaneousExtensions2]>; 1094 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1095 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1096} 1097defm : SXB<z_ssub, GR64, SGFR>; 1098 1099// Subtracting an immediate is the same as adding the negated immediate. 1100let AddedComplexity = 1 in { 1101 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1102 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1103 Requires<[FeatureHighWord]>; 1104 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1105 (AFIMux GR32:$src1, simm32n:$src2)>, 1106 Requires<[FeatureHighWord]>; 1107 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1108 (AHI GR32:$src1, imm32sx16n:$src2)>; 1109 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1110 (AFI GR32:$src1, simm32n:$src2)>; 1111 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1112 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1113 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1114 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1115} 1116 1117// And vice versa in one special case, where we need to load a 1118// constant into a register in any case, but the negated constant 1119// requires fewer instructions to load. 1120def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1121 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1122def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1123 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1124 1125// Subtraction producing a carry. 1126let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1127 // Subtraction of a register. 1128 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1129 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1130 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1131 1132 // Subtraction from a high register. 1133 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1134 Requires<[FeatureHighWord]>; 1135 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1136 Requires<[FeatureHighWord]>; 1137 1138 // Subtraction of unsigned 32-bit immediates. 1139 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1140 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1141 1142 // Subtraction of memory. 1143 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1144 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1145 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1146} 1147defm : ZXB<z_usub, GR64, SLGFR>; 1148 1149// Subtracting an immediate is the same as adding the negated immediate. 1150let AddedComplexity = 1 in { 1151 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1152 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1153 Requires<[FeatureDistinctOps]>; 1154 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1155 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1156 Requires<[FeatureDistinctOps]>; 1157} 1158 1159// And vice versa in one special case (but we prefer addition). 1160def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1161 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1162 1163// Subtraction producing and using a carry. 1164let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1165 // Subtraction of a register. 1166 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1167 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1168 1169 // Subtraction of memory. 1170 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1171 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1172} 1173 1174 1175//===----------------------------------------------------------------------===// 1176// AND 1177//===----------------------------------------------------------------------===// 1178 1179let Defs = [CC] in { 1180 // ANDs of a register. 1181 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1182 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1183 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1184 } 1185 1186 let isConvertibleToThreeAddress = 1 in { 1187 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1188 // The CC result only reflects the 16-bit field, not the full register. 1189 // 1190 // NIxMux expands to NI[LH]x, depending on the choice of register. 1191 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1192 Requires<[FeatureHighWord]>; 1193 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1194 Requires<[FeatureHighWord]>; 1195 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1196 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1197 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1198 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1199 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1200 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1201 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1202 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1203 1204 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1205 // The CC result only reflects the 32-bit field, which means we can 1206 // use it as a zero indicator for i32 operations but not otherwise. 1207 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1208 // Expands to NILF or NIHF, depending on the choice of register. 1209 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1210 Requires<[FeatureHighWord]>; 1211 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1212 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1213 } 1214 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1215 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1216 } 1217 1218 // ANDs of memory. 1219 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1220 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1221 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1222 } 1223 1224 // AND to memory 1225 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1226 1227 // Block AND. 1228 let mayLoad = 1, mayStore = 1 in 1229 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1230} 1231defm : RMWIByte<and, bdaddr12pair, NI>; 1232defm : RMWIByte<and, bdaddr20pair, NIY>; 1233 1234//===----------------------------------------------------------------------===// 1235// OR 1236//===----------------------------------------------------------------------===// 1237 1238let Defs = [CC] in { 1239 // ORs of a register. 1240 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1241 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1242 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1243 } 1244 1245 // ORs of a 16-bit immediate, leaving other bits unaffected. 1246 // The CC result only reflects the 16-bit field, not the full register. 1247 // 1248 // OIxMux expands to OI[LH]x, depending on the choice of register. 1249 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1250 Requires<[FeatureHighWord]>; 1251 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1252 Requires<[FeatureHighWord]>; 1253 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1254 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1255 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1256 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1257 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1258 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1259 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1260 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1261 1262 // ORs of a 32-bit immediate, leaving other bits unaffected. 1263 // The CC result only reflects the 32-bit field, which means we can 1264 // use it as a zero indicator for i32 operations but not otherwise. 1265 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1266 // Expands to OILF or OIHF, depending on the choice of register. 1267 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1268 Requires<[FeatureHighWord]>; 1269 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1270 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1271 } 1272 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1273 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1274 1275 // ORs of memory. 1276 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1277 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1278 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1279 } 1280 1281 // OR to memory 1282 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1283 1284 // Block OR. 1285 let mayLoad = 1, mayStore = 1 in 1286 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1287} 1288defm : RMWIByte<or, bdaddr12pair, OI>; 1289defm : RMWIByte<or, bdaddr20pair, OIY>; 1290 1291//===----------------------------------------------------------------------===// 1292// XOR 1293//===----------------------------------------------------------------------===// 1294 1295let Defs = [CC] in { 1296 // XORs of a register. 1297 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1298 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1299 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1300 } 1301 1302 // XORs of a 32-bit immediate, leaving other bits unaffected. 1303 // The CC result only reflects the 32-bit field, which means we can 1304 // use it as a zero indicator for i32 operations but not otherwise. 1305 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1306 // Expands to XILF or XIHF, depending on the choice of register. 1307 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1308 Requires<[FeatureHighWord]>; 1309 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1310 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1311 } 1312 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1313 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1314 1315 // XORs of memory. 1316 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1317 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1318 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1319 } 1320 1321 // XOR to memory 1322 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1323 1324 // Block XOR. 1325 let mayLoad = 1, mayStore = 1 in 1326 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1327} 1328defm : RMWIByte<xor, bdaddr12pair, XI>; 1329defm : RMWIByte<xor, bdaddr20pair, XIY>; 1330 1331//===----------------------------------------------------------------------===// 1332// Combined logical operations 1333//===----------------------------------------------------------------------===// 1334 1335let Predicates = [FeatureMiscellaneousExtensions3], 1336 Defs = [CC] in { 1337 // AND with complement. 1338 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1339 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1340 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1341 } 1342 1343 // OR with complement. 1344 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1345 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1346 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1347 } 1348 1349 // NAND. 1350 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1351 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1352 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1353 } 1354 1355 // NOR. 1356 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1357 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1358 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1359 } 1360 1361 // NXOR. 1362 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1363 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1364 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1365 } 1366} 1367 1368//===----------------------------------------------------------------------===// 1369// Multiplication 1370//===----------------------------------------------------------------------===// 1371 1372// Multiplication of a register, setting the condition code. We prefer these 1373// over MS(G)R if available, even though we cannot use the condition code, 1374// since they are three-operand instructions. 1375let Predicates = [FeatureMiscellaneousExtensions2], 1376 Defs = [CC], isCommutable = 1 in { 1377 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1378 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1379} 1380 1381// Multiplication of a register. 1382let isCommutable = 1 in { 1383 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1384 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1385} 1386def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1387defm : SXB<mul, GR64, MSGFR>; 1388 1389// Multiplication of a signed 16-bit immediate. 1390def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1391def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1392 1393// Multiplication of a signed 32-bit immediate. 1394def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1395def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1396 1397// Multiplication of memory. 1398defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1399defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1400def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1401 Requires<[FeatureMiscellaneousExtensions2]>; 1402def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1403def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1404 1405// Multiplication of memory, setting the condition code. 1406let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1407 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1408 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1409} 1410 1411// Multiplication of a register, producing two results. 1412def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1413def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1414 Requires<[FeatureMiscellaneousExtensions2]>; 1415def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1416def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1417 1418def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1419 (MGRK GR64:$src1, GR64:$src2)>; 1420def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1421 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1422 1423// Multiplication of memory, producing two results. 1424def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1425def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1426def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1427 Requires<[FeatureMiscellaneousExtensions2]>; 1428def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1429def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1430 1431def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1432 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1433def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1434 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1435 1436//===----------------------------------------------------------------------===// 1437// Division and remainder 1438//===----------------------------------------------------------------------===// 1439 1440let hasSideEffects = 1 in { // Do not speculatively execute. 1441 // Division and remainder, from registers. 1442 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1443 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1444 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1445 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1446 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1447 1448 // Division and remainder, from memory. 1449 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1450 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1451 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1452 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1453 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1454} 1455def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1456 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1457def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1458 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1459def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1460 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1461def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1462 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1463 1464def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1465 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1466 subreg_l32)), GR32:$src2)>; 1467def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1468 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1469 subreg_l32)), bdxaddr20only:$src2)>; 1470def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1471 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1472def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1473 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1474 1475//===----------------------------------------------------------------------===// 1476// Shifts 1477//===----------------------------------------------------------------------===// 1478 1479// Logical shift left. 1480defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1481def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1482def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1483 1484// Arithmetic shift left. 1485let Defs = [CC] in { 1486 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1487 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1488 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1489} 1490 1491// Logical shift right. 1492defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1493def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1494def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1495 1496// Arithmetic shift right. 1497let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1498 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1499 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1500 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1501} 1502 1503// Rotate left. 1504def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1505def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1506 1507// Rotate second operand left and inserted selected bits into first operand. 1508// These can act like 32-bit operands provided that the constant start and 1509// end bits (operands 2 and 3) are in the range [32, 64). 1510let Defs = [CC] in { 1511 let isCodeGenOnly = 1 in 1512 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1513 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1514 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1515} 1516 1517// On zEC12 we have a variant of RISBG that does not set CC. 1518let Predicates = [FeatureMiscellaneousExtensions] in 1519 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1520 1521// Forms of RISBG that only affect one word of the destination register. 1522// They do not set CC. 1523let Predicates = [FeatureHighWord] in { 1524 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1525 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1526 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1527 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1528 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1529 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1530 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1531} 1532 1533// Rotate second operand left and perform a logical operation with selected 1534// bits of the first operand. The CC result only describes the selected bits, 1535// so isn't useful for a full comparison against zero. 1536let Defs = [CC] in { 1537 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1538 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1539 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1540} 1541 1542//===----------------------------------------------------------------------===// 1543// Comparison 1544//===----------------------------------------------------------------------===// 1545 1546// Signed comparisons. We put these before the unsigned comparisons because 1547// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1548// of the unsigned forms do. 1549let Defs = [CC], CCValues = 0xE in { 1550 // Comparison with a register. 1551 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1552 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1553 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1554 1555 // Comparison with a high register. 1556 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1557 Requires<[FeatureHighWord]>; 1558 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1559 Requires<[FeatureHighWord]>; 1560 1561 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1562 // depending on the choice of register. 1563 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1564 Requires<[FeatureHighWord]>; 1565 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1566 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1567 1568 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1569 // depending on the choice of register. 1570 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1571 Requires<[FeatureHighWord]>; 1572 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1573 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1574 Requires<[FeatureHighWord]>; 1575 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1576 1577 // Comparison with memory. 1578 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1579 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1580 Requires<[FeatureHighWord]>; 1581 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1582 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1583 Requires<[FeatureHighWord]>; 1584 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1585 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1586 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1587 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1588 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1589 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1590 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1591 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1592 1593 // Comparison between memory and a signed 16-bit immediate. 1594 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1595 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1596 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1597} 1598defm : SXB<z_scmp, GR64, CGFR>; 1599 1600// Unsigned comparisons. 1601let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1602 // Comparison with a register. 1603 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1604 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1605 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1606 1607 // Comparison with a high register. 1608 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1609 Requires<[FeatureHighWord]>; 1610 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1611 Requires<[FeatureHighWord]>; 1612 1613 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1614 // or CLIH, depending on the choice of register. 1615 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1616 Requires<[FeatureHighWord]>; 1617 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1618 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1619 Requires<[FeatureHighWord]>; 1620 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1621 1622 // Comparison with memory. 1623 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1624 Requires<[FeatureHighWord]>; 1625 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1626 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1627 Requires<[FeatureHighWord]>; 1628 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1629 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1630 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1631 aligned_azextloadi16>; 1632 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1633 aligned_load>; 1634 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1635 aligned_azextloadi16>; 1636 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1637 aligned_azextloadi32>; 1638 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1639 aligned_load>; 1640 1641 // Comparison between memory and an unsigned 8-bit immediate. 1642 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1643 1644 // Comparison between memory and an unsigned 16-bit immediate. 1645 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1646 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1647 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1648} 1649defm : ZXB<z_ucmp, GR64, CLGFR>; 1650 1651// Memory-to-memory comparison. 1652let mayLoad = 1, Defs = [CC] in { 1653 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1654 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1655 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1656 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1657} 1658 1659// String comparison. 1660let mayLoad = 1, Defs = [CC] in 1661 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1662 1663// Test under mask. 1664let Defs = [CC] in { 1665 // TMxMux expands to TM[LH]x, depending on the choice of register. 1666 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1667 Requires<[FeatureHighWord]>; 1668 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1669 Requires<[FeatureHighWord]>; 1670 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1671 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1672 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1673 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1674 1675 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1676 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1677 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1678 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1679 1680 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1681} 1682 1683def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1684def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1685 1686// Compare logical characters under mask -- not (yet) used for codegen. 1687let Defs = [CC] in { 1688 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1689 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1690} 1691 1692//===----------------------------------------------------------------------===// 1693// Prefetch and execution hint 1694//===----------------------------------------------------------------------===// 1695 1696let mayLoad = 1, mayStore = 1 in { 1697 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1698 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1699} 1700 1701let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1702 // Branch Prediction Preload 1703 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1704 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1705 1706 // Next Instruction Access Intent 1707 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1708} 1709 1710//===----------------------------------------------------------------------===// 1711// Atomic operations 1712//===----------------------------------------------------------------------===// 1713 1714// A serialization instruction that acts as a barrier for all memory 1715// accesses, which expands to "bcr 14, 0". 1716let hasSideEffects = 1 in 1717def Serialize : Alias<2, (outs), (ins), []>; 1718 1719// A pseudo instruction that serves as a compiler barrier. 1720let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1721def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1722 1723let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1724 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1725 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1726 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1727 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1728 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1729 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1730 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1731 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1732 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1733 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1734} 1735 1736def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1737def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1738def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1739 1740def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1741def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1742let Predicates = [FeatureNoInterlockedAccess1] in { 1743 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1744 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1745 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1746 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1747 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1748 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1749} 1750 1751def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1752def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1753def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1754 1755def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1756def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1757let Predicates = [FeatureNoInterlockedAccess1] in { 1758 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1759 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1760 imm32ll16c>; 1761 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1762 imm32lh16c>; 1763 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1764 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1765 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1766 imm64ll16c>; 1767 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1768 imm64lh16c>; 1769 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1770 imm64hl16c>; 1771 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1772 imm64hh16c>; 1773 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1774 imm64lf32c>; 1775 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1776 imm64hf32c>; 1777} 1778 1779def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1780def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1781let Predicates = [FeatureNoInterlockedAccess1] in { 1782 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1783 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1784 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1785 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1786 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1787 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1788 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1789 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1790 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1791 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1792 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1793} 1794 1795def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1796def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1797let Predicates = [FeatureNoInterlockedAccess1] in { 1798 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1799 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1800 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1801 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1802 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1803} 1804 1805def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1806def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1807 imm32lh16c>; 1808def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1809def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1810 imm32ll16c>; 1811def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1812 imm32lh16c>; 1813def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1814def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1815def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1816 imm64ll16c>; 1817def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1818 imm64lh16c>; 1819def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1820 imm64hl16c>; 1821def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1822 imm64hh16c>; 1823def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1824 imm64lf32c>; 1825def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1826 imm64hf32c>; 1827 1828def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1829def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1830def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1831 1832def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1833def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1834def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1835 1836def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1837def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1838def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1839 1840def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1841def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1842def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1843 1844def ATOMIC_CMP_SWAPW 1845 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1846 ADDR32:$bitshift, ADDR32:$negbitshift, 1847 uimm32:$bitsize), 1848 [(set GR32:$dst, 1849 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1850 ADDR32:$bitshift, ADDR32:$negbitshift, 1851 uimm32:$bitsize))]> { 1852 let Defs = [CC]; 1853 let mayLoad = 1; 1854 let mayStore = 1; 1855 let usesCustomInserter = 1; 1856 let hasNoSchedulingInfo = 1; 1857} 1858 1859// Test and set. 1860let mayLoad = 1, Defs = [CC] in 1861 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1862 1863// Compare and swap. 1864let Defs = [CC] in { 1865 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1866 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1867} 1868 1869// Compare double and swap. 1870let Defs = [CC] in { 1871 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1872 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1873} 1874 1875// Compare and swap and store. 1876let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1877 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1878 1879// Perform locked operation. 1880let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1881 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1882 1883// Load/store pair from/to quadword. 1884def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1885def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1886 1887// Load pair disjoint. 1888let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1889 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1890 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1891} 1892 1893//===----------------------------------------------------------------------===// 1894// Translate and convert 1895//===----------------------------------------------------------------------===// 1896 1897let mayLoad = 1, mayStore = 1 in 1898 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1899 1900let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1901 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1902 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1903} 1904 1905let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1906 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1907 1908let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1909 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1910 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1911} 1912 1913let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1914 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1915 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1916 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1917 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1918} 1919 1920let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1921 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1922 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1923 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1924 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1925 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1926 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1927 1928 let isAsmParserOnly = 1 in { 1929 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1930 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1931 } 1932} 1933 1934//===----------------------------------------------------------------------===// 1935// Message-security assist 1936//===----------------------------------------------------------------------===// 1937 1938let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1939 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1940 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1941 1942 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1943 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1944 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1945 1946 let Predicates = [FeatureMessageSecurityAssist4] in { 1947 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1948 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1949 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1950 GR128, GR128, GR128>; 1951 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1952 } 1953 1954 let Predicates = [FeatureMessageSecurityAssist5] in 1955 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1956 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1957 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1958 1959 let Predicates = [FeatureMessageSecurityAssist8] in 1960 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1961 GR128, GR128, GR128>; 1962 1963 let Predicates = [FeatureMessageSecurityAssist9] in 1964 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1965} 1966 1967//===----------------------------------------------------------------------===// 1968// Guarded storage 1969//===----------------------------------------------------------------------===// 1970 1971// These instructions use and/or modify the guarded storage control 1972// registers, which we do not otherwise model, so they should have 1973// hasSideEffects. 1974let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1975 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1976 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1977 1978 let mayLoad = 1 in 1979 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1980 let mayStore = 1 in 1981 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1982} 1983 1984//===----------------------------------------------------------------------===// 1985// Decimal arithmetic 1986//===----------------------------------------------------------------------===// 1987 1988defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1989def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1990 1991defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1992def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1993 1994let mayLoad = 1, mayStore = 1 in { 1995 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1996 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1997 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1998 1999 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 2000 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 2001 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 2002 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 2003 let Defs = [CC] in { 2004 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 2005 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 2006 } 2007} 2008 2009let mayLoad = 1, mayStore = 1 in { 2010 let Defs = [CC] in { 2011 def AP : SideEffectBinarySSb<"ap", 0xFA>; 2012 def SP : SideEffectBinarySSb<"sp", 0xFB>; 2013 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 2014 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 2015 } 2016 def MP : SideEffectBinarySSb<"mp", 0xFC>; 2017 def DP : SideEffectBinarySSb<"dp", 0xFD>; 2018 let Defs = [CC] in { 2019 def ED : SideEffectBinarySSa<"ed", 0xDE>; 2020 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 2021 } 2022} 2023 2024let Defs = [CC] in { 2025 def CP : CompareSSb<"cp", 0xF9>; 2026 def TP : TestRSL<"tp", 0xEBC0>; 2027} 2028 2029//===----------------------------------------------------------------------===// 2030// Access registers 2031//===----------------------------------------------------------------------===// 2032 2033// Read a 32-bit access register into a GR32. As with all GR32 operations, 2034// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2035// when a 64-bit address is stored in a pair of access registers. 2036def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2037 2038// Set access register. 2039def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2040 2041// Copy access register. 2042def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2043 2044// Load address extended. 2045defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2046 2047// Load access multiple. 2048defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2049 2050// Store access multiple. 2051defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2052 2053//===----------------------------------------------------------------------===// 2054// Program mask and addressing mode 2055//===----------------------------------------------------------------------===// 2056 2057// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2058let Uses = [CC] in 2059 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2060 2061// Set CC and program mask from a register. 2062let hasSideEffects = 1, Defs = [CC] in 2063 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2064 2065// Branch and link - like BAS, but also extracts CC and program mask. 2066let isCall = 1, Uses = [CC], Defs = [CC] in { 2067 def BAL : CallRX<"bal", 0x45>; 2068 def BALR : CallRR<"balr", 0x05>; 2069} 2070 2071// Test addressing mode. 2072let Defs = [CC] in 2073 def TAM : SideEffectInherentE<"tam", 0x010B>; 2074 2075// Set addressing mode. 2076let hasSideEffects = 1 in { 2077 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2078 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2079 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2080} 2081 2082// Branch and set mode. Not really a call, but also sets an output register. 2083let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2084 def BSM : CallRR<"bsm", 0x0B>; 2085 2086// Branch and save and set mode. 2087let isCall = 1, Defs = [CC] in 2088 def BASSM : CallRR<"bassm", 0x0C>; 2089 2090//===----------------------------------------------------------------------===// 2091// Transactional execution 2092//===----------------------------------------------------------------------===// 2093 2094let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2095 // Transaction Begin 2096 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2097 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2098 let hasNoSchedulingInfo = 1 in 2099 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2100 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2101 int_s390_tbeginc, imm32zx16>; 2102 } 2103 2104 // Transaction End 2105 let Defs = [CC] in 2106 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2107 2108 // Transaction Abort 2109 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2110 hasSideEffects = 1 in 2111 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2112 2113 // Nontransactional Store 2114 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2115 2116 // Extract Transaction Nesting Depth 2117 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2118} 2119 2120//===----------------------------------------------------------------------===// 2121// Processor assist 2122//===----------------------------------------------------------------------===// 2123 2124let Predicates = [FeatureProcessorAssist] in { 2125 let hasSideEffects = 1 in 2126 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2127 def : Pat<(int_s390_ppa_txassist GR32:$src), 2128 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2129 zero_reg, 1)>; 2130} 2131 2132//===----------------------------------------------------------------------===// 2133// Miscellaneous Instructions. 2134//===----------------------------------------------------------------------===// 2135 2136// Find leftmost one, AKA count leading zeros. The instruction actually 2137// returns a pair of GR64s, the first giving the number of leading zeros 2138// and the second giving a copy of the source with the leftmost one bit 2139// cleared. We only use the first result here. 2140let Defs = [CC] in 2141 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2142def : Pat<(i64 (ctlz GR64:$src)), 2143 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2144 2145// Population count. Counts bits set per byte or doubleword. 2146let Predicates = [FeatureMiscellaneousExtensions3] in { 2147 let Defs = [CC] in 2148 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2149 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2150} 2151let Predicates = [FeaturePopulationCount], Defs = [CC] in 2152 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2153 2154// Search a block of memory for a character. 2155let mayLoad = 1, Defs = [CC] in 2156 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2157let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2158 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2159 2160// Compare until substring equal. 2161let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2162 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2163 2164// Compare and form codeword. 2165let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2166 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2167 2168// Update tree. 2169let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2170 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2171 def UPT : SideEffectInherentE<"upt", 0x0102>; 2172 2173// Checksum. 2174let mayLoad = 1, Defs = [CC] in 2175 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2176 2177// Compression call. 2178let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2179 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2180 2181// Sort lists. 2182let Predicates = [FeatureEnhancedSort], 2183 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2184 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2185 2186// Deflate conversion call. 2187let Predicates = [FeatureDeflateConversion], 2188 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2189 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2190 GR128, GR128, GR64>; 2191 2192// NNPA. 2193let Predicates = [FeatureNNPAssist], 2194 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2195 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2196 2197// Execute. 2198let hasSideEffects = 1 in { 2199 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2200 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2201 let hasNoSchedulingInfo = 1 in 2202 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2203 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2204 []>; 2205} 2206 2207//===----------------------------------------------------------------------===// 2208// .insn directive instructions 2209//===----------------------------------------------------------------------===// 2210 2211let isCodeGenOnly = 1, hasSideEffects = 1 in { 2212 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2213 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2214 imm32sx16:$I2), 2215 ".insn ri,$enc,$R1,$I2", []>; 2216 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2217 AnyReg:$R3, brtarget16:$I2), 2218 ".insn rie,$enc,$R1,$R3,$I2", []>; 2219 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2220 brtarget32:$I2), 2221 ".insn ril,$enc,$R1,$I2", []>; 2222 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2223 uimm32:$I2), 2224 ".insn rilu,$enc,$R1,$I2", []>; 2225 def InsnRIS : DirectiveInsnRIS<(outs), 2226 (ins imm64zx48:$enc, AnyReg:$R1, 2227 imm32sx8:$I2, imm32zx4:$M3, 2228 bdaddr12only:$BD4), 2229 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2230 def InsnRR : DirectiveInsnRR<(outs), 2231 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2232 ".insn rr,$enc,$R1,$R2", []>; 2233 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2234 AnyReg:$R1, AnyReg:$R2), 2235 ".insn rre,$enc,$R1,$R2", []>; 2236 def InsnRRF : DirectiveInsnRRF<(outs), 2237 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2238 AnyReg:$R3, imm32zx4:$M4), 2239 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2240 def InsnRRS : DirectiveInsnRRS<(outs), 2241 (ins imm64zx48:$enc, AnyReg:$R1, 2242 AnyReg:$R2, imm32zx4:$M3, 2243 bdaddr12only:$BD4), 2244 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2245 def InsnRS : DirectiveInsnRS<(outs), 2246 (ins imm64zx32:$enc, AnyReg:$R1, 2247 AnyReg:$R3, bdaddr12only:$BD2), 2248 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2249 def InsnRSE : DirectiveInsnRSE<(outs), 2250 (ins imm64zx48:$enc, AnyReg:$R1, 2251 AnyReg:$R3, bdaddr12only:$BD2), 2252 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2253 def InsnRSI : DirectiveInsnRSI<(outs), 2254 (ins imm64zx48:$enc, AnyReg:$R1, 2255 AnyReg:$R3, brtarget16:$RI2), 2256 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2257 def InsnRSY : DirectiveInsnRSY<(outs), 2258 (ins imm64zx48:$enc, AnyReg:$R1, 2259 AnyReg:$R3, bdaddr20only:$BD2), 2260 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2261 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2262 bdxaddr12only:$XBD2), 2263 ".insn rx,$enc,$R1,$XBD2", []>; 2264 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2265 bdxaddr12only:$XBD2), 2266 ".insn rxe,$enc,$R1,$XBD2", []>; 2267 def InsnRXF : DirectiveInsnRXF<(outs), 2268 (ins imm64zx48:$enc, AnyReg:$R1, 2269 AnyReg:$R3, bdxaddr12only:$XBD2), 2270 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2271 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2272 bdxaddr20only:$XBD2), 2273 ".insn rxy,$enc,$R1,$XBD2", []>; 2274 def InsnS : DirectiveInsnS<(outs), 2275 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2276 ".insn s,$enc,$BD2", []>; 2277 def InsnSI : DirectiveInsnSI<(outs), 2278 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2279 imm32sx8:$I2), 2280 ".insn si,$enc,$BD1,$I2", []>; 2281 def InsnSIY : DirectiveInsnSIY<(outs), 2282 (ins imm64zx48:$enc, 2283 bdaddr20only:$BD1, imm32zx8:$I2), 2284 ".insn siy,$enc,$BD1,$I2", []>; 2285 def InsnSIL : DirectiveInsnSIL<(outs), 2286 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2287 imm32zx16:$I2), 2288 ".insn sil,$enc,$BD1,$I2", []>; 2289 def InsnSS : DirectiveInsnSS<(outs), 2290 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2291 bdaddr12only:$BD2, AnyReg:$R3), 2292 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2293 def InsnSSE : DirectiveInsnSSE<(outs), 2294 (ins imm64zx48:$enc, 2295 bdaddr12only:$BD1,bdaddr12only:$BD2), 2296 ".insn sse,$enc,$BD1,$BD2", []>; 2297 def InsnSSF : DirectiveInsnSSF<(outs), 2298 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2299 bdaddr12only:$BD2, AnyReg:$R3), 2300 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2301 def InsnVRI : DirectiveInsnVRI<(outs), 2302 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2303 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2304 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2305 def InsnVRR : DirectiveInsnVRR<(outs), 2306 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2307 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2308 imm32zx4:$M6), 2309 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2310 def InsnVRS : DirectiveInsnVRS<(outs), 2311 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2312 bdaddr12only:$BD2, imm32zx4:$M4), 2313 ".insn vrs,$enc,$BD2,$M4", []>; 2314 def InsnVRV : DirectiveInsnVRV<(outs), 2315 (ins imm64zx48:$enc, VR128:$V1, 2316 bdvaddr12only:$VBD2, imm32zx4:$M3), 2317 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2318 def InsnVRX : DirectiveInsnVRX<(outs), 2319 (ins imm64zx48:$enc, VR128:$V1, 2320 bdxaddr12only:$XBD2, imm32zx4:$M3), 2321 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2322 def InsnVSI : DirectiveInsnVSI<(outs), 2323 (ins imm64zx48:$enc, VR128:$V1, 2324 bdaddr12only:$BD2, imm32zx8:$I3), 2325 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2326} 2327 2328//===----------------------------------------------------------------------===// 2329// Peepholes. 2330//===----------------------------------------------------------------------===// 2331 2332// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2333// equivalent to (and (xor x, -1), y) 2334def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2335 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2336 2337// Shift/rotate instructions only use the last 6 bits of the second operand 2338// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2339// last 16 bits. 2340// Complexity is added so that we match this before we match NILF on the AND 2341// operation alone. 2342let AddedComplexity = 4 in { 2343 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2344 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2345 2346 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2347 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2348 2349 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2350 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2351 2352 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2353 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2354 2355 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2356 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2357 2358 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2359 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2360 2361 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2362 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2363 2364 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2365 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2366} 2367 2368// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2369// use the last 6 bits of the second operand register (making it modulo 64). 2370let AddedComplexity = 4 in { 2371 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2372 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2373 2374 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2375 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2376 2377 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2378 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2379 2380 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2381 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2382} 2383 2384// Peepholes for turning scalar operations into block operations. The length 2385// is given as one less for these pseudos. 2386defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2387defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2388defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2389defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2390defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2391defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2392defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2393 2394//===----------------------------------------------------------------------===// 2395// Mnemonic Aliases 2396//===----------------------------------------------------------------------===// 2397 2398def JCT : MnemonicAlias<"jct", "brct">; 2399def JCTG : MnemonicAlias<"jctg", "brctg">; 2400def JAS : MnemonicAlias<"jas", "bras">; 2401def JASL : MnemonicAlias<"jasl", "brasl">; 2402def JXH : MnemonicAlias<"jxh", "brxh">; 2403def JXLE : MnemonicAlias<"jxle", "brxle">; 2404def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2405def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2406 2407def BRU : MnemonicAlias<"bru", "j">; 2408def BRUL : MnemonicAlias<"brul", "jg", "att">; 2409def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2410 2411foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2412 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2413 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2414 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2415 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2416} 2417