1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// These pseudos carry values needed to compute the MaxcallFrameSize of the 17// function. The callseq_start node requires the hasSideEffects flag. 18let usesCustomInserter = 1, hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1, 46 hasSideEffects = 1 in 47 def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>; 48 49//===----------------------------------------------------------------------===// 50// Branch instructions 51//===----------------------------------------------------------------------===// 52 53// Conditional branches. 54let isBranch = 1, isTerminator = 1, Uses = [CC] in { 55 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 56 // with the condition-code mask being the first operand. It seems friendlier 57 // to use mnemonic forms like JE and JLH when writing out the assembly though. 58 let isCodeGenOnly = 1 in { 59 // An assembler extended mnemonic for BRC. 60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 61 // An assembler extended mnemonic for BRCL. (The extension is "G" 62 // rather than "L" because "JL" is "Jump if Less".) 63 def BRCL : CondBranchRIL<"jg#", 0xC04>; 64 let isIndirectBranch = 1 in { 65 def BC : CondBranchRX<"b#", 0x47>; 66 def BCR : CondBranchRR<"b#r", 0x07>; 67 def BIC : CondBranchRXY<"bi#", 0xe347>, 68 Requires<[FeatureMiscellaneousExtensions2]>; 69 } 70 } 71 72 // Allow using the raw forms directly from the assembler (and occasional 73 // special code generation needs) as well. 74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 76 let isIndirectBranch = 1 in { 77 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 79 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 80 Requires<[FeatureMiscellaneousExtensions2]>; 81 } 82 83 // Define AsmParser extended mnemonics for each general condition-code mask 84 // (integer or floating-point) 85 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 86 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 87 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 88 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 89 let isIndirectBranch = 1 in { 90 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 91 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 92 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 93 Requires<[FeatureMiscellaneousExtensions2]>; 94 } 95 } 96} 97 98// Unconditional branches. These are in fact simply variants of the 99// conditional branches with the condition mask set to "always". 100let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 101 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 102 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 103 let isIndirectBranch = 1 in { 104 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 105 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 106 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 107 Requires<[FeatureMiscellaneousExtensions2]>; 108 } 109} 110 111// NOPs. These are again variants of the conditional branches, with the 112// condition mask set to "never". NOP_bare can't be an InstAlias since it 113// would need R0D hard coded which is not part of ADDR64BitRegClass. 114def NOP : NeverCondBranchRX<"nop", 0x47>; 115let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, X2 = 0, B2 = 0, D2 = 0 in 116 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 117def NOPR : NeverCondBranchRR<"nopr", 0x07>; 118def NOPR_bare : InstAlias<"nopr", (NOPR R0D), 0>; 119 120// An alias of BRC 0, label 121def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 122 123// An alias of BRCL 0, label 124// jgnop on att ; jlnop on hlasm 125def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 126 127// Fused compare-and-branch instructions. 128// 129// These instructions do not use or clobber the condition codes. 130// We nevertheless pretend that the relative compare-and-branch 131// instructions clobber CC, so that we can lower them to separate 132// comparisons and BRCLs if the branch ends up being out of range. 133let isBranch = 1, isTerminator = 1 in { 134 // As for normal branches, we handle these instructions internally in 135 // their raw CRJ-like form, but use assembly macros like CRJE when writing 136 // them out. Using the *Pair multiclasses, we also create the raw forms. 137 let Defs = [CC] in { 138 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 139 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 140 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 141 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 142 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 143 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 144 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 145 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 146 } 147 let isIndirectBranch = 1 in { 148 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 149 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 150 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 151 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 152 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 153 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 154 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 155 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 156 } 157 158 // Define AsmParser mnemonics for each integer condition-code mask. 159 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 160 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 161 let Defs = [CC] in { 162 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 163 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 164 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 165 imm32sx8>; 166 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 167 imm64sx8>; 168 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 169 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 170 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 171 imm32zx8>; 172 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 173 imm64zx8>; 174 } 175 let isIndirectBranch = 1 in { 176 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 177 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 178 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 179 imm32sx8>; 180 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 181 imm64sx8>; 182 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 183 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 184 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 185 imm32zx8>; 186 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 187 imm64zx8>; 188 } 189 } 190} 191 192// Decrement a register and branch if it is nonzero. These don't clobber CC, 193// but we might need to split long relative branches into sequences that do. 194let isBranch = 1, isTerminator = 1 in { 195 let Defs = [CC] in { 196 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 197 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 198 } 199 // This doesn't need to clobber CC since we never need to split it. 200 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 201 Requires<[FeatureHighWord]>; 202 203 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 204 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 205 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 206 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 207} 208 209let isBranch = 1, isTerminator = 1 in { 210 let Defs = [CC] in { 211 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 212 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 213 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 214 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 215 } 216 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 217 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 218 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 219 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 220} 221 222//===----------------------------------------------------------------------===// 223// Trap instructions 224//===----------------------------------------------------------------------===// 225 226// Unconditional trap. 227let hasCtrlDep = 1, hasSideEffects = 1 in 228 def Trap : Alias<4, (outs), (ins), [(trap)]>; 229 230// Conditional trap. 231let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 232 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 233 234// Fused compare-and-trap instructions. 235let hasCtrlDep = 1, hasSideEffects = 1 in { 236 // These patterns work the same way as for compare-and-branch. 237 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 238 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 239 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 240 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 241 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 242 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 243 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 244 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 245 let Predicates = [FeatureMiscellaneousExtensions] in { 246 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 247 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 248 } 249 250 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 251 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 252 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 253 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 254 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 255 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 256 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 257 imm32sx16>; 258 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 259 imm64sx16>; 260 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 261 imm32zx16>; 262 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 263 imm64zx16>; 264 let Predicates = [FeatureMiscellaneousExtensions] in { 265 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 266 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 267 } 268 } 269} 270 271//===----------------------------------------------------------------------===// 272// Call and return instructions 273//===----------------------------------------------------------------------===// 274 275// Define the general form of the call instructions for the asm parser. 276// These instructions don't hard-code %r14 as the return address register. 277let isCall = 1, Defs = [CC] in { 278 def BRAS : CallRI <"bras", 0xA75>; 279 def BRASL : CallRIL<"brasl", 0xC05>; 280 def BAS : CallRX <"bas", 0x4D>; 281 def BASR : CallRR <"basr", 0x0D>; 282} 283 284// A symbol in the ADA (z/OS only). 285def adasym : Operand<i64>; 286 287// z/OS XPLINK 288let Predicates = [IsTargetXPLINK64] in { 289 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 290 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 291 [(z_call pcrel32:$I2)]>; 292 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 293 [(z_call ADDR64:$R2)]>; 294 } 295 296 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in { 297 def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>; 298 } 299 300 let hasNoSchedulingInfo = 1, Defs = [CC] in { 301 def ADA_ENTRY : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 302 ADDR64:$ADA, imm64:$Offset), 303 [(set i64:$Reg, (z_ada_entry i64:$addr, 304 i64:$ADA, i64:$Offset))]>; 305 } 306 let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in { 307 def ADA_ENTRY_VALUE : Alias<12, (outs GR64:$Reg), (ins adasym:$addr, 308 ADDR64:$ADA, imm64:$Offset), 309 [(set i64:$Reg, (z_load (z_ada_entry 310 iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>; 311 } 312} 313 314// Regular calls. 315// z/Linux ELF 316let Predicates = [IsTargetELF] in { 317 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 318 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 319 [(z_call pcrel32:$I2)]>; 320 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 321 [(z_call ADDR64:$R2)]>; 322 } 323 324 // TLS calls. These will be lowered into a call to __tls_get_offset, 325 // with an extra relocation specifying the TLS symbol. 326 let isCall = 1, Defs = [R14D, CC] in { 327 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 328 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 329 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 330 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 331 } 332} 333 334// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 335// R1 used for ELF 336let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 337 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 338 [(z_sibcall pcrel32:$I2)]>; 339 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 340 [(z_sibcall ADDR64:$R2)]>; 341} 342 343// Conditional sibling calls. 344let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 345 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 346 pcrel32:$I2), []>; 347 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 348 ADDR64:$R2), []>; 349} 350 351// Fused compare and conditional sibling calls. 352let isCall = 1, isTerminator = 1, isReturn = 1 in { 353 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 354 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 355 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 356 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 357 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 358 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 359 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 360 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 361} 362 363let Predicates = [IsTargetXPLINK64] in { 364 // A return instruction (b 2(%r7)). 365 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 366 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retglue)]>; 367 368 // A conditional return instruction (bc <cond>, 2(%r7)). 369 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 370 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 371} 372 373let Predicates = [IsTargetELF] in { 374 // A return instruction (br %r14). 375 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 376 def Return : Alias<2, (outs), (ins), [(z_retglue)]>; 377 378 // A conditional return instruction (bcr <cond>, %r14). 379 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 380 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 381} 382 383// Fused compare and conditional returns. 384let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 385 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 386 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 387 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 388 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 389 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 390 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 391 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 392 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 393} 394 395//===----------------------------------------------------------------------===// 396// Select instructions 397//===----------------------------------------------------------------------===// 398 399def Select32 : SelectWrapper<i32, GR32>, 400 Requires<[FeatureNoLoadStoreOnCond]>; 401def Select64 : SelectWrapper<i64, GR64>, 402 Requires<[FeatureNoLoadStoreOnCond]>; 403 404// We don't define 32-bit Mux stores if we don't have STOCFH, because the 405// low-only STOC should then always be used if possible. 406defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 407 nonvolatile_anyextloadi8, bdxaddr20only>, 408 Requires<[FeatureHighWord]>; 409defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 410 nonvolatile_anyextloadi16, bdxaddr20only>, 411 Requires<[FeatureHighWord]>; 412defm CondStore32Mux : CondStores<GRX32, simple_store, 413 simple_load, bdxaddr20only>, 414 Requires<[FeatureLoadStoreOnCond2]>; 415defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 416 nonvolatile_anyextloadi8, bdxaddr20only>; 417defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 418 nonvolatile_anyextloadi16, bdxaddr20only>; 419defm CondStore32 : CondStores<GR32, simple_store, 420 simple_load, bdxaddr20only>; 421 422defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 423 nonvolatile_anyextloadi8, bdxaddr20only>; 424defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 425 nonvolatile_anyextloadi16, bdxaddr20only>; 426defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 427 nonvolatile_anyextloadi32, bdxaddr20only>; 428defm CondStore64 : CondStores<GR64, simple_store, 429 simple_load, bdxaddr20only>; 430 431//===----------------------------------------------------------------------===// 432// Move instructions 433//===----------------------------------------------------------------------===// 434 435// Register moves. 436def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 437def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 438 439let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 440 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 441 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 442} 443 444let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 445 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 446 447// Immediate moves. 448let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 449 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 450 // deopending on the choice of register. 451 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 452 Requires<[FeatureHighWord]>; 453 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 454 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 455 456 // Other 16-bit immediates. 457 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 458 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 459 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 460 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 461 462 // 32-bit immediates. 463 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 464 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 465 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 466} 467def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>; 468def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>; 469 470// Register loads. 471let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 472 // Expands to L, LY or LFH, depending on the choice of register. 473 def LMux : UnaryRXYPseudo<"l", z_load, GRX32, 4>, 474 Requires<[FeatureHighWord]>; 475 defm L : UnaryRXPair<"l", 0x58, 0xE358, z_load, GR32, 4>; 476 def LFH : UnaryRXY<"lfh", 0xE3CA, z_load, GRH32, 4>, 477 Requires<[FeatureHighWord]>; 478 def LG : UnaryRXY<"lg", 0xE304, z_load, GR64, 8>; 479 480 // These instructions are split after register allocation, so we don't 481 // want a custom inserter. 482 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 483 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 484 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 485 } 486} 487let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 488 def LT : UnaryRXY<"lt", 0xE312, z_load, GR32, 4>; 489 def LTG : UnaryRXY<"ltg", 0xE302, z_load, GR64, 8>; 490} 491 492let canFoldAsLoad = 1 in { 493 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_z_load, GR32>; 494 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_z_load, GR64>; 495} 496 497// Load and zero rightmost byte. 498let Predicates = [FeatureLoadAndZeroRightmostByte] in { 499 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 500 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 501 def : Pat<(and (i32 (z_load bdxaddr20only:$src)), 0xffffff00), 502 (LZRF bdxaddr20only:$src)>; 503 def : Pat<(and (i64 (z_load bdxaddr20only:$src)), 0xffffffffffffff00), 504 (LZRG bdxaddr20only:$src)>; 505} 506 507// Load and trap. 508let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 509 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 510 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 511 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 512} 513 514// Register stores. 515let SimpleBDXStore = 1, mayStore = 1 in { 516 // Expands to ST, STY or STFH, depending on the choice of register. 517 def STMux : StoreRXYPseudo<store, GRX32, 4>, 518 Requires<[FeatureHighWord]>; 519 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 520 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 521 Requires<[FeatureHighWord]>; 522 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 523 524 // These instructions are split after register allocation, so we don't 525 // want a custom inserter. 526 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 527 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 528 [(store GR128:$src, bdxaddr20only128:$dst)]>; 529 } 530} 531def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 532def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 533 534// 8-bit immediate stores to 8-bit fields. 535defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 536 537// 16-bit immediate stores to 16-, 32- or 64-bit fields. 538def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 539def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 540def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 541 542// Memory-to-memory moves. 543let mayLoad = 1, mayStore = 1 in 544 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 545let mayLoad = 1, mayStore = 1, Defs = [CC] in { 546 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 547 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 548 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 549} 550 551// Memset[Length][Byte] pseudos. 552def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 553def MemsetImmReg : MemsetPseudo<imm64, GR32>; 554def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 555def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 556 557// Move right. 558let Predicates = [FeatureMiscellaneousExtensions3], 559 mayLoad = 1, mayStore = 1, Uses = [R0L] in 560 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 561 562// String moves. 563let mayLoad = 1, mayStore = 1, Defs = [CC] in 564 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 565 566//===----------------------------------------------------------------------===// 567// Conditional move instructions 568//===----------------------------------------------------------------------===// 569 570let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 571 // Select. 572 let isCommutable = 1 in { 573 // Expands to SELR or SELFHR or a branch-and-move sequence, 574 // depending on the choice of registers. 575 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 576 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 577 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 578 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 579 } 580 581 // Define AsmParser extended mnemonics for each general condition-code mask. 582 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 583 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 584 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 585 GR32, GR32, GR32>; 586 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 587 GRH32, GRH32, GRH32>; 588 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 589 GR64, GR64, GR64>; 590 } 591} 592 593let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 594 // Load immediate on condition. Matched via DAG pattern and created 595 // by the PeepholeOptimizer via FoldImmediate. 596 597 // Expands to LOCHI or LOCHHI, depending on the choice of register. 598 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 599 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 600 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 601 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 602 603 // Move register on condition. Matched via DAG pattern and 604 // created by early if-conversion. 605 let isCommutable = 1 in { 606 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 607 // depending on the choice of registers. 608 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 609 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 610 } 611 612 // Load on condition. Matched via DAG pattern. 613 // Expands to LOC or LOCFH, depending on the choice of register. 614 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 615 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 616 617 // Store on condition. Expanded from CondStore* pseudos. 618 // Expands to STOC or STOCFH, depending on the choice of register. 619 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 620 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 621 622 // Define AsmParser extended mnemonics for each general condition-code mask. 623 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 624 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 625 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 626 imm32sx16>; 627 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 628 imm64sx16>; 629 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 630 imm32sx16>; 631 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 632 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 633 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 634 } 635} 636 637let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 638 // Move register on condition. Matched via DAG pattern and 639 // created by early if-conversion. 640 let isCommutable = 1 in { 641 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 642 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 643 } 644 645 // Load on condition. Matched via DAG pattern. 646 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 647 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 648 649 // Store on condition. Expanded from CondStore* pseudos. 650 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 651 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 652 653 // Define AsmParser extended mnemonics for each general condition-code mask. 654 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 655 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 656 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 657 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 658 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 659 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 660 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 661 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 662 } 663} 664//===----------------------------------------------------------------------===// 665// Sign extensions 666//===----------------------------------------------------------------------===// 667// 668// Note that putting these before zero extensions mean that we will prefer 669// them for anyextload*. There's not really much to choose between the two 670// either way, but signed-extending loads have a short LH and a long LHY, 671// while zero-extending loads have only the long LLH. 672// 673//===----------------------------------------------------------------------===// 674 675// 32-bit extensions from registers. 676def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 677def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 678 679// 64-bit extensions from registers. 680def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 681def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 682def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 683 684let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 685 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 686 687// Match 32-to-64-bit sign extensions in which the source is already 688// in a 64-bit register. 689def : Pat<(sext_inreg GR64:$src, i32), 690 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 691 692// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 693// depending on the choice of register. 694def LBMux : UnaryRXYPseudo<"lb", z_asextloadi8, GRX32, 1>, 695 Requires<[FeatureHighWord]>; 696def LB : UnaryRXY<"lb", 0xE376, z_asextloadi8, GR32, 1>; 697def LBH : UnaryRXY<"lbh", 0xE3C0, z_asextloadi8, GRH32, 1>, 698 Requires<[FeatureHighWord]>; 699 700// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 701// depending on the choice of register. 702def LHMux : UnaryRXYPseudo<"lh", z_asextloadi16, GRX32, 2>, 703 Requires<[FeatureHighWord]>; 704defm LH : UnaryRXPair<"lh", 0x48, 0xE378, z_asextloadi16, GR32, 2>; 705def LHH : UnaryRXY<"lhh", 0xE3C4, z_asextloadi16, GRH32, 2>, 706 Requires<[FeatureHighWord]>; 707def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_z_asextloadi16, GR32>; 708 709// 64-bit extensions from memory. 710def LGB : UnaryRXY<"lgb", 0xE377, z_asextloadi8, GR64, 1>; 711def LGH : UnaryRXY<"lgh", 0xE315, z_asextloadi16, GR64, 2>; 712def LGF : UnaryRXY<"lgf", 0xE314, z_asextloadi32, GR64, 4>; 713def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_z_asextloadi16, GR64>; 714def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_z_asextloadi32, GR64>; 715let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 716 def LTGF : UnaryRXY<"ltgf", 0xE332, z_asextloadi32, GR64, 4>; 717 718//===----------------------------------------------------------------------===// 719// Zero extensions 720//===----------------------------------------------------------------------===// 721 722// 32-bit extensions from registers. 723 724// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 725def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 726 Requires<[FeatureHighWord]>; 727def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 728// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 729def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 730 Requires<[FeatureHighWord]>; 731def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 732 733// 64-bit extensions from registers. 734def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 735def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 736def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 737 738// Match 32-to-64-bit zero extensions in which the source is already 739// in a 64-bit register. 740def : Pat<(and GR64:$src, 0xffffffff), 741 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 742 743// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 744// depending on the choice of register. 745def LLCMux : UnaryRXYPseudo<"llc", z_azextloadi8, GRX32, 1>, 746 Requires<[FeatureHighWord]>; 747def LLC : UnaryRXY<"llc", 0xE394, z_azextloadi8, GR32, 1>; 748def LLCH : UnaryRXY<"llch", 0xE3C2, z_azextloadi8, GRH32, 1>, 749 Requires<[FeatureHighWord]>; 750 751// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 752// depending on the choice of register. 753def LLHMux : UnaryRXYPseudo<"llh", z_azextloadi16, GRX32, 2>, 754 Requires<[FeatureHighWord]>; 755def LLH : UnaryRXY<"llh", 0xE395, z_azextloadi16, GR32, 2>; 756def LLHH : UnaryRXY<"llhh", 0xE3C6, z_azextloadi16, GRH32, 2>, 757 Requires<[FeatureHighWord]>; 758def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_z_azextloadi16, GR32>; 759 760// 64-bit extensions from memory. 761def LLGC : UnaryRXY<"llgc", 0xE390, z_azextloadi8, GR64, 1>; 762def LLGH : UnaryRXY<"llgh", 0xE391, z_azextloadi16, GR64, 2>; 763def LLGF : UnaryRXY<"llgf", 0xE316, z_azextloadi32, GR64, 4>; 764def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_z_azextloadi16, GR64>; 765def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_z_azextloadi32, GR64>; 766 767// 31-to-64-bit zero extensions. 768def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 769def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 770def : Pat<(and GR64:$src, 0x7fffffff), 771 (LLGTR GR64:$src)>; 772def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 773 (LLGT bdxaddr20only:$src)>; 774 775// Load and zero rightmost byte. 776let Predicates = [FeatureLoadAndZeroRightmostByte] in { 777 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 778 def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0xffffff00), 779 (LLZRGF bdxaddr20only:$src)>; 780} 781 782// Load and trap. 783let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 784 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 785 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 786} 787 788// Extend GR64s to GR128s. 789let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 790 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 791 792//===----------------------------------------------------------------------===// 793// "Any" extensions 794//===----------------------------------------------------------------------===// 795 796// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 797def : Pat<(i64 (anyext GR32:$src)), 798 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 799 800// Extend GR64s to GR128s. 801let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 802 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 803 804//===----------------------------------------------------------------------===// 805// Truncations 806//===----------------------------------------------------------------------===// 807 808// Truncations of 64-bit registers to 32-bit registers. 809def : Pat<(i32 (trunc GR64:$src)), 810 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 811 812// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 813// STC, STCY or STCH, depending on the choice of register. 814def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 815 Requires<[FeatureHighWord]>; 816defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 817def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 818 Requires<[FeatureHighWord]>; 819 820// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 821// STH, STHY or STHH, depending on the choice of register. 822def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 823 Requires<[FeatureHighWord]>; 824defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 825def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 826 Requires<[FeatureHighWord]>; 827def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 828 829// Truncations of 64-bit registers to memory. 830defm : StoreGR64Pair<STC, STCY, truncstorei8>; 831defm : StoreGR64Pair<STH, STHY, truncstorei16>; 832def : StoreGR64PC<STHRL, aligned_truncstorei16>; 833defm : StoreGR64Pair<ST, STY, truncstorei32>; 834def : StoreGR64PC<STRL, aligned_truncstorei32>; 835 836// Store characters under mask -- not (yet) used for codegen. 837defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 838def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 839 840//===----------------------------------------------------------------------===// 841// Multi-register moves 842//===----------------------------------------------------------------------===// 843 844// Multi-register loads. 845defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 846def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 847def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 848def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 849 850// Multi-register stores. 851defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 852def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 853def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 854 855//===----------------------------------------------------------------------===// 856// Byte swaps 857//===----------------------------------------------------------------------===// 858 859// Byte-swapping register moves. 860def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 861def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 862 863// Byte-swapping loads. 864def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 865def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 866def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 867 868// Byte-swapping stores. 869def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 870def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 871def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 872 873// Byte-swapping memory-to-memory moves. 874let mayLoad = 1, mayStore = 1 in 875 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 876 877//===----------------------------------------------------------------------===// 878// Load address instructions 879//===----------------------------------------------------------------------===// 880 881// Load BDX-style addresses. 882let isAsCheapAsAMove = 1, isReMaterializable = 1 in 883 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 884 885// Load a PC-relative address. There's no version of this instruction 886// with a 16-bit offset, so there's no relaxation. 887let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 888 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 889 890// Load the Global Offset Table address. This will be lowered into a 891// larl $R1, _GLOBAL_OFFSET_TABLE_ 892// instruction. 893def GOT : Alias<6, (outs GR64:$R1), (ins), 894 [(set GR64:$R1, (global_offset_table))]>; 895 896//===----------------------------------------------------------------------===// 897// Absolute and Negation 898//===----------------------------------------------------------------------===// 899 900let Defs = [CC] in { 901 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 902 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 903 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 904 } 905 let CCValues = 0xE, CompareZeroCCMask = 0xE in 906 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 907} 908defm : SXU<abs, LPGFR>; 909 910let Defs = [CC] in { 911 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 912 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 913 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 914 } 915 let CCValues = 0xE, CompareZeroCCMask = 0xE in 916 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 917} 918defm : SXU<z_inegabs, LNGFR>; 919 920let Defs = [CC] in { 921 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 922 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 923 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 924 } 925 let CCValues = 0xE, CompareZeroCCMask = 0xE in 926 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 927} 928defm : SXU<ineg, LCGFR>; 929 930//===----------------------------------------------------------------------===// 931// Insertion 932//===----------------------------------------------------------------------===// 933 934let isCodeGenOnly = 1 in 935 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, z_azextloadi8, 1>; 936defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, z_azextloadi8, 1>; 937 938defm : InsertMem<"inserti8", IC32, GR32, z_azextloadi8, bdxaddr12pair>; 939defm : InsertMem<"inserti8", IC32Y, GR32, z_azextloadi8, bdxaddr20pair>; 940 941defm : InsertMem<"inserti8", IC, GR64, z_azextloadi8, bdxaddr12pair>; 942defm : InsertMem<"inserti8", ICY, GR64, z_azextloadi8, bdxaddr20pair>; 943 944// Insert characters under mask -- not (yet) used for codegen. 945let Defs = [CC] in { 946 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 947 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 948} 949 950// Insertions of a 16-bit immediate, leaving other bits unaffected. 951// We don't have or_as_insert equivalents of these operations because 952// OI is available instead. 953// 954// IIxMux expands to II[LH]x, depending on the choice of register. 955def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 956 Requires<[FeatureHighWord]>; 957def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 958 Requires<[FeatureHighWord]>; 959def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 960def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 961def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 962def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 963def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 964def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 965def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 966def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 967 968// ...likewise for 32-bit immediates. For GR32s this is a general 969// full-width move. (We use IILF rather than something like LLILF 970// for 32-bit moves because IILF leaves the upper 32 bits of the 971// GR64 unchanged.) 972let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 973 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 974 Requires<[FeatureHighWord]>; 975 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 976 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 977} 978def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>; 979def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 980def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 981 982// An alternative model of inserthf, with the first operand being 983// a zero-extended value. 984def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 985 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 986 imm64hf32:$imm)>; 987 988//===----------------------------------------------------------------------===// 989// Addition 990//===----------------------------------------------------------------------===// 991 992// Addition producing a signed overflow flag. 993let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 994 // Addition of a register. 995 let isCommutable = 1 in { 996 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 997 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 998 } 999 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 1000 1001 // Addition to a high register. 1002 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 1003 Requires<[FeatureHighWord]>; 1004 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 1005 Requires<[FeatureHighWord]>; 1006 1007 // Addition of signed 16-bit immediates. 1008 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 1009 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 1010 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 1011 1012 // Addition of signed 32-bit immediates. 1013 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 1014 Requires<[FeatureHighWord]>; 1015 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 1016 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 1017 Requires<[FeatureHighWord]>; 1018 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 1019 1020 // Addition of memory. 1021 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, z_asextloadi16, 2>; 1022 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, z_load, 4>; 1023 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, z_asextloadi16, 2>, 1024 Requires<[FeatureMiscellaneousExtensions2]>; 1025 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, z_asextloadi32, 4>; 1026 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, z_load, 8>; 1027 1028 // Addition to memory. 1029 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 1030 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 1031} 1032defm : SXB<z_sadd, GR64, AGFR>; 1033 1034// Addition producing a carry. 1035let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 1036 // Addition of a register. 1037 let isCommutable = 1 in { 1038 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1039 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1040 } 1041 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1042 1043 // Addition to a high register. 1044 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1045 Requires<[FeatureHighWord]>; 1046 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1047 Requires<[FeatureHighWord]>; 1048 1049 // Addition of signed 16-bit immediates. 1050 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1051 Requires<[FeatureDistinctOps]>; 1052 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1053 Requires<[FeatureDistinctOps]>; 1054 1055 // Addition of unsigned 32-bit immediates. 1056 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1057 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1058 1059 // Addition of signed 32-bit immediates. 1060 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1061 Requires<[FeatureHighWord]>; 1062 1063 // Addition of memory. 1064 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, z_load, 4>; 1065 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, z_azextloadi32, 4>; 1066 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, z_load, 8>; 1067 1068 // Addition to memory. 1069 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1070 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1071} 1072defm : ZXB<z_uadd, GR64, ALGFR>; 1073 1074// Addition producing and using a carry. 1075let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1076 // Addition of a register. 1077 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1078 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1079 1080 // Addition of memory. 1081 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, z_load, 4>; 1082 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, z_load, 8>; 1083} 1084 1085// Addition that does not modify the condition code. 1086def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1087 Requires<[FeatureHighWord]>; 1088 1089 1090//===----------------------------------------------------------------------===// 1091// Subtraction 1092//===----------------------------------------------------------------------===// 1093 1094// Subtraction producing a signed overflow flag. 1095let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1096 CCIfNoSignedWrap = 1 in { 1097 // Subtraction of a register. 1098 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1099 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1100 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1101 1102 // Subtraction from a high register. 1103 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1104 Requires<[FeatureHighWord]>; 1105 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1106 Requires<[FeatureHighWord]>; 1107 1108 // Subtraction of memory. 1109 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, z_asextloadi16, 2>; 1110 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, z_load, 4>; 1111 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, z_asextloadi16, 2>, 1112 Requires<[FeatureMiscellaneousExtensions2]>; 1113 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, z_asextloadi32, 4>; 1114 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, z_load, 8>; 1115} 1116defm : SXB<z_ssub, GR64, SGFR>; 1117 1118// Subtracting an immediate is the same as adding the negated immediate. 1119let AddedComplexity = 1 in { 1120 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1121 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1122 Requires<[FeatureHighWord]>; 1123 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1124 (AFIMux GR32:$src1, simm32n:$src2)>, 1125 Requires<[FeatureHighWord]>; 1126 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1127 (AHI GR32:$src1, imm32sx16n:$src2)>; 1128 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1129 (AFI GR32:$src1, simm32n:$src2)>; 1130 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1131 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1132 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1133 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1134} 1135 1136// And vice versa in one special case, where we need to load a 1137// constant into a register in any case, but the negated constant 1138// requires fewer instructions to load. 1139def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1140 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1141def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1142 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1143 1144// Subtraction producing a carry. 1145let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1146 // Subtraction of a register. 1147 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1148 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1149 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1150 1151 // Subtraction from a high register. 1152 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1153 Requires<[FeatureHighWord]>; 1154 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1155 Requires<[FeatureHighWord]>; 1156 1157 // Subtraction of unsigned 32-bit immediates. 1158 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1159 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1160 1161 // Subtraction of memory. 1162 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, z_load, 4>; 1163 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, z_azextloadi32, 4>; 1164 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, z_load, 8>; 1165} 1166defm : ZXB<z_usub, GR64, SLGFR>; 1167 1168// Subtracting an immediate is the same as adding the negated immediate. 1169let AddedComplexity = 1 in { 1170 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1171 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1172 Requires<[FeatureDistinctOps]>; 1173 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1174 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1175 Requires<[FeatureDistinctOps]>; 1176} 1177 1178// And vice versa in one special case (but we prefer addition). 1179def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1180 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1181 1182// Subtraction producing and using a carry. 1183let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1184 // Subtraction of a register. 1185 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1186 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1187 1188 // Subtraction of memory. 1189 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, z_load, 4>; 1190 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, z_load, 8>; 1191} 1192 1193 1194//===----------------------------------------------------------------------===// 1195// AND 1196//===----------------------------------------------------------------------===// 1197 1198let Defs = [CC] in { 1199 // ANDs of a register. 1200 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1201 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1202 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1203 } 1204 1205 let isConvertibleToThreeAddress = 1 in { 1206 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1207 // The CC result only reflects the 16-bit field, not the full register. 1208 // 1209 // NIxMux expands to NI[LH]x, depending on the choice of register. 1210 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1211 Requires<[FeatureHighWord]>; 1212 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1213 Requires<[FeatureHighWord]>; 1214 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1215 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1216 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1217 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1218 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1219 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1220 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1221 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1222 1223 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1224 // The CC result only reflects the 32-bit field, which means we can 1225 // use it as a zero indicator for i32 operations but not otherwise. 1226 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1227 // Expands to NILF or NIHF, depending on the choice of register. 1228 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1229 Requires<[FeatureHighWord]>; 1230 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1231 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1232 } 1233 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1234 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1235 } 1236 1237 // ANDs of memory. 1238 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1239 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, z_load, 4>; 1240 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, z_load, 8>; 1241 } 1242 1243 // AND to memory 1244 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1245 1246 // Block AND. 1247 let mayLoad = 1, mayStore = 1 in 1248 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1249} 1250defm : RMWIByte<and, bdaddr12pair, NI>; 1251defm : RMWIByte<and, bdaddr20pair, NIY>; 1252 1253//===----------------------------------------------------------------------===// 1254// OR 1255//===----------------------------------------------------------------------===// 1256 1257let Defs = [CC] in { 1258 // ORs of a register. 1259 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1260 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1261 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1262 } 1263 1264 // ORs of a 16-bit immediate, leaving other bits unaffected. 1265 // The CC result only reflects the 16-bit field, not the full register. 1266 // 1267 // OIxMux expands to OI[LH]x, depending on the choice of register. 1268 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1269 Requires<[FeatureHighWord]>; 1270 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1271 Requires<[FeatureHighWord]>; 1272 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1273 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1274 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1275 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1276 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1277 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1278 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1279 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1280 1281 // ORs of a 32-bit immediate, leaving other bits unaffected. 1282 // The CC result only reflects the 32-bit field, which means we can 1283 // use it as a zero indicator for i32 operations but not otherwise. 1284 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1285 // Expands to OILF or OIHF, depending on the choice of register. 1286 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1287 Requires<[FeatureHighWord]>; 1288 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1289 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1290 } 1291 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1292 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1293 1294 // ORs of memory. 1295 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1296 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, z_load, 4>; 1297 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, z_load, 8>; 1298 } 1299 1300 // OR to memory 1301 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1302 1303 // Block OR. 1304 let mayLoad = 1, mayStore = 1 in 1305 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1306} 1307defm : RMWIByte<or, bdaddr12pair, OI>; 1308defm : RMWIByte<or, bdaddr20pair, OIY>; 1309 1310//===----------------------------------------------------------------------===// 1311// XOR 1312//===----------------------------------------------------------------------===// 1313 1314let Defs = [CC] in { 1315 // XORs of a register. 1316 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1317 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1318 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1319 } 1320 1321 // XORs of a 32-bit immediate, leaving other bits unaffected. 1322 // The CC result only reflects the 32-bit field, which means we can 1323 // use it as a zero indicator for i32 operations but not otherwise. 1324 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1325 // Expands to XILF or XIHF, depending on the choice of register. 1326 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1327 Requires<[FeatureHighWord]>; 1328 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1329 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1330 } 1331 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1332 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1333 1334 // XORs of memory. 1335 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1336 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, z_load, 4>; 1337 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, z_load, 8>; 1338 } 1339 1340 // XOR to memory 1341 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1342 1343 // Block XOR. 1344 let mayLoad = 1, mayStore = 1 in 1345 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1346} 1347defm : RMWIByte<xor, bdaddr12pair, XI>; 1348defm : RMWIByte<xor, bdaddr20pair, XIY>; 1349 1350//===----------------------------------------------------------------------===// 1351// Combined logical operations 1352//===----------------------------------------------------------------------===// 1353 1354let Predicates = [FeatureMiscellaneousExtensions3], 1355 Defs = [CC] in { 1356 // AND with complement. 1357 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1358 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1359 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1360 } 1361 1362 // OR with complement. 1363 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1364 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1365 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1366 } 1367 1368 // NAND. 1369 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1370 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1371 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1372 } 1373 1374 // NOR. 1375 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1376 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1377 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1378 let isAsmParserOnly = 1 in { 1379 def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>; 1380 def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>; 1381 } 1382 } 1383 1384 // NXOR. 1385 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1386 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1387 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1388 } 1389} 1390 1391//===----------------------------------------------------------------------===// 1392// Multiplication 1393//===----------------------------------------------------------------------===// 1394 1395// Multiplication of a register, setting the condition code. We prefer these 1396// over MS(G)R if available, even though we cannot use the condition code, 1397// since they are three-operand instructions. 1398let Predicates = [FeatureMiscellaneousExtensions2], 1399 Defs = [CC], isCommutable = 1 in { 1400 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1401 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1402} 1403 1404// Multiplication of a register. 1405let isCommutable = 1 in { 1406 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1407 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1408} 1409def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1410defm : SXB<mul, GR64, MSGFR>; 1411 1412// Multiplication of a signed 16-bit immediate. 1413def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1414def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1415 1416// Multiplication of a signed 32-bit immediate. 1417def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1418def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1419 1420// Multiplication of memory. 1421defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, z_asextloadi16, 2>; 1422defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, z_load, 4>; 1423def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, z_asextloadi16, 2>, 1424 Requires<[FeatureMiscellaneousExtensions2]>; 1425def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, z_asextloadi32, 4>; 1426def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, z_load, 8>; 1427 1428// Multiplication of memory, setting the condition code. 1429let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1430 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, z_load, 4>; 1431 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, z_load, 8>; 1432} 1433 1434// Multiplication of a register, producing two results. 1435def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1436def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1437 Requires<[FeatureMiscellaneousExtensions2]>; 1438def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1439def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1440 1441def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1442 (MGRK GR64:$src1, GR64:$src2)>; 1443def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1444 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1445 1446// Multiplication of memory, producing two results. 1447def M : BinaryRX <"m", 0x5C, null_frag, GR128, z_load, 4>; 1448def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, z_load, 4>; 1449def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, z_load, 8>, 1450 Requires<[FeatureMiscellaneousExtensions2]>; 1451def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, z_load, 4>; 1452def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, z_load, 8>; 1453 1454def : Pat<(z_smul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1455 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1456def : Pat<(z_umul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1457 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1458 1459//===----------------------------------------------------------------------===// 1460// Division and remainder 1461//===----------------------------------------------------------------------===// 1462 1463let hasSideEffects = 1 in { // Do not speculatively execute. 1464 // Division and remainder, from registers. 1465 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1466 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1467 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1468 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1469 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1470 1471 // Division and remainder, from memory. 1472 def D : BinaryRX <"d", 0x5D, null_frag, GR128, z_load, 4>; 1473 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, z_load, 4>; 1474 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, z_load, 8>; 1475 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, z_load, 4>; 1476 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, z_load, 8>; 1477} 1478def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1479 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1480def : Pat<(z_sdivrem GR64:$src1, (i32 (z_load bdxaddr20only:$src2))), 1481 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1482def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1483 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1484def : Pat<(z_sdivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1485 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1486 1487def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1488 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1489 subreg_l32)), GR32:$src2)>; 1490def : Pat<(z_udivrem GR32:$src1, (i32 (z_load bdxaddr20only:$src2))), 1491 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1492 subreg_l32)), bdxaddr20only:$src2)>; 1493def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1494 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1495def : Pat<(z_udivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1496 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1497 1498//===----------------------------------------------------------------------===// 1499// Shifts 1500//===----------------------------------------------------------------------===// 1501 1502// Logical shift left. 1503defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1504def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1505def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1506 1507// Arithmetic shift left. 1508let Defs = [CC] in { 1509 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1510 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1511 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1512} 1513 1514// Logical shift right. 1515defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1516def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1517def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1518 1519// Arithmetic shift right. 1520let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1521 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1522 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1523 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1524} 1525 1526// Rotate left. 1527def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1528def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1529 1530// Rotate second operand left and inserted selected bits into first operand. 1531// These can act like 32-bit operands provided that the constant start and 1532// end bits (operands 2 and 3) are in the range [32, 64). 1533let Defs = [CC] in { 1534 let isCodeGenOnly = 1 in 1535 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1536 let CCValues = 0xE, CompareZeroCCMask = 0xE in { 1537 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1538 def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>; 1539 } 1540} 1541 1542// On zEC12 we have a variant of RISBG that does not set CC. 1543let Predicates = [FeatureMiscellaneousExtensions] in { 1544 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1545 def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>; 1546} 1547 1548// Forms of RISBG that only affect one word of the destination register. 1549// They do not set CC. 1550let Predicates = [FeatureHighWord] in { 1551 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1552 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1553 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1554 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1555 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1556 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1557 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1558} 1559 1560// Rotate second operand left and perform a logical operation with selected 1561// bits of the first operand. The CC result only describes the selected bits, 1562// so isn't useful for a full comparison against zero. 1563let Defs = [CC] in { 1564 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1565 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1566 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1567} 1568 1569//===----------------------------------------------------------------------===// 1570// Comparison 1571//===----------------------------------------------------------------------===// 1572 1573// Signed comparisons. We put these before the unsigned comparisons because 1574// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1575// of the unsigned forms do. 1576let Defs = [CC], CCValues = 0xE in { 1577 // Comparison with a register. 1578 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1579 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1580 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1581 1582 // Comparison with a high register. 1583 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1584 Requires<[FeatureHighWord]>; 1585 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1586 Requires<[FeatureHighWord]>; 1587 1588 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1589 // depending on the choice of register. 1590 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1591 Requires<[FeatureHighWord]>; 1592 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1593 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1594 1595 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1596 // depending on the choice of register. 1597 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1598 Requires<[FeatureHighWord]>; 1599 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1600 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1601 Requires<[FeatureHighWord]>; 1602 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1603 1604 // Comparison with memory. 1605 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, z_asextloadi16, 2>; 1606 def CMux : CompareRXYPseudo<z_scmp, GRX32, z_load, 4>, 1607 Requires<[FeatureHighWord]>; 1608 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, z_load, 4>; 1609 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, z_load, 4>, 1610 Requires<[FeatureHighWord]>; 1611 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, z_asextloadi16, 2>; 1612 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, z_asextloadi32, 4>; 1613 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, z_load, 8>; 1614 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_z_asextloadi16>; 1615 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_z_load>; 1616 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_z_asextloadi16>; 1617 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_z_asextloadi32>; 1618 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_z_load>; 1619 1620 // Comparison between memory and a signed 16-bit immediate. 1621 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, z_asextloadi16, imm32sx16>; 1622 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, z_load, imm32sx16>; 1623 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, z_load, imm64sx16>; 1624} 1625defm : SXB<z_scmp, GR64, CGFR>; 1626 1627// Unsigned comparisons. 1628let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1629 // Comparison with a register. 1630 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1631 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1632 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1633 1634 // Comparison with a high register. 1635 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1636 Requires<[FeatureHighWord]>; 1637 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1638 Requires<[FeatureHighWord]>; 1639 1640 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1641 // or CLIH, depending on the choice of register. 1642 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1643 Requires<[FeatureHighWord]>; 1644 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1645 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1646 Requires<[FeatureHighWord]>; 1647 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1648 1649 // Comparison with memory. 1650 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, z_load, 4>, 1651 Requires<[FeatureHighWord]>; 1652 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, z_load, 4>; 1653 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, z_load, 4>, 1654 Requires<[FeatureHighWord]>; 1655 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, z_azextloadi32, 4>; 1656 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, z_load, 8>; 1657 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1658 aligned_z_azextloadi16>; 1659 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1660 aligned_z_load>; 1661 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1662 aligned_z_azextloadi16>; 1663 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1664 aligned_z_azextloadi32>; 1665 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1666 aligned_z_load>; 1667 1668 // Comparison between memory and an unsigned 8-bit immediate. 1669 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, z_azextloadi8, imm32zx8>; 1670 1671 // Comparison between memory and an unsigned 16-bit immediate. 1672 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, z_azextloadi16, imm32zx16>; 1673 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, z_load, imm32zx16>; 1674 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, z_load, imm64zx16>; 1675} 1676defm : ZXB<z_ucmp, GR64, CLGFR>; 1677 1678// Memory-to-memory comparison. 1679let mayLoad = 1, Defs = [CC] in { 1680 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1681 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1682 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1683 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1684} 1685 1686// String comparison. 1687let mayLoad = 1, Defs = [CC] in 1688 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1689 1690// Test under mask. 1691let Defs = [CC] in { 1692 // TMxMux expands to TM[LH]x, depending on the choice of register. 1693 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1694 Requires<[FeatureHighWord]>; 1695 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1696 Requires<[FeatureHighWord]>; 1697 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1698 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1699 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1700 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1701 1702 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1703 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1704 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1705 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1706 1707 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, z_anyextloadi8, imm32zx8>; 1708} 1709 1710def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1711def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1712 1713// Compare logical characters under mask -- not (yet) used for codegen. 1714let Defs = [CC] in { 1715 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1716 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1717} 1718 1719//===----------------------------------------------------------------------===// 1720// Prefetch and execution hint 1721//===----------------------------------------------------------------------===// 1722 1723let mayLoad = 1, mayStore = 1 in { 1724 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1725 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1726} 1727 1728let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1729 // Branch Prediction Preload 1730 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1731 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1732 1733 // Next Instruction Access Intent 1734 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1735} 1736 1737//===----------------------------------------------------------------------===// 1738// Atomic operations 1739//===----------------------------------------------------------------------===// 1740 1741// A serialization instruction that acts as a barrier for all memory 1742// accesses, which expands to "bcr 14, 0". 1743let hasSideEffects = 1 in 1744def Serialize : Alias<2, (outs), (ins), []>; 1745 1746let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1747 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_i32, GR32>; 1748 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_i64, GR64>; 1749 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1750 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1751 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_i32, GR32>; 1752 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_i64, GR64>; 1753 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_i32, GR32>; 1754 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_i64, GR64>; 1755 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_i32, GR32>; 1756 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_i64, GR64>; 1757} 1758 1759def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1760 1761def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1762def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1763 1764def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1765 1766def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1767def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1768 1769def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1770def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1771 1772def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1773def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1774 1775def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1776def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1777 imm32lh16c>; 1778 1779def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1780def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1781def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1782def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1783 1784def ATOMIC_CMP_SWAPW 1785 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1786 ADDR32:$bitshift, ADDR32:$negbitshift, 1787 uimm32:$bitsize), 1788 [(set GR32:$dst, 1789 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1790 ADDR32:$bitshift, ADDR32:$negbitshift, 1791 uimm32:$bitsize))]> { 1792 let Defs = [CC]; 1793 let mayLoad = 1; 1794 let mayStore = 1; 1795 let usesCustomInserter = 1; 1796 let hasNoSchedulingInfo = 1; 1797} 1798 1799// Test and set. 1800let mayLoad = 1, Defs = [CC] in 1801 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1802 1803// Compare and swap. 1804let Defs = [CC] in { 1805 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1806 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1807} 1808 1809// Compare double and swap. 1810let Defs = [CC] in { 1811 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1812 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1813} 1814 1815// Compare and swap and store. 1816let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1817 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1818 1819// Perform locked operation. 1820let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1821 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1822 1823// Load/store pair from/to quadword. 1824def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1825def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1826 1827// Load pair disjoint. 1828let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1829 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1830 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1831} 1832 1833//===----------------------------------------------------------------------===// 1834// Translate and convert 1835//===----------------------------------------------------------------------===// 1836 1837let mayLoad = 1, mayStore = 1 in 1838 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1839 1840let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1841 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1842 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1843} 1844 1845let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1846 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1847 1848let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1849 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1850 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1851} 1852 1853let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1854 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1855 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1856 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1857 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1858} 1859 1860let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1861 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1862 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1863 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1864 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1865 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1866 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1867 1868 let isAsmParserOnly = 1 in { 1869 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1870 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1871 } 1872} 1873 1874//===----------------------------------------------------------------------===// 1875// Message-security assist 1876//===----------------------------------------------------------------------===// 1877 1878let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1879 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1880 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1881 1882 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1883 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1884 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1885 1886 let Predicates = [FeatureMessageSecurityAssist4] in { 1887 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1888 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1889 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1890 GR128, GR128, GR128>; 1891 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1892 } 1893 1894 let Predicates = [FeatureMessageSecurityAssist5] in 1895 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1896 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1897 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1898 1899 let Predicates = [FeatureMessageSecurityAssist8] in 1900 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1901 GR128, GR128, GR128>; 1902 1903 let Predicates = [FeatureMessageSecurityAssist9] in 1904 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1905} 1906 1907//===----------------------------------------------------------------------===// 1908// Guarded storage 1909//===----------------------------------------------------------------------===// 1910 1911// These instructions use and/or modify the guarded storage control 1912// registers, which we do not otherwise model, so they should have 1913// hasSideEffects. 1914let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1915 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1916 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1917 1918 let mayLoad = 1 in 1919 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1920 let mayStore = 1 in 1921 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1922} 1923 1924//===----------------------------------------------------------------------===// 1925// Decimal arithmetic 1926//===----------------------------------------------------------------------===// 1927 1928defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, z_load, 4>; 1929def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, z_load, 8>; 1930 1931defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1932def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1933 1934let mayLoad = 1, mayStore = 1 in { 1935 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1936 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1937 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1938 1939 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1940 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1941 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1942 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1943 let Defs = [CC] in { 1944 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1945 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1946 } 1947} 1948 1949let mayLoad = 1, mayStore = 1 in { 1950 let Defs = [CC] in { 1951 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1952 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1953 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1954 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1955 } 1956 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1957 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1958 let Defs = [CC] in { 1959 def ED : SideEffectBinarySSa<"ed", 0xDE>; 1960 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 1961 } 1962} 1963 1964let Defs = [CC] in { 1965 def CP : CompareSSb<"cp", 0xF9>; 1966 def TP : TestRSL<"tp", 0xEBC0>; 1967} 1968 1969//===----------------------------------------------------------------------===// 1970// Access registers 1971//===----------------------------------------------------------------------===// 1972 1973// Read a 32-bit access register into a GR32. As with all GR32 operations, 1974// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 1975// when a 64-bit address is stored in a pair of access registers. 1976def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 1977 1978// Set access register. 1979def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 1980 1981// Copy access register. 1982def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 1983 1984// Load address extended. 1985defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 1986 1987// Load access multiple. 1988defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 1989 1990// Store access multiple. 1991defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 1992 1993//===----------------------------------------------------------------------===// 1994// Program mask and addressing mode 1995//===----------------------------------------------------------------------===// 1996 1997// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 1998let Uses = [CC] in 1999 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2000 2001// Set CC and program mask from a register. 2002let hasSideEffects = 1, Defs = [CC] in 2003 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2004 2005// Branch and link - like BAS, but also extracts CC and program mask. 2006let isCall = 1, Uses = [CC], Defs = [CC] in { 2007 def BAL : CallRX<"bal", 0x45>; 2008 def BALR : CallRR<"balr", 0x05>; 2009} 2010 2011// Test addressing mode. 2012let Defs = [CC] in 2013 def TAM : SideEffectInherentE<"tam", 0x010B>; 2014 2015// Set addressing mode. 2016let hasSideEffects = 1 in { 2017 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2018 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2019 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2020} 2021 2022// Branch and set mode. Not really a call, but also sets an output register. 2023let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2024 def BSM : CallRR<"bsm", 0x0B>; 2025 2026// Branch and save and set mode. 2027let isCall = 1, Defs = [CC] in 2028 def BASSM : CallRR<"bassm", 0x0C>; 2029 2030//===----------------------------------------------------------------------===// 2031// Transactional execution 2032//===----------------------------------------------------------------------===// 2033 2034let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2035 // Transaction Begin 2036 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2037 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2038 let hasNoSchedulingInfo = 1 in 2039 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2040 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2041 int_s390_tbeginc, imm32zx16>; 2042 } 2043 2044 // Transaction End 2045 let Defs = [CC] in 2046 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2047 2048 // Transaction Abort 2049 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2050 hasSideEffects = 1 in 2051 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2052 2053 // Nontransactional Store 2054 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2055 2056 // Extract Transaction Nesting Depth 2057 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2058} 2059 2060//===----------------------------------------------------------------------===// 2061// Processor assist 2062//===----------------------------------------------------------------------===// 2063 2064let Predicates = [FeatureProcessorAssist] in { 2065 let hasSideEffects = 1 in 2066 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2067 def : Pat<(int_s390_ppa_txassist GR32:$src), 2068 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2069 zero_reg, 1)>; 2070} 2071 2072//===----------------------------------------------------------------------===// 2073// Miscellaneous Instructions. 2074//===----------------------------------------------------------------------===// 2075 2076// Find leftmost one, AKA count leading zeros. The instruction actually 2077// returns a pair of GR64s, the first giving the number of leading zeros 2078// and the second giving a copy of the source with the leftmost one bit 2079// cleared. We only use the first result here. 2080let Defs = [CC] in 2081 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2082def : Pat<(i64 (ctlz GR64:$src)), 2083 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2084 2085// Population count. Counts bits set per byte or doubleword. 2086let Predicates = [FeatureMiscellaneousExtensions3] in { 2087 let Defs = [CC] in 2088 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2089 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2090} 2091let Predicates = [FeaturePopulationCount], Defs = [CC] in 2092 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2093 2094// Search a block of memory for a character. 2095let mayLoad = 1, Defs = [CC] in 2096 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2097let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2098 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2099 2100// Compare until substring equal. 2101let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2102 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2103 2104// Compare and form codeword. 2105let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2106 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2107 2108// Update tree. 2109let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2110 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2111 def UPT : SideEffectInherentE<"upt", 0x0102>; 2112 2113// Checksum. 2114let mayLoad = 1, Defs = [CC] in 2115 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2116 2117// Compression call. 2118let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2119 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2120 2121// Sort lists. 2122let Predicates = [FeatureEnhancedSort], 2123 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2124 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2125 2126// Deflate conversion call. 2127let Predicates = [FeatureDeflateConversion], 2128 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2129 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2130 GR128, GR128, GR64>; 2131 2132// NNPA. 2133let Predicates = [FeatureNNPAssist], 2134 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2135 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2136 2137// Execute. 2138let hasSideEffects = 1 in { 2139 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2140 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2141 let hasNoSchedulingInfo = 1 in 2142 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2143 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2144 []>; 2145} 2146 2147//===----------------------------------------------------------------------===// 2148// .insn directive instructions 2149//===----------------------------------------------------------------------===// 2150 2151let isCodeGenOnly = 1, hasSideEffects = 1 in { 2152 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2153 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2154 imm32sx16:$I2), 2155 ".insn ri,$enc,$R1,$I2", []>; 2156 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2157 AnyReg:$R3, brtarget16:$I2), 2158 ".insn rie,$enc,$R1,$R3,$I2", []>; 2159 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2160 brtarget32:$I2), 2161 ".insn ril,$enc,$R1,$I2", []>; 2162 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2163 uimm32:$I2), 2164 ".insn rilu,$enc,$R1,$I2", []>; 2165 def InsnRIS : DirectiveInsnRIS<(outs), 2166 (ins imm64zx48:$enc, AnyReg:$R1, 2167 imm32sx8:$I2, imm32zx4:$M3, 2168 (bdaddr12only $B4, $D4):$BD4), 2169 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2170 def InsnRR : DirectiveInsnRR<(outs), 2171 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2172 ".insn rr,$enc,$R1,$R2", []>; 2173 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2174 AnyReg:$R1, AnyReg:$R2), 2175 ".insn rre,$enc,$R1,$R2", []>; 2176 def InsnRRF : DirectiveInsnRRF<(outs), 2177 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2178 AnyReg:$R3, imm32zx4:$M4), 2179 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2180 def InsnRRS : DirectiveInsnRRS<(outs), 2181 (ins imm64zx48:$enc, AnyReg:$R1, 2182 AnyReg:$R2, imm32zx4:$M3, 2183 (bdaddr12only $B4, $D4):$BD4), 2184 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2185 def InsnRS : DirectiveInsnRS<(outs), 2186 (ins imm64zx32:$enc, AnyReg:$R1, 2187 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2188 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2189 def InsnRSE : DirectiveInsnRSE<(outs), 2190 (ins imm64zx48:$enc, AnyReg:$R1, 2191 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2192 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2193 def InsnRSI : DirectiveInsnRSI<(outs), 2194 (ins imm64zx48:$enc, AnyReg:$R1, 2195 AnyReg:$R3, brtarget16:$RI2), 2196 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2197 def InsnRSY : DirectiveInsnRSY<(outs), 2198 (ins imm64zx48:$enc, AnyReg:$R1, 2199 AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2), 2200 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2201 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2202 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2203 ".insn rx,$enc,$R1,$XBD2", []>; 2204 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2205 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2206 ".insn rxe,$enc,$R1,$XBD2", []>; 2207 def InsnRXF : DirectiveInsnRXF<(outs), 2208 (ins imm64zx48:$enc, AnyReg:$R1, 2209 AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2210 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2211 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2212 (bdxaddr20only $B2, $D2, $X2):$XBD2), 2213 ".insn rxy,$enc,$R1,$XBD2", []>; 2214 def InsnS : DirectiveInsnS<(outs), 2215 (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2), 2216 ".insn s,$enc,$BD2", []>; 2217 def InsnSI : DirectiveInsnSI<(outs), 2218 (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, 2219 imm32sx8:$I2), 2220 ".insn si,$enc,$BD1,$I2", []>; 2221 def InsnSIY : DirectiveInsnSIY<(outs), 2222 (ins imm64zx48:$enc, 2223 (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2), 2224 ".insn siy,$enc,$BD1,$I2", []>; 2225 def InsnSIL : DirectiveInsnSIL<(outs), 2226 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2227 imm32zx16:$I2), 2228 ".insn sil,$enc,$BD1,$I2", []>; 2229 def InsnSS : DirectiveInsnSS<(outs), 2230 (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1, 2231 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2232 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2233 def InsnSSE : DirectiveInsnSSE<(outs), 2234 (ins imm64zx48:$enc, 2235 (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2), 2236 ".insn sse,$enc,$BD1,$BD2", []>; 2237 def InsnSSF : DirectiveInsnSSF<(outs), 2238 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2239 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2240 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2241 def InsnVRI : DirectiveInsnVRI<(outs), 2242 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2243 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2244 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2245 def InsnVRR : DirectiveInsnVRR<(outs), 2246 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2247 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2248 imm32zx4:$M6), 2249 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2250 def InsnVRS : DirectiveInsnVRS<(outs), 2251 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2252 (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2253 ".insn vrs,$enc,$BD2,$M4", []>; 2254 def InsnVRV : DirectiveInsnVRV<(outs), 2255 (ins imm64zx48:$enc, VR128:$V1, 2256 (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3), 2257 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2258 def InsnVRX : DirectiveInsnVRX<(outs), 2259 (ins imm64zx48:$enc, VR128:$V1, 2260 (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2261 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2262 def InsnVSI : DirectiveInsnVSI<(outs), 2263 (ins imm64zx48:$enc, VR128:$V1, 2264 (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2265 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2266} 2267 2268//===----------------------------------------------------------------------===// 2269// Peepholes. 2270//===----------------------------------------------------------------------===// 2271 2272// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2273// equivalent to (and (xor x, -1), y) 2274def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2275 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2276 2277// Use LCGR/AGHI for i64 xor with -1. 2278def : Pat<(xor GR64:$x, (i64 -1)), 2279 (AGHI (LCGR GR64:$x), (i64 -1))>; 2280 2281// Shift/rotate instructions only use the last 6 bits of the second operand 2282// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2283// last 16 bits. 2284// Complexity is added so that we match this before we match NILF on the AND 2285// operation alone. 2286let AddedComplexity = 4 in { 2287 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2288 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2289 2290 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2291 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2292 2293 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2294 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2295 2296 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2297 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2298 2299 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2300 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2301 2302 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2303 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2304 2305 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2306 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2307 2308 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2309 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2310} 2311 2312// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2313// use the last 6 bits of the second operand register (making it modulo 64). 2314let AddedComplexity = 4 in { 2315 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2316 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2317 2318 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2319 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2320 2321 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2322 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2323 2324 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2325 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2326} 2327 2328// Peepholes for turning scalar operations into block operations. The length 2329// is given as one less for these pseudos. 2330defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2331defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2332defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2333defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2334defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2335defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2336defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2337 2338//===----------------------------------------------------------------------===// 2339// Mnemonic Aliases 2340//===----------------------------------------------------------------------===// 2341 2342def JCT : MnemonicAlias<"jct", "brct">; 2343def JCTG : MnemonicAlias<"jctg", "brctg">; 2344def JC : MnemonicAlias<"jc", "brc">; 2345def JCTH : MnemonicAlias<"jcth", "brcth">; 2346def JAS : MnemonicAlias<"jas", "bras">; 2347def JASL : MnemonicAlias<"jasl", "brasl">; 2348def JXH : MnemonicAlias<"jxh", "brxh">; 2349def JXLE : MnemonicAlias<"jxle", "brxle">; 2350def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2351def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2352 2353def BRU : MnemonicAlias<"bru", "j">; 2354def BRUL : MnemonicAlias<"brul", "jg", "att">; 2355def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2356 2357foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2358 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2359 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2360 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2361 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2362} 2363