1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// The callseq_start node requires the hasSideEffects flag, even though these 17// instructions are noops on SystemZ. 18let hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45//===----------------------------------------------------------------------===// 46// Branch instructions 47//===----------------------------------------------------------------------===// 48 49// Conditional branches. 50let isBranch = 1, isTerminator = 1, Uses = [CC] in { 51 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 52 // with the condition-code mask being the first operand. It seems friendlier 53 // to use mnemonic forms like JE and JLH when writing out the assembly though. 54 let isCodeGenOnly = 1 in { 55 // An assembler extended mnemonic for BRC. 56 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 57 // An assembler extended mnemonic for BRCL. (The extension is "G" 58 // rather than "L" because "JL" is "Jump if Less".) 59 def BRCL : CondBranchRIL<"jg#", 0xC04>; 60 let isIndirectBranch = 1 in { 61 def BC : CondBranchRX<"b#", 0x47>; 62 def BCR : CondBranchRR<"b#r", 0x07>; 63 def BIC : CondBranchRXY<"bi#", 0xe347>, 64 Requires<[FeatureMiscellaneousExtensions2]>; 65 } 66 } 67 68 // Allow using the raw forms directly from the assembler (and occasional 69 // special code generation needs) as well. 70 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 71 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 72 let isIndirectBranch = 1 in { 73 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 74 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 75 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 76 Requires<[FeatureMiscellaneousExtensions2]>; 77 } 78 79 // Define AsmParser extended mnemonics for each general condition-code mask 80 // (integer or floating-point) 81 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 82 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 83 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 84 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 85 let isIndirectBranch = 1 in { 86 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 87 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 88 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 89 Requires<[FeatureMiscellaneousExtensions2]>; 90 } 91 } 92} 93 94// Unconditional branches. These are in fact simply variants of the 95// conditional branches with the condition mask set to "always". 96let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 97 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 98 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 99 let isIndirectBranch = 1 in { 100 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 101 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 102 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 103 Requires<[FeatureMiscellaneousExtensions2]>; 104 } 105} 106 107// NOPs. These are again variants of the conditional branches, with the 108// condition mask set to "never". NOP_bare can't be an InstAlias since it 109// would need R0D hard coded which is not part of ADDR64BitRegClass. 110def NOP : InstAlias<"nop\t$XBD", (BCAsm 0, bdxaddr12only:$XBD), 0>; 111let isAsmParserOnly = 1, hasNoSchedulingInfo = 1, M1 = 0, XBD2 = 0 in 112 def NOP_bare : InstRXb<0x47,(outs), (ins), "nop", []>; 113def NOPR : InstAlias<"nopr\t$R", (BCRAsm 0, GR64:$R), 0>; 114def NOPR_bare : InstAlias<"nopr", (BCRAsm 0, R0D), 0>; 115 116// An alias of BRC 0, label 117def JNOP : InstAlias<"jnop\t$RI2", (BRCAsm 0, brtarget16:$RI2), 0>; 118 119// An alias of BRCL 0, label 120// jgnop on att ; jlnop on hlasm 121def JGNOP : InstAlias<"{jgnop|jlnop}\t$RI2", (BRCLAsm 0, brtarget32:$RI2), 0>; 122 123// Fused compare-and-branch instructions. 124// 125// These instructions do not use or clobber the condition codes. 126// We nevertheless pretend that the relative compare-and-branch 127// instructions clobber CC, so that we can lower them to separate 128// comparisons and BRCLs if the branch ends up being out of range. 129let isBranch = 1, isTerminator = 1 in { 130 // As for normal branches, we handle these instructions internally in 131 // their raw CRJ-like form, but use assembly macros like CRJE when writing 132 // them out. Using the *Pair multiclasses, we also create the raw forms. 133 let Defs = [CC] in { 134 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 135 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 136 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 137 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 138 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 139 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 140 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 141 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 142 } 143 let isIndirectBranch = 1 in { 144 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 145 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 146 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 147 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 148 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 149 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 150 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 151 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 152 } 153 154 // Define AsmParser mnemonics for each integer condition-code mask. 155 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 156 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 157 let Defs = [CC] in { 158 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 159 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 160 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 161 imm32sx8>; 162 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 163 imm64sx8>; 164 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 165 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 166 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 167 imm32zx8>; 168 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 169 imm64zx8>; 170 } 171 let isIndirectBranch = 1 in { 172 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 173 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 174 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 175 imm32sx8>; 176 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 177 imm64sx8>; 178 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 179 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 180 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 181 imm32zx8>; 182 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 183 imm64zx8>; 184 } 185 } 186} 187 188// Decrement a register and branch if it is nonzero. These don't clobber CC, 189// but we might need to split long relative branches into sequences that do. 190let isBranch = 1, isTerminator = 1 in { 191 let Defs = [CC] in { 192 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 193 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 194 } 195 // This doesn't need to clobber CC since we never need to split it. 196 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 197 Requires<[FeatureHighWord]>; 198 199 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 200 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 201 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 202 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 203} 204 205let isBranch = 1, isTerminator = 1 in { 206 let Defs = [CC] in { 207 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 208 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 209 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 210 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 211 } 212 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 213 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 214 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 215 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 216} 217 218//===----------------------------------------------------------------------===// 219// Trap instructions 220//===----------------------------------------------------------------------===// 221 222// Unconditional trap. 223let hasCtrlDep = 1, hasSideEffects = 1 in 224 def Trap : Alias<4, (outs), (ins), [(trap)]>; 225 226// Conditional trap. 227let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 228 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 229 230// Fused compare-and-trap instructions. 231let hasCtrlDep = 1, hasSideEffects = 1 in { 232 // These patterns work the same way as for compare-and-branch. 233 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 234 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 235 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 236 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 237 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 238 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 239 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 240 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 241 let Predicates = [FeatureMiscellaneousExtensions] in { 242 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 243 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 244 } 245 246 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 247 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 248 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 249 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 250 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 251 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 252 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 253 imm32sx16>; 254 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 255 imm64sx16>; 256 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 257 imm32zx16>; 258 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 259 imm64zx16>; 260 let Predicates = [FeatureMiscellaneousExtensions] in { 261 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 262 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 263 } 264 } 265} 266 267//===----------------------------------------------------------------------===// 268// Call and return instructions 269//===----------------------------------------------------------------------===// 270 271// Define the general form of the call instructions for the asm parser. 272// These instructions don't hard-code %r14 as the return address register. 273let isCall = 1, Defs = [CC] in { 274 def BRAS : CallRI <"bras", 0xA75>; 275 def BRASL : CallRIL<"brasl", 0xC05>; 276 def BAS : CallRX <"bas", 0x4D>; 277 def BASR : CallRR <"basr", 0x0D>; 278} 279 280// z/OS XPLINK 281let Predicates = [IsTargetXPLINK64] in { 282 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 283 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 284 [(z_call pcrel32:$I2)]>; 285 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 286 [(z_call ADDR64:$R2)]>; 287 } 288} 289 290// Regular calls. 291// z/Linux ELF 292let Predicates = [IsTargetELF] in { 293 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 294 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 295 [(z_call pcrel32:$I2)]>; 296 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 297 [(z_call ADDR64:$R2)]>; 298 } 299 300 // TLS calls. These will be lowered into a call to __tls_get_offset, 301 // with an extra relocation specifying the TLS symbol. 302 let isCall = 1, Defs = [R14D, CC] in { 303 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 304 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 305 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 306 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 307 } 308} 309 310// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 311// R1 used for ELF 312let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 313 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 314 [(z_sibcall pcrel32:$I2)]>; 315 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 316 [(z_sibcall ADDR64:$R2)]>; 317} 318 319// Conditional sibling calls. 320let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 321 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 322 pcrel32:$I2), []>; 323 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 324 ADDR64:$R2), []>; 325} 326 327// Fused compare and conditional sibling calls. 328let isCall = 1, isTerminator = 1, isReturn = 1 in { 329 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 330 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 331 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 332 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 333 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 334 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 335 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 336 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 337} 338 339// A return instruction (br %r14) for ELF and (b 2 %r7) for XPLink. 340let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 341 def Return : Alias<2, (outs), (ins), [(z_retflag)]>; 342 343// A conditional return instruction (bcr <cond>, %r14). 344let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 345 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 346 347// Fused compare and conditional returns. 348let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 349 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 350 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 351 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 352 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 353 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 354 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 355 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 356 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 357} 358 359//===----------------------------------------------------------------------===// 360// Select instructions 361//===----------------------------------------------------------------------===// 362 363def Select32 : SelectWrapper<i32, GR32>, 364 Requires<[FeatureNoLoadStoreOnCond]>; 365def Select64 : SelectWrapper<i64, GR64>, 366 Requires<[FeatureNoLoadStoreOnCond]>; 367 368// We don't define 32-bit Mux stores if we don't have STOCFH, because the 369// low-only STOC should then always be used if possible. 370defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 371 nonvolatile_anyextloadi8, bdxaddr20only>, 372 Requires<[FeatureHighWord]>; 373defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 374 nonvolatile_anyextloadi16, bdxaddr20only>, 375 Requires<[FeatureHighWord]>; 376defm CondStore32Mux : CondStores<GRX32, simple_store, 377 simple_load, bdxaddr20only>, 378 Requires<[FeatureLoadStoreOnCond2]>; 379defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 380 nonvolatile_anyextloadi8, bdxaddr20only>; 381defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 382 nonvolatile_anyextloadi16, bdxaddr20only>; 383defm CondStore32 : CondStores<GR32, simple_store, 384 simple_load, bdxaddr20only>; 385 386defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 387 nonvolatile_anyextloadi8, bdxaddr20only>; 388defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 389 nonvolatile_anyextloadi16, bdxaddr20only>; 390defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 391 nonvolatile_anyextloadi32, bdxaddr20only>; 392defm CondStore64 : CondStores<GR64, simple_store, 393 simple_load, bdxaddr20only>; 394 395//===----------------------------------------------------------------------===// 396// Move instructions 397//===----------------------------------------------------------------------===// 398 399// Register moves. 400def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 401def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 402 403let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 404 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 405 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 406} 407 408let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 409 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 410 411// Immediate moves. 412let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 413 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 414 // deopending on the choice of register. 415 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 416 Requires<[FeatureHighWord]>; 417 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 418 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 419 420 // Other 16-bit immediates. 421 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 422 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 423 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 424 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 425 426 // 32-bit immediates. 427 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 428 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 429 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 430} 431 432// Register loads. 433let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 434 // Expands to L, LY or LFH, depending on the choice of register. 435 def LMux : UnaryRXYPseudo<"l", load, GRX32, 4>, 436 Requires<[FeatureHighWord]>; 437 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>; 438 def LFH : UnaryRXY<"lfh", 0xE3CA, load, GRH32, 4>, 439 Requires<[FeatureHighWord]>; 440 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>; 441 442 // These instructions are split after register allocation, so we don't 443 // want a custom inserter. 444 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 445 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 446 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 447 } 448} 449let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 450 def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; 451 def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; 452} 453 454let canFoldAsLoad = 1 in { 455 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; 456 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; 457} 458 459// Load and zero rightmost byte. 460let Predicates = [FeatureLoadAndZeroRightmostByte] in { 461 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 462 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 463 def : Pat<(and (i32 (load bdxaddr20only:$src)), 0xffffff00), 464 (LZRF bdxaddr20only:$src)>; 465 def : Pat<(and (i64 (load bdxaddr20only:$src)), 0xffffffffffffff00), 466 (LZRG bdxaddr20only:$src)>; 467} 468 469// Load and trap. 470let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 471 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 472 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 473 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 474} 475 476// Register stores. 477let SimpleBDXStore = 1, mayStore = 1 in { 478 // Expands to ST, STY or STFH, depending on the choice of register. 479 def STMux : StoreRXYPseudo<store, GRX32, 4>, 480 Requires<[FeatureHighWord]>; 481 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 482 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 483 Requires<[FeatureHighWord]>; 484 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 485 486 // These instructions are split after register allocation, so we don't 487 // want a custom inserter. 488 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 489 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 490 [(store GR128:$src, bdxaddr20only128:$dst)]>; 491 } 492} 493def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 494def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 495 496// 8-bit immediate stores to 8-bit fields. 497defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 498 499// 16-bit immediate stores to 16-, 32- or 64-bit fields. 500def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 501def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 502def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 503 504// Memory-to-memory moves. 505let mayLoad = 1, mayStore = 1 in 506 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 507let mayLoad = 1, mayStore = 1, Defs = [CC] in { 508 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 509 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 510 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 511} 512 513// Memset[Length][Byte] pseudos. 514def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 515def MemsetImmReg : MemsetPseudo<imm64, GR32>; 516def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 517def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 518 519// Move right. 520let Predicates = [FeatureMiscellaneousExtensions3], 521 mayLoad = 1, mayStore = 1, Uses = [R0L] in 522 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 523 524// String moves. 525let mayLoad = 1, mayStore = 1, Defs = [CC] in 526 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 527 528//===----------------------------------------------------------------------===// 529// Conditional move instructions 530//===----------------------------------------------------------------------===// 531 532let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 533 // Select. 534 let isCommutable = 1 in { 535 // Expands to SELR or SELFHR or a branch-and-move sequence, 536 // depending on the choice of registers. 537 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 538 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 539 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 540 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 541 } 542 543 // Define AsmParser extended mnemonics for each general condition-code mask. 544 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 545 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 546 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 547 GR32, GR32, GR32>; 548 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 549 GRH32, GRH32, GRH32>; 550 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 551 GR64, GR64, GR64>; 552 } 553} 554 555let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 556 // Load immediate on condition. Matched via DAG pattern and created 557 // by the PeepholeOptimizer via FoldImmediate. 558 559 // Expands to LOCHI or LOCHHI, depending on the choice of register. 560 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 561 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 562 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 563 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 564 565 // Move register on condition. Matched via DAG pattern and 566 // created by early if-conversion. 567 let isCommutable = 1 in { 568 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 569 // depending on the choice of registers. 570 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 571 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 572 } 573 574 // Load on condition. Matched via DAG pattern. 575 // Expands to LOC or LOCFH, depending on the choice of register. 576 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 577 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 578 579 // Store on condition. Expanded from CondStore* pseudos. 580 // Expands to STOC or STOCFH, depending on the choice of register. 581 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 582 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 583 584 // Define AsmParser extended mnemonics for each general condition-code mask. 585 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 586 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 587 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 588 imm32sx16>; 589 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 590 imm64sx16>; 591 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 592 imm32sx16>; 593 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 594 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 595 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 596 } 597} 598 599let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 600 // Move register on condition. Matched via DAG pattern and 601 // created by early if-conversion. 602 let isCommutable = 1 in { 603 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 604 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 605 } 606 607 // Load on condition. Matched via DAG pattern. 608 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 609 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 610 611 // Store on condition. Expanded from CondStore* pseudos. 612 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 613 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 614 615 // Define AsmParser extended mnemonics for each general condition-code mask. 616 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 617 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 618 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 619 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 620 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 621 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 622 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 623 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 624 } 625} 626//===----------------------------------------------------------------------===// 627// Sign extensions 628//===----------------------------------------------------------------------===// 629// 630// Note that putting these before zero extensions mean that we will prefer 631// them for anyextload*. There's not really much to choose between the two 632// either way, but signed-extending loads have a short LH and a long LHY, 633// while zero-extending loads have only the long LLH. 634// 635//===----------------------------------------------------------------------===// 636 637// 32-bit extensions from registers. 638def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 639def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 640 641// 64-bit extensions from registers. 642def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 643def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 644def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 645 646let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 647 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 648 649// Match 32-to-64-bit sign extensions in which the source is already 650// in a 64-bit register. 651def : Pat<(sext_inreg GR64:$src, i32), 652 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 653 654// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 655// depending on the choice of register. 656def LBMux : UnaryRXYPseudo<"lb", asextloadi8, GRX32, 1>, 657 Requires<[FeatureHighWord]>; 658def LB : UnaryRXY<"lb", 0xE376, asextloadi8, GR32, 1>; 659def LBH : UnaryRXY<"lbh", 0xE3C0, asextloadi8, GRH32, 1>, 660 Requires<[FeatureHighWord]>; 661 662// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 663// depending on the choice of register. 664def LHMux : UnaryRXYPseudo<"lh", asextloadi16, GRX32, 2>, 665 Requires<[FeatureHighWord]>; 666defm LH : UnaryRXPair<"lh", 0x48, 0xE378, asextloadi16, GR32, 2>; 667def LHH : UnaryRXY<"lhh", 0xE3C4, asextloadi16, GRH32, 2>, 668 Requires<[FeatureHighWord]>; 669def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_asextloadi16, GR32>; 670 671// 64-bit extensions from memory. 672def LGB : UnaryRXY<"lgb", 0xE377, asextloadi8, GR64, 1>; 673def LGH : UnaryRXY<"lgh", 0xE315, asextloadi16, GR64, 2>; 674def LGF : UnaryRXY<"lgf", 0xE314, asextloadi32, GR64, 4>; 675def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_asextloadi16, GR64>; 676def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_asextloadi32, GR64>; 677let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 678 def LTGF : UnaryRXY<"ltgf", 0xE332, asextloadi32, GR64, 4>; 679 680//===----------------------------------------------------------------------===// 681// Zero extensions 682//===----------------------------------------------------------------------===// 683 684// 32-bit extensions from registers. 685 686// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 687def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 688 Requires<[FeatureHighWord]>; 689def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 690// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 691def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 692 Requires<[FeatureHighWord]>; 693def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 694 695// 64-bit extensions from registers. 696def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 697def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 698def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 699 700// Match 32-to-64-bit zero extensions in which the source is already 701// in a 64-bit register. 702def : Pat<(and GR64:$src, 0xffffffff), 703 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 704 705// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 706// depending on the choice of register. 707def LLCMux : UnaryRXYPseudo<"llc", azextloadi8, GRX32, 1>, 708 Requires<[FeatureHighWord]>; 709def LLC : UnaryRXY<"llc", 0xE394, azextloadi8, GR32, 1>; 710def LLCH : UnaryRXY<"llch", 0xE3C2, azextloadi8, GRH32, 1>, 711 Requires<[FeatureHighWord]>; 712 713// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 714// depending on the choice of register. 715def LLHMux : UnaryRXYPseudo<"llh", azextloadi16, GRX32, 2>, 716 Requires<[FeatureHighWord]>; 717def LLH : UnaryRXY<"llh", 0xE395, azextloadi16, GR32, 2>; 718def LLHH : UnaryRXY<"llhh", 0xE3C6, azextloadi16, GRH32, 2>, 719 Requires<[FeatureHighWord]>; 720def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_azextloadi16, GR32>; 721 722// 64-bit extensions from memory. 723def LLGC : UnaryRXY<"llgc", 0xE390, azextloadi8, GR64, 1>; 724def LLGH : UnaryRXY<"llgh", 0xE391, azextloadi16, GR64, 2>; 725def LLGF : UnaryRXY<"llgf", 0xE316, azextloadi32, GR64, 4>; 726def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_azextloadi16, GR64>; 727def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_azextloadi32, GR64>; 728 729// 31-to-64-bit zero extensions. 730def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 731def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 732def : Pat<(and GR64:$src, 0x7fffffff), 733 (LLGTR GR64:$src)>; 734def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 735 (LLGT bdxaddr20only:$src)>; 736 737// Load and zero rightmost byte. 738let Predicates = [FeatureLoadAndZeroRightmostByte] in { 739 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 740 def : Pat<(and (i64 (azextloadi32 bdxaddr20only:$src)), 0xffffff00), 741 (LLZRGF bdxaddr20only:$src)>; 742} 743 744// Load and trap. 745let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 746 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 747 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 748} 749 750// Extend GR64s to GR128s. 751let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 752 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 753 754//===----------------------------------------------------------------------===// 755// "Any" extensions 756//===----------------------------------------------------------------------===// 757 758// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 759def : Pat<(i64 (anyext GR32:$src)), 760 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 761 762// Extend GR64s to GR128s. 763let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 764 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 765 766//===----------------------------------------------------------------------===// 767// Truncations 768//===----------------------------------------------------------------------===// 769 770// Truncations of 64-bit registers to 32-bit registers. 771def : Pat<(i32 (trunc GR64:$src)), 772 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 773 774// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 775// STC, STCY or STCH, depending on the choice of register. 776def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 777 Requires<[FeatureHighWord]>; 778defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 779def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 780 Requires<[FeatureHighWord]>; 781 782// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 783// STH, STHY or STHH, depending on the choice of register. 784def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 785 Requires<[FeatureHighWord]>; 786defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 787def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 788 Requires<[FeatureHighWord]>; 789def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 790 791// Truncations of 64-bit registers to memory. 792defm : StoreGR64Pair<STC, STCY, truncstorei8>; 793defm : StoreGR64Pair<STH, STHY, truncstorei16>; 794def : StoreGR64PC<STHRL, aligned_truncstorei16>; 795defm : StoreGR64Pair<ST, STY, truncstorei32>; 796def : StoreGR64PC<STRL, aligned_truncstorei32>; 797 798// Store characters under mask -- not (yet) used for codegen. 799defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 800def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 801 802//===----------------------------------------------------------------------===// 803// Multi-register moves 804//===----------------------------------------------------------------------===// 805 806// Multi-register loads. 807defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 808def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 809def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 810def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 811 812// Multi-register stores. 813defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 814def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 815def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 816 817//===----------------------------------------------------------------------===// 818// Byte swaps 819//===----------------------------------------------------------------------===// 820 821// Byte-swapping register moves. 822def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 823def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 824 825// Byte-swapping loads. 826def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 827def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 828def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 829 830// Byte-swapping stores. 831def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 832def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 833def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 834 835// Byte-swapping memory-to-memory moves. 836let mayLoad = 1, mayStore = 1 in 837 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 838 839//===----------------------------------------------------------------------===// 840// Load address instructions 841//===----------------------------------------------------------------------===// 842 843// Load BDX-style addresses. 844let isAsCheapAsAMove = 1, isReMaterializable = 1 in 845 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 846 847// Load a PC-relative address. There's no version of this instruction 848// with a 16-bit offset, so there's no relaxation. 849let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 850 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 851 852// Load the Global Offset Table address. This will be lowered into a 853// larl $R1, _GLOBAL_OFFSET_TABLE_ 854// instruction. 855def GOT : Alias<6, (outs GR64:$R1), (ins), 856 [(set GR64:$R1, (global_offset_table))]>; 857 858//===----------------------------------------------------------------------===// 859// Absolute and Negation 860//===----------------------------------------------------------------------===// 861 862let Defs = [CC] in { 863 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 864 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 865 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 866 } 867 let CCValues = 0xE, CompareZeroCCMask = 0xE in 868 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 869} 870defm : SXU<abs, LPGFR>; 871 872let Defs = [CC] in { 873 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 874 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 875 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 876 } 877 let CCValues = 0xE, CompareZeroCCMask = 0xE in 878 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 879} 880defm : SXU<z_inegabs, LNGFR>; 881 882let Defs = [CC] in { 883 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 884 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 885 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 886 } 887 let CCValues = 0xE, CompareZeroCCMask = 0xE in 888 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 889} 890defm : SXU<ineg, LCGFR>; 891 892//===----------------------------------------------------------------------===// 893// Insertion 894//===----------------------------------------------------------------------===// 895 896let isCodeGenOnly = 1 in 897 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, azextloadi8, 1>; 898defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, azextloadi8, 1>; 899 900defm : InsertMem<"inserti8", IC32, GR32, azextloadi8, bdxaddr12pair>; 901defm : InsertMem<"inserti8", IC32Y, GR32, azextloadi8, bdxaddr20pair>; 902 903defm : InsertMem<"inserti8", IC, GR64, azextloadi8, bdxaddr12pair>; 904defm : InsertMem<"inserti8", ICY, GR64, azextloadi8, bdxaddr20pair>; 905 906// Insert characters under mask -- not (yet) used for codegen. 907let Defs = [CC] in { 908 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 909 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 910} 911 912// Insertions of a 16-bit immediate, leaving other bits unaffected. 913// We don't have or_as_insert equivalents of these operations because 914// OI is available instead. 915// 916// IIxMux expands to II[LH]x, depending on the choice of register. 917def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 918 Requires<[FeatureHighWord]>; 919def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 920 Requires<[FeatureHighWord]>; 921def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 922def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 923def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 924def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 925def IILL64 : BinaryAliasRI<insertll, GR64, imm64ll16>; 926def IILH64 : BinaryAliasRI<insertlh, GR64, imm64lh16>; 927def IIHL64 : BinaryAliasRI<inserthl, GR64, imm64hl16>; 928def IIHH64 : BinaryAliasRI<inserthh, GR64, imm64hh16>; 929 930// ...likewise for 32-bit immediates. For GR32s this is a general 931// full-width move. (We use IILF rather than something like LLILF 932// for 32-bit moves because IILF leaves the upper 32 bits of the 933// GR64 unchanged.) 934let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 935 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 936 Requires<[FeatureHighWord]>; 937 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 938 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 939} 940def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 941def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 942 943// An alternative model of inserthf, with the first operand being 944// a zero-extended value. 945def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 946 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 947 imm64hf32:$imm)>; 948 949//===----------------------------------------------------------------------===// 950// Addition 951//===----------------------------------------------------------------------===// 952 953// Addition producing a signed overflow flag. 954let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 955 // Addition of a register. 956 let isCommutable = 1 in { 957 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 958 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 959 } 960 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 961 962 // Addition to a high register. 963 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 964 Requires<[FeatureHighWord]>; 965 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 966 Requires<[FeatureHighWord]>; 967 968 // Addition of signed 16-bit immediates. 969 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 970 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 971 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 972 973 // Addition of signed 32-bit immediates. 974 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 975 Requires<[FeatureHighWord]>; 976 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 977 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 978 Requires<[FeatureHighWord]>; 979 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 980 981 // Addition of memory. 982 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, asextloadi16, 2>; 983 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, load, 4>; 984 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, asextloadi16, 2>, 985 Requires<[FeatureMiscellaneousExtensions2]>; 986 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, asextloadi32, 4>; 987 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, load, 8>; 988 989 // Addition to memory. 990 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 991 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 992} 993defm : SXB<z_sadd, GR64, AGFR>; 994 995// Addition producing a carry. 996let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 997 // Addition of a register. 998 let isCommutable = 1 in { 999 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1000 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1001 } 1002 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1003 1004 // Addition to a high register. 1005 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1006 Requires<[FeatureHighWord]>; 1007 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1008 Requires<[FeatureHighWord]>; 1009 1010 // Addition of signed 16-bit immediates. 1011 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1012 Requires<[FeatureDistinctOps]>; 1013 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1014 Requires<[FeatureDistinctOps]>; 1015 1016 // Addition of unsigned 32-bit immediates. 1017 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1018 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1019 1020 // Addition of signed 32-bit immediates. 1021 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1022 Requires<[FeatureHighWord]>; 1023 1024 // Addition of memory. 1025 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, load, 4>; 1026 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, azextloadi32, 4>; 1027 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, load, 8>; 1028 1029 // Addition to memory. 1030 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1031 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1032} 1033defm : ZXB<z_uadd, GR64, ALGFR>; 1034 1035// Addition producing and using a carry. 1036let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1037 // Addition of a register. 1038 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1039 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1040 1041 // Addition of memory. 1042 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, load, 4>; 1043 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, load, 8>; 1044} 1045 1046// Addition that does not modify the condition code. 1047def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1048 Requires<[FeatureHighWord]>; 1049 1050 1051//===----------------------------------------------------------------------===// 1052// Subtraction 1053//===----------------------------------------------------------------------===// 1054 1055// Subtraction producing a signed overflow flag. 1056let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1057 CCIfNoSignedWrap = 1 in { 1058 // Subtraction of a register. 1059 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1060 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1061 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1062 1063 // Subtraction from a high register. 1064 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1065 Requires<[FeatureHighWord]>; 1066 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1067 Requires<[FeatureHighWord]>; 1068 1069 // Subtraction of memory. 1070 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, asextloadi16, 2>; 1071 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, load, 4>; 1072 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, asextloadi16, 2>, 1073 Requires<[FeatureMiscellaneousExtensions2]>; 1074 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, asextloadi32, 4>; 1075 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, load, 8>; 1076} 1077defm : SXB<z_ssub, GR64, SGFR>; 1078 1079// Subtracting an immediate is the same as adding the negated immediate. 1080let AddedComplexity = 1 in { 1081 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1082 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1083 Requires<[FeatureHighWord]>; 1084 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1085 (AFIMux GR32:$src1, simm32n:$src2)>, 1086 Requires<[FeatureHighWord]>; 1087 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1088 (AHI GR32:$src1, imm32sx16n:$src2)>; 1089 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1090 (AFI GR32:$src1, simm32n:$src2)>; 1091 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1092 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1093 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1094 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1095} 1096 1097// And vice versa in one special case, where we need to load a 1098// constant into a register in any case, but the negated constant 1099// requires fewer instructions to load. 1100def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1101 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1102def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1103 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1104 1105// Subtraction producing a carry. 1106let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1107 // Subtraction of a register. 1108 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1109 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1110 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1111 1112 // Subtraction from a high register. 1113 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1114 Requires<[FeatureHighWord]>; 1115 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1116 Requires<[FeatureHighWord]>; 1117 1118 // Subtraction of unsigned 32-bit immediates. 1119 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1120 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1121 1122 // Subtraction of memory. 1123 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, load, 4>; 1124 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, azextloadi32, 4>; 1125 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, load, 8>; 1126} 1127defm : ZXB<z_usub, GR64, SLGFR>; 1128 1129// Subtracting an immediate is the same as adding the negated immediate. 1130let AddedComplexity = 1 in { 1131 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1132 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1133 Requires<[FeatureDistinctOps]>; 1134 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1135 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1136 Requires<[FeatureDistinctOps]>; 1137} 1138 1139// And vice versa in one special case (but we prefer addition). 1140def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1141 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1142 1143// Subtraction producing and using a carry. 1144let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1145 // Subtraction of a register. 1146 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1147 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1148 1149 // Subtraction of memory. 1150 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, load, 4>; 1151 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, load, 8>; 1152} 1153 1154 1155//===----------------------------------------------------------------------===// 1156// AND 1157//===----------------------------------------------------------------------===// 1158 1159let Defs = [CC] in { 1160 // ANDs of a register. 1161 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1162 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1163 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1164 } 1165 1166 let isConvertibleToThreeAddress = 1 in { 1167 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1168 // The CC result only reflects the 16-bit field, not the full register. 1169 // 1170 // NIxMux expands to NI[LH]x, depending on the choice of register. 1171 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1172 Requires<[FeatureHighWord]>; 1173 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1174 Requires<[FeatureHighWord]>; 1175 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1176 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1177 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1178 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1179 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1180 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1181 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1182 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1183 1184 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1185 // The CC result only reflects the 32-bit field, which means we can 1186 // use it as a zero indicator for i32 operations but not otherwise. 1187 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1188 // Expands to NILF or NIHF, depending on the choice of register. 1189 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1190 Requires<[FeatureHighWord]>; 1191 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1192 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1193 } 1194 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1195 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1196 } 1197 1198 // ANDs of memory. 1199 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1200 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, load, 4>; 1201 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, load, 8>; 1202 } 1203 1204 // AND to memory 1205 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1206 1207 // Block AND. 1208 let mayLoad = 1, mayStore = 1 in 1209 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1210} 1211defm : RMWIByte<and, bdaddr12pair, NI>; 1212defm : RMWIByte<and, bdaddr20pair, NIY>; 1213 1214//===----------------------------------------------------------------------===// 1215// OR 1216//===----------------------------------------------------------------------===// 1217 1218let Defs = [CC] in { 1219 // ORs of a register. 1220 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1221 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1222 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1223 } 1224 1225 // ORs of a 16-bit immediate, leaving other bits unaffected. 1226 // The CC result only reflects the 16-bit field, not the full register. 1227 // 1228 // OIxMux expands to OI[LH]x, depending on the choice of register. 1229 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1230 Requires<[FeatureHighWord]>; 1231 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1232 Requires<[FeatureHighWord]>; 1233 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1234 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1235 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1236 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1237 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1238 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1239 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1240 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1241 1242 // ORs of a 32-bit immediate, leaving other bits unaffected. 1243 // The CC result only reflects the 32-bit field, which means we can 1244 // use it as a zero indicator for i32 operations but not otherwise. 1245 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1246 // Expands to OILF or OIHF, depending on the choice of register. 1247 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1248 Requires<[FeatureHighWord]>; 1249 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1250 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1251 } 1252 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1253 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1254 1255 // ORs of memory. 1256 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1257 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, load, 4>; 1258 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, load, 8>; 1259 } 1260 1261 // OR to memory 1262 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1263 1264 // Block OR. 1265 let mayLoad = 1, mayStore = 1 in 1266 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1267} 1268defm : RMWIByte<or, bdaddr12pair, OI>; 1269defm : RMWIByte<or, bdaddr20pair, OIY>; 1270 1271//===----------------------------------------------------------------------===// 1272// XOR 1273//===----------------------------------------------------------------------===// 1274 1275let Defs = [CC] in { 1276 // XORs of a register. 1277 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1278 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1279 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1280 } 1281 1282 // XORs of a 32-bit immediate, leaving other bits unaffected. 1283 // The CC result only reflects the 32-bit field, which means we can 1284 // use it as a zero indicator for i32 operations but not otherwise. 1285 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1286 // Expands to XILF or XIHF, depending on the choice of register. 1287 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1288 Requires<[FeatureHighWord]>; 1289 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1290 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1291 } 1292 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1293 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1294 1295 // XORs of memory. 1296 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1297 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, load, 4>; 1298 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, load, 8>; 1299 } 1300 1301 // XOR to memory 1302 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1303 1304 // Block XOR. 1305 let mayLoad = 1, mayStore = 1 in 1306 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1307} 1308defm : RMWIByte<xor, bdaddr12pair, XI>; 1309defm : RMWIByte<xor, bdaddr20pair, XIY>; 1310 1311//===----------------------------------------------------------------------===// 1312// Combined logical operations 1313//===----------------------------------------------------------------------===// 1314 1315let Predicates = [FeatureMiscellaneousExtensions3], 1316 Defs = [CC] in { 1317 // AND with complement. 1318 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1319 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1320 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1321 } 1322 1323 // OR with complement. 1324 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1325 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1326 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1327 } 1328 1329 // NAND. 1330 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1331 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1332 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1333 } 1334 1335 // NOR. 1336 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1337 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1338 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1339 } 1340 1341 // NXOR. 1342 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1343 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1344 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1345 } 1346} 1347 1348//===----------------------------------------------------------------------===// 1349// Multiplication 1350//===----------------------------------------------------------------------===// 1351 1352// Multiplication of a register, setting the condition code. We prefer these 1353// over MS(G)R if available, even though we cannot use the condition code, 1354// since they are three-operand instructions. 1355let Predicates = [FeatureMiscellaneousExtensions2], 1356 Defs = [CC], isCommutable = 1 in { 1357 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1358 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1359} 1360 1361// Multiplication of a register. 1362let isCommutable = 1 in { 1363 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1364 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1365} 1366def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1367defm : SXB<mul, GR64, MSGFR>; 1368 1369// Multiplication of a signed 16-bit immediate. 1370def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1371def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1372 1373// Multiplication of a signed 32-bit immediate. 1374def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1375def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1376 1377// Multiplication of memory. 1378defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; 1379defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; 1380def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, 1381 Requires<[FeatureMiscellaneousExtensions2]>; 1382def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; 1383def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; 1384 1385// Multiplication of memory, setting the condition code. 1386let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1387 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, load, 4>; 1388 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, load, 8>; 1389} 1390 1391// Multiplication of a register, producing two results. 1392def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1393def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1394 Requires<[FeatureMiscellaneousExtensions2]>; 1395def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1396def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1397 1398def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1399 (MGRK GR64:$src1, GR64:$src2)>; 1400def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1401 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1402 1403// Multiplication of memory, producing two results. 1404def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; 1405def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; 1406def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, 1407 Requires<[FeatureMiscellaneousExtensions2]>; 1408def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; 1409def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; 1410 1411def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1412 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1413def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1414 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1415 1416//===----------------------------------------------------------------------===// 1417// Division and remainder 1418//===----------------------------------------------------------------------===// 1419 1420let hasSideEffects = 1 in { // Do not speculatively execute. 1421 // Division and remainder, from registers. 1422 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1423 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1424 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1425 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1426 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1427 1428 // Division and remainder, from memory. 1429 def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>; 1430 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>; 1431 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>; 1432 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>; 1433 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>; 1434} 1435def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1436 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1437def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))), 1438 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1439def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1440 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1441def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1442 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1443 1444def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1445 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1446 subreg_l32)), GR32:$src2)>; 1447def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))), 1448 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1449 subreg_l32)), bdxaddr20only:$src2)>; 1450def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1451 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1452def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))), 1453 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1454 1455//===----------------------------------------------------------------------===// 1456// Shifts 1457//===----------------------------------------------------------------------===// 1458 1459// Logical shift left. 1460defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1461def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1462def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1463 1464// Arithmetic shift left. 1465let Defs = [CC] in { 1466 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1467 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1468 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1469} 1470 1471// Logical shift right. 1472defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1473def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1474def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1475 1476// Arithmetic shift right. 1477let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1478 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1479 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1480 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1481} 1482 1483// Rotate left. 1484def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1485def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1486 1487// Rotate second operand left and inserted selected bits into first operand. 1488// These can act like 32-bit operands provided that the constant start and 1489// end bits (operands 2 and 3) are in the range [32, 64). 1490let Defs = [CC] in { 1491 let isCodeGenOnly = 1 in 1492 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1493 let CCValues = 0xE, CompareZeroCCMask = 0xE in 1494 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1495} 1496 1497// On zEC12 we have a variant of RISBG that does not set CC. 1498let Predicates = [FeatureMiscellaneousExtensions] in 1499 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1500 1501// Forms of RISBG that only affect one word of the destination register. 1502// They do not set CC. 1503let Predicates = [FeatureHighWord] in { 1504 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1505 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1506 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1507 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1508 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1509 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1510 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1511} 1512 1513// Rotate second operand left and perform a logical operation with selected 1514// bits of the first operand. The CC result only describes the selected bits, 1515// so isn't useful for a full comparison against zero. 1516let Defs = [CC] in { 1517 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1518 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1519 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1520} 1521 1522//===----------------------------------------------------------------------===// 1523// Comparison 1524//===----------------------------------------------------------------------===// 1525 1526// Signed comparisons. We put these before the unsigned comparisons because 1527// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1528// of the unsigned forms do. 1529let Defs = [CC], CCValues = 0xE in { 1530 // Comparison with a register. 1531 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1532 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1533 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1534 1535 // Comparison with a high register. 1536 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1537 Requires<[FeatureHighWord]>; 1538 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1539 Requires<[FeatureHighWord]>; 1540 1541 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1542 // depending on the choice of register. 1543 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1544 Requires<[FeatureHighWord]>; 1545 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1546 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1547 1548 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1549 // depending on the choice of register. 1550 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1551 Requires<[FeatureHighWord]>; 1552 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1553 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1554 Requires<[FeatureHighWord]>; 1555 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1556 1557 // Comparison with memory. 1558 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, asextloadi16, 2>; 1559 def CMux : CompareRXYPseudo<z_scmp, GRX32, load, 4>, 1560 Requires<[FeatureHighWord]>; 1561 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, load, 4>; 1562 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, load, 4>, 1563 Requires<[FeatureHighWord]>; 1564 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, asextloadi16, 2>; 1565 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, asextloadi32, 4>; 1566 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, load, 8>; 1567 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_asextloadi16>; 1568 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_load>; 1569 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_asextloadi16>; 1570 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_asextloadi32>; 1571 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_load>; 1572 1573 // Comparison between memory and a signed 16-bit immediate. 1574 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, asextloadi16, imm32sx16>; 1575 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, load, imm32sx16>; 1576 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, load, imm64sx16>; 1577} 1578defm : SXB<z_scmp, GR64, CGFR>; 1579 1580// Unsigned comparisons. 1581let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1582 // Comparison with a register. 1583 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1584 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1585 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1586 1587 // Comparison with a high register. 1588 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1589 Requires<[FeatureHighWord]>; 1590 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1591 Requires<[FeatureHighWord]>; 1592 1593 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1594 // or CLIH, depending on the choice of register. 1595 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1596 Requires<[FeatureHighWord]>; 1597 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1598 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1599 Requires<[FeatureHighWord]>; 1600 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1601 1602 // Comparison with memory. 1603 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, load, 4>, 1604 Requires<[FeatureHighWord]>; 1605 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>; 1606 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, load, 4>, 1607 Requires<[FeatureHighWord]>; 1608 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, azextloadi32, 4>; 1609 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>; 1610 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1611 aligned_azextloadi16>; 1612 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1613 aligned_load>; 1614 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1615 aligned_azextloadi16>; 1616 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1617 aligned_azextloadi32>; 1618 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1619 aligned_load>; 1620 1621 // Comparison between memory and an unsigned 8-bit immediate. 1622 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, azextloadi8, imm32zx8>; 1623 1624 // Comparison between memory and an unsigned 16-bit immediate. 1625 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, azextloadi16, imm32zx16>; 1626 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>; 1627 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>; 1628} 1629defm : ZXB<z_ucmp, GR64, CLGFR>; 1630 1631// Memory-to-memory comparison. 1632let mayLoad = 1, Defs = [CC] in { 1633 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1634 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1635 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1636 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1637} 1638 1639// String comparison. 1640let mayLoad = 1, Defs = [CC] in 1641 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1642 1643// Test under mask. 1644let Defs = [CC] in { 1645 // TMxMux expands to TM[LH]x, depending on the choice of register. 1646 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1647 Requires<[FeatureHighWord]>; 1648 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1649 Requires<[FeatureHighWord]>; 1650 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1651 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1652 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1653 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1654 1655 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1656 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1657 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1658 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1659 1660 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; 1661} 1662 1663def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1664def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1665 1666// Compare logical characters under mask -- not (yet) used for codegen. 1667let Defs = [CC] in { 1668 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1669 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1670} 1671 1672//===----------------------------------------------------------------------===// 1673// Prefetch and execution hint 1674//===----------------------------------------------------------------------===// 1675 1676let mayLoad = 1, mayStore = 1 in { 1677 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1678 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1679} 1680 1681let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1682 // Branch Prediction Preload 1683 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1684 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1685 1686 // Next Instruction Access Intent 1687 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1688} 1689 1690//===----------------------------------------------------------------------===// 1691// Atomic operations 1692//===----------------------------------------------------------------------===// 1693 1694// A serialization instruction that acts as a barrier for all memory 1695// accesses, which expands to "bcr 14, 0". 1696let hasSideEffects = 1 in 1697def Serialize : Alias<2, (outs), (ins), []>; 1698 1699// A pseudo instruction that serves as a compiler barrier. 1700let hasSideEffects = 1, hasNoSchedulingInfo = 1 in 1701def MemBarrier : Pseudo<(outs), (ins), [(z_membarrier)]>; 1702 1703let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1704 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_32, GR32>; 1705 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_64, GR64>; 1706 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1707 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1708 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_32, GR32>; 1709 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_64, GR64>; 1710 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_32, GR32>; 1711 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_64, GR64>; 1712 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_32, GR32>; 1713 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_64, GR64>; 1714} 1715 1716def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1717def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>; 1718def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>; 1719 1720def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1721def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1722let Predicates = [FeatureNoInterlockedAccess1] in { 1723 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>; 1724 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>; 1725 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>; 1726 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>; 1727 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>; 1728 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>; 1729} 1730 1731def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1732def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>; 1733def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>; 1734 1735def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1736def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1737let Predicates = [FeatureNoInterlockedAccess1] in { 1738 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>; 1739 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm32<atomic_load_and_32, 1740 imm32ll16c>; 1741 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm32<atomic_load_and_32, 1742 imm32lh16c>; 1743 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>; 1744 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>; 1745 def ATOMIC_LOAD_NILL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1746 imm64ll16c>; 1747 def ATOMIC_LOAD_NILH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1748 imm64lh16c>; 1749 def ATOMIC_LOAD_NIHL64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1750 imm64hl16c>; 1751 def ATOMIC_LOAD_NIHH64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1752 imm64hh16c>; 1753 def ATOMIC_LOAD_NILF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1754 imm64lf32c>; 1755 def ATOMIC_LOAD_NIHF64 : AtomicLoadBinaryImm64<atomic_load_and_64, 1756 imm64hf32c>; 1757} 1758 1759def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1760def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1761let Predicates = [FeatureNoInterlockedAccess1] in { 1762 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>; 1763 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>; 1764 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>; 1765 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>; 1766 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>; 1767 def ATOMIC_LOAD_OILL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>; 1768 def ATOMIC_LOAD_OILH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>; 1769 def ATOMIC_LOAD_OIHL64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>; 1770 def ATOMIC_LOAD_OIHH64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>; 1771 def ATOMIC_LOAD_OILF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>; 1772 def ATOMIC_LOAD_OIHF64 : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>; 1773} 1774 1775def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1776def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1777let Predicates = [FeatureNoInterlockedAccess1] in { 1778 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>; 1779 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>; 1780 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>; 1781 def ATOMIC_LOAD_XILF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>; 1782 def ATOMIC_LOAD_XIHF64 : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>; 1783} 1784 1785def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1786def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1787 imm32lh16c>; 1788def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>; 1789def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1790 imm32ll16c>; 1791def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm32<atomic_load_nand_32, 1792 imm32lh16c>; 1793def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>; 1794def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>; 1795def ATOMIC_LOAD_NILL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1796 imm64ll16c>; 1797def ATOMIC_LOAD_NILH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1798 imm64lh16c>; 1799def ATOMIC_LOAD_NIHL64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1800 imm64hl16c>; 1801def ATOMIC_LOAD_NIHH64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1802 imm64hh16c>; 1803def ATOMIC_LOAD_NILF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1804 imm64lf32c>; 1805def ATOMIC_LOAD_NIHF64i : AtomicLoadBinaryImm64<atomic_load_nand_64, 1806 imm64hf32c>; 1807 1808def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1809def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>; 1810def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>; 1811 1812def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1813def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>; 1814def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>; 1815 1816def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1817def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>; 1818def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>; 1819 1820def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1821def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>; 1822def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>; 1823 1824def ATOMIC_CMP_SWAPW 1825 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1826 ADDR32:$bitshift, ADDR32:$negbitshift, 1827 uimm32:$bitsize), 1828 [(set GR32:$dst, 1829 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1830 ADDR32:$bitshift, ADDR32:$negbitshift, 1831 uimm32:$bitsize))]> { 1832 let Defs = [CC]; 1833 let mayLoad = 1; 1834 let mayStore = 1; 1835 let usesCustomInserter = 1; 1836 let hasNoSchedulingInfo = 1; 1837} 1838 1839// Test and set. 1840let mayLoad = 1, Defs = [CC] in 1841 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1842 1843// Compare and swap. 1844let Defs = [CC] in { 1845 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1846 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1847} 1848 1849// Compare double and swap. 1850let Defs = [CC] in { 1851 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1852 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1853} 1854 1855// Compare and swap and store. 1856let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1857 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1858 1859// Perform locked operation. 1860let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1861 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1862 1863// Load/store pair from/to quadword. 1864def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1865def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1866 1867// Load pair disjoint. 1868let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1869 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1870 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1871} 1872 1873//===----------------------------------------------------------------------===// 1874// Translate and convert 1875//===----------------------------------------------------------------------===// 1876 1877let mayLoad = 1, mayStore = 1 in 1878 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1879 1880let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1881 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1882 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1883} 1884 1885let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1886 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1887 1888let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1889 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1890 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1891} 1892 1893let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1894 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1895 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1896 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1897 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1898} 1899 1900let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1901 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1902 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1903 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1904 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1905 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1906 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1907 1908 let isAsmParserOnly = 1 in { 1909 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1910 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1911 } 1912} 1913 1914//===----------------------------------------------------------------------===// 1915// Message-security assist 1916//===----------------------------------------------------------------------===// 1917 1918let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1919 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1920 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1921 1922 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1923 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1924 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1925 1926 let Predicates = [FeatureMessageSecurityAssist4] in { 1927 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1928 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1929 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1930 GR128, GR128, GR128>; 1931 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1932 } 1933 1934 let Predicates = [FeatureMessageSecurityAssist5] in 1935 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1936 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1937 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1938 1939 let Predicates = [FeatureMessageSecurityAssist8] in 1940 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1941 GR128, GR128, GR128>; 1942 1943 let Predicates = [FeatureMessageSecurityAssist9] in 1944 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1945} 1946 1947//===----------------------------------------------------------------------===// 1948// Guarded storage 1949//===----------------------------------------------------------------------===// 1950 1951// These instructions use and/or modify the guarded storage control 1952// registers, which we do not otherwise model, so they should have 1953// hasSideEffects. 1954let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1955 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1956 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1957 1958 let mayLoad = 1 in 1959 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1960 let mayStore = 1 in 1961 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1962} 1963 1964//===----------------------------------------------------------------------===// 1965// Decimal arithmetic 1966//===----------------------------------------------------------------------===// 1967 1968defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, load, 4>; 1969def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, load, 8>; 1970 1971defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1972def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1973 1974let mayLoad = 1, mayStore = 1 in { 1975 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1976 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1977 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1978 1979 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1980 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 1981 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 1982 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 1983 let Defs = [CC] in { 1984 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 1985 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 1986 } 1987} 1988 1989let mayLoad = 1, mayStore = 1 in { 1990 let Defs = [CC] in { 1991 def AP : SideEffectBinarySSb<"ap", 0xFA>; 1992 def SP : SideEffectBinarySSb<"sp", 0xFB>; 1993 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 1994 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 1995 } 1996 def MP : SideEffectBinarySSb<"mp", 0xFC>; 1997 def DP : SideEffectBinarySSb<"dp", 0xFD>; 1998 let Defs = [CC] in { 1999 def ED : SideEffectBinarySSa<"ed", 0xDE>; 2000 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 2001 } 2002} 2003 2004let Defs = [CC] in { 2005 def CP : CompareSSb<"cp", 0xF9>; 2006 def TP : TestRSL<"tp", 0xEBC0>; 2007} 2008 2009//===----------------------------------------------------------------------===// 2010// Access registers 2011//===----------------------------------------------------------------------===// 2012 2013// Read a 32-bit access register into a GR32. As with all GR32 operations, 2014// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2015// when a 64-bit address is stored in a pair of access registers. 2016def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2017 2018// Set access register. 2019def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2020 2021// Copy access register. 2022def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2023 2024// Load address extended. 2025defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2026 2027// Load access multiple. 2028defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2029 2030// Store access multiple. 2031defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2032 2033//===----------------------------------------------------------------------===// 2034// Program mask and addressing mode 2035//===----------------------------------------------------------------------===// 2036 2037// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2038let Uses = [CC] in 2039 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2040 2041// Set CC and program mask from a register. 2042let hasSideEffects = 1, Defs = [CC] in 2043 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2044 2045// Branch and link - like BAS, but also extracts CC and program mask. 2046let isCall = 1, Uses = [CC], Defs = [CC] in { 2047 def BAL : CallRX<"bal", 0x45>; 2048 def BALR : CallRR<"balr", 0x05>; 2049} 2050 2051// Test addressing mode. 2052let Defs = [CC] in 2053 def TAM : SideEffectInherentE<"tam", 0x010B>; 2054 2055// Set addressing mode. 2056let hasSideEffects = 1 in { 2057 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2058 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2059 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2060} 2061 2062// Branch and set mode. Not really a call, but also sets an output register. 2063let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2064 def BSM : CallRR<"bsm", 0x0B>; 2065 2066// Branch and save and set mode. 2067let isCall = 1, Defs = [CC] in 2068 def BASSM : CallRR<"bassm", 0x0C>; 2069 2070//===----------------------------------------------------------------------===// 2071// Transactional execution 2072//===----------------------------------------------------------------------===// 2073 2074let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2075 // Transaction Begin 2076 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2077 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2078 let hasNoSchedulingInfo = 1 in 2079 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2080 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2081 int_s390_tbeginc, imm32zx16>; 2082 } 2083 2084 // Transaction End 2085 let Defs = [CC] in 2086 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2087 2088 // Transaction Abort 2089 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2090 hasSideEffects = 1 in 2091 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2092 2093 // Nontransactional Store 2094 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2095 2096 // Extract Transaction Nesting Depth 2097 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2098} 2099 2100//===----------------------------------------------------------------------===// 2101// Processor assist 2102//===----------------------------------------------------------------------===// 2103 2104let Predicates = [FeatureProcessorAssist] in { 2105 let hasSideEffects = 1 in 2106 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2107 def : Pat<(int_s390_ppa_txassist GR32:$src), 2108 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2109 zero_reg, 1)>; 2110} 2111 2112//===----------------------------------------------------------------------===// 2113// Miscellaneous Instructions. 2114//===----------------------------------------------------------------------===// 2115 2116// Find leftmost one, AKA count leading zeros. The instruction actually 2117// returns a pair of GR64s, the first giving the number of leading zeros 2118// and the second giving a copy of the source with the leftmost one bit 2119// cleared. We only use the first result here. 2120let Defs = [CC] in 2121 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2122def : Pat<(i64 (ctlz GR64:$src)), 2123 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2124 2125// Population count. Counts bits set per byte or doubleword. 2126let Predicates = [FeatureMiscellaneousExtensions3] in { 2127 let Defs = [CC] in 2128 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2129 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2130} 2131let Predicates = [FeaturePopulationCount], Defs = [CC] in 2132 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2133 2134// Search a block of memory for a character. 2135let mayLoad = 1, Defs = [CC] in 2136 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2137let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2138 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2139 2140// Compare until substring equal. 2141let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2142 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2143 2144// Compare and form codeword. 2145let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2146 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2147 2148// Update tree. 2149let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2150 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2151 def UPT : SideEffectInherentE<"upt", 0x0102>; 2152 2153// Checksum. 2154let mayLoad = 1, Defs = [CC] in 2155 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2156 2157// Compression call. 2158let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2159 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2160 2161// Sort lists. 2162let Predicates = [FeatureEnhancedSort], 2163 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2164 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2165 2166// Deflate conversion call. 2167let Predicates = [FeatureDeflateConversion], 2168 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2169 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2170 GR128, GR128, GR64>; 2171 2172// NNPA. 2173let Predicates = [FeatureNNPAssist], 2174 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2175 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2176 2177// Execute. 2178let hasSideEffects = 1 in { 2179 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2180 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2181 let hasNoSchedulingInfo = 1 in 2182 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2183 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2184 []>; 2185} 2186 2187//===----------------------------------------------------------------------===// 2188// .insn directive instructions 2189//===----------------------------------------------------------------------===// 2190 2191let isCodeGenOnly = 1, hasSideEffects = 1 in { 2192 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2193 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2194 imm32sx16:$I2), 2195 ".insn ri,$enc,$R1,$I2", []>; 2196 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2197 AnyReg:$R3, brtarget16:$I2), 2198 ".insn rie,$enc,$R1,$R3,$I2", []>; 2199 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2200 brtarget32:$I2), 2201 ".insn ril,$enc,$R1,$I2", []>; 2202 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2203 uimm32:$I2), 2204 ".insn rilu,$enc,$R1,$I2", []>; 2205 def InsnRIS : DirectiveInsnRIS<(outs), 2206 (ins imm64zx48:$enc, AnyReg:$R1, 2207 imm32sx8:$I2, imm32zx4:$M3, 2208 bdaddr12only:$BD4), 2209 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2210 def InsnRR : DirectiveInsnRR<(outs), 2211 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2212 ".insn rr,$enc,$R1,$R2", []>; 2213 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2214 AnyReg:$R1, AnyReg:$R2), 2215 ".insn rre,$enc,$R1,$R2", []>; 2216 def InsnRRF : DirectiveInsnRRF<(outs), 2217 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2218 AnyReg:$R3, imm32zx4:$M4), 2219 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2220 def InsnRRS : DirectiveInsnRRS<(outs), 2221 (ins imm64zx48:$enc, AnyReg:$R1, 2222 AnyReg:$R2, imm32zx4:$M3, 2223 bdaddr12only:$BD4), 2224 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2225 def InsnRS : DirectiveInsnRS<(outs), 2226 (ins imm64zx32:$enc, AnyReg:$R1, 2227 AnyReg:$R3, bdaddr12only:$BD2), 2228 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2229 def InsnRSE : DirectiveInsnRSE<(outs), 2230 (ins imm64zx48:$enc, AnyReg:$R1, 2231 AnyReg:$R3, bdaddr12only:$BD2), 2232 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2233 def InsnRSI : DirectiveInsnRSI<(outs), 2234 (ins imm64zx48:$enc, AnyReg:$R1, 2235 AnyReg:$R3, brtarget16:$RI2), 2236 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2237 def InsnRSY : DirectiveInsnRSY<(outs), 2238 (ins imm64zx48:$enc, AnyReg:$R1, 2239 AnyReg:$R3, bdaddr20only:$BD2), 2240 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2241 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2242 bdxaddr12only:$XBD2), 2243 ".insn rx,$enc,$R1,$XBD2", []>; 2244 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2245 bdxaddr12only:$XBD2), 2246 ".insn rxe,$enc,$R1,$XBD2", []>; 2247 def InsnRXF : DirectiveInsnRXF<(outs), 2248 (ins imm64zx48:$enc, AnyReg:$R1, 2249 AnyReg:$R3, bdxaddr12only:$XBD2), 2250 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2251 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2252 bdxaddr20only:$XBD2), 2253 ".insn rxy,$enc,$R1,$XBD2", []>; 2254 def InsnS : DirectiveInsnS<(outs), 2255 (ins imm64zx32:$enc, bdaddr12only:$BD2), 2256 ".insn s,$enc,$BD2", []>; 2257 def InsnSI : DirectiveInsnSI<(outs), 2258 (ins imm64zx32:$enc, bdaddr12only:$BD1, 2259 imm32sx8:$I2), 2260 ".insn si,$enc,$BD1,$I2", []>; 2261 def InsnSIY : DirectiveInsnSIY<(outs), 2262 (ins imm64zx48:$enc, 2263 bdaddr20only:$BD1, imm32zx8:$I2), 2264 ".insn siy,$enc,$BD1,$I2", []>; 2265 def InsnSIL : DirectiveInsnSIL<(outs), 2266 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2267 imm32zx16:$I2), 2268 ".insn sil,$enc,$BD1,$I2", []>; 2269 def InsnSS : DirectiveInsnSS<(outs), 2270 (ins imm64zx48:$enc, bdraddr12only:$RBD1, 2271 bdaddr12only:$BD2, AnyReg:$R3), 2272 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2273 def InsnSSE : DirectiveInsnSSE<(outs), 2274 (ins imm64zx48:$enc, 2275 bdaddr12only:$BD1,bdaddr12only:$BD2), 2276 ".insn sse,$enc,$BD1,$BD2", []>; 2277 def InsnSSF : DirectiveInsnSSF<(outs), 2278 (ins imm64zx48:$enc, bdaddr12only:$BD1, 2279 bdaddr12only:$BD2, AnyReg:$R3), 2280 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2281 def InsnVRI : DirectiveInsnVRI<(outs), 2282 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2283 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2284 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2285 def InsnVRR : DirectiveInsnVRR<(outs), 2286 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2287 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2288 imm32zx4:$M6), 2289 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2290 def InsnVRS : DirectiveInsnVRS<(outs), 2291 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2292 bdaddr12only:$BD2, imm32zx4:$M4), 2293 ".insn vrs,$enc,$BD2,$M4", []>; 2294 def InsnVRV : DirectiveInsnVRV<(outs), 2295 (ins imm64zx48:$enc, VR128:$V1, 2296 bdvaddr12only:$VBD2, imm32zx4:$M3), 2297 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2298 def InsnVRX : DirectiveInsnVRX<(outs), 2299 (ins imm64zx48:$enc, VR128:$V1, 2300 bdxaddr12only:$XBD2, imm32zx4:$M3), 2301 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2302 def InsnVSI : DirectiveInsnVSI<(outs), 2303 (ins imm64zx48:$enc, VR128:$V1, 2304 bdaddr12only:$BD2, imm32zx8:$I3), 2305 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2306} 2307 2308//===----------------------------------------------------------------------===// 2309// Peepholes. 2310//===----------------------------------------------------------------------===// 2311 2312// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2313// equivalent to (and (xor x, -1), y) 2314def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2315 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2316 2317// Shift/rotate instructions only use the last 6 bits of the second operand 2318// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2319// last 16 bits. 2320// Complexity is added so that we match this before we match NILF on the AND 2321// operation alone. 2322let AddedComplexity = 4 in { 2323 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2324 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2325 2326 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2327 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2328 2329 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2330 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2331 2332 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2333 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2334 2335 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2336 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2337 2338 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2339 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2340 2341 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2342 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2343 2344 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2345 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2346} 2347 2348// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2349// use the last 6 bits of the second operand register (making it modulo 64). 2350let AddedComplexity = 4 in { 2351 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2352 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2353 2354 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2355 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2356 2357 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2358 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2359 2360 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2361 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2362} 2363 2364// Peepholes for turning scalar operations into block operations. The length 2365// is given as one less for these pseudos. 2366defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2367defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2368defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2369defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2370defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2371defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2372defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2373 2374//===----------------------------------------------------------------------===// 2375// Mnemonic Aliases 2376//===----------------------------------------------------------------------===// 2377 2378def JCT : MnemonicAlias<"jct", "brct">; 2379def JCTG : MnemonicAlias<"jctg", "brctg">; 2380def JAS : MnemonicAlias<"jas", "bras">; 2381def JASL : MnemonicAlias<"jasl", "brasl">; 2382def JXH : MnemonicAlias<"jxh", "brxh">; 2383def JXLE : MnemonicAlias<"jxle", "brxle">; 2384def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2385def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2386 2387def BRU : MnemonicAlias<"bru", "j">; 2388def BRUL : MnemonicAlias<"brul", "jg", "att">; 2389def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2390 2391foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2392 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2393 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2394 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "att">; 2395 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2396} 2397